Lecture 11: Semiconductor memory I

NVM, SRAM, DRAM

Hyeon-Min Bae

Department of Electrical Engineering

KAIST, Daejeon, Korea

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 1

Chapter Overview

q Memory Classification
q Memory Architectures
q The Memory Core
q Periphery
q Reliability
q Case Studies

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 2

Semiconductor Memory Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random
EPROM Mask-Programmed
Access Access
E2PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
CAM

Non-random are fast, ex) video memory

CAM: contents addressable memory (or associative
memory), use query style format to access memory

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 3

Memory Timing: Definitions

Read cycle == write cycle in general

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 4

Memory Architecture: Decoders

M bits M bits

S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Nwords

Word 2 Word 2

Decoder
cell A1 cell

AK2 1
SN - 2
Word N - 2 Word N 2 2
SN - 1
Word N - 1 Word N 2 1
K 5 log2N

Input-Output Input-Output
(M bits) (M bits)

Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals:
N words == N select signals
K = log2N
(only one select signal is high) Still HEIGHT >> WIDTH
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 5
Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Solution: Row decoder + Column decoder

Target
Height==Width

Amplify swing to
rail-to-rail amplitude

Selects appropriate
word

Valid for 64Kb~256Kb memories

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 6
Example

• Memory array of 4000x2000 (4096x2048)

• 2048 = 256 8-bit words
• 12bit row address
• 8bit column address

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 7

Hierarchical Memory Architecture

Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 8

Block Diagram of 4 Mbit SRAM

Clock Z-address X-address

[Hirose90]
generator buffer buffer

Predecoder and block selector

Bit line load

128 K Array Block 0

Subglobal row decoder

Subglobal row decoder

Global row decoder

Block 1
30
Block 31
Block

Transfer gate

Local row decoder

Column decoder
Sense amplifier and write driver

CS, WE I/O x1/x4 Y-address X-address

buffer buffer controller buffer buffer

32 blocks (each 128K), each block: 1024 row, 128 columns

Row (X): 10 bits, Column (Y): 7 bits, Block (Z): 5 bits
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 9
Read-Only Memory Cells

BL BL BL
VDD
WL
WL WL
1

BL BL BL

WL WL
WL
0
GND

Diode ROM MOS ROM 1 MOS ROM 2

Diode ROM: Bit line resistively grounded. WL supplies current.

MOS ROM: Sourcing/sinking current from/to local VDD/GND.

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 10

MOS OR ROM

BL[0] BL[1] BL[2] BL[3]

WL[0]
VDD
WL[1]

WL[2]
VDD

WL[3]

Vbias

Pull-down loads

Reduction of overhead by sharing VDD btw odd & even WL

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 11

MOS NOR ROM

V DD
Pull-up devices

WL [0]

GND
WL [1]

WL [2]

GND
WL [3]

BL [0] BL [1] BL [2] BL [3]

Same as psudo NMOS NOR gates

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 12
 MOS NOR ROM Layout

Cell (9.5l x 7l)

GND Programmming using the

Active Layer Only

Polysilicon
GND Metal1 on Diffusion

Metal1
Diffusion

GND routed with diffusion à big no no but density is important

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 13
MOS NOR ROM Layout

Cell (11l x 7l)

Programmming using
the Contact Layer Only

Polysilicon

Diffusion
Metal1
Metal1 on Diffusion

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 14

MOS NAND ROM

V DD
Pull-up devices

BL [0] BL [1] BL [2] BL [3]

WL [0]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row

BL goes low when selected
Advantage: No GND or VDD
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 15
MOS NAND ROM Layout

Cell (8l x 7l)

Programmming using
the Metal-1 Layer Only

No contact to VDD or GND necessary;

drastically reduced cell size
Loss in performance compared to NOR ROM

Polysilicon

Diffusion

Metal1 on Diffusion

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 16

NAND ROM Layout

Cell (5l x 6l)

Programmming using
Implants Only

Polysilicon

Threshold-altering
Area reduction at the cost of additional processes implant
Creating depletion TR to create short.
Metal1 on Diffusion

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 17

 Equivalent Transient Model for MOS NOR ROM

Model for NOR ROM V DD

BL
r word
WL Cbit

cword

• Word line parasitics

– Wire capacitance and gate capacitance
– Wire resistance (polysilicon)
• Bit line parasitics
– Resistance not dominant (metal)
– Drain and Gate-Drain capacitance

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 18

Pseudo-NMOS

Vin=VDDà VOL>0
MP IDP NMOS: Vel. Sat
PMOS: Vel. Sat
vout
MN IDN
vi
𝐼!" + 𝐼!# = 0
(
𝑉!&'$%
𝐾" 𝑉!! − 𝑉$% 𝑉!&'$ − 1 + 𝜆% 𝑉)*
2
(
𝑉!&'$+
+ 𝐾# −𝑉!! − 𝑉$+ 𝑉!&'$+ − 1 + 𝜆% (𝑉)* −𝑉!! )
2

VOL= 1.5V, VDD=2.5V & determine KN, KP

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 19
Equivalent Transient Model for MOS NAND ROM

V DD
Model for NAND ROM
BL

CL
r bit

cbit
r word
WL

cword

q Word line parasitics

§ Similar to NOR ROM
q Bit line parasitics
§ Resistance of cascaded transistors dominates
§ Drain/Source and complete gate capacitance
§ Equivalent to a long TR for large arrays. à Impractical for 8
or 16 row memories

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 20

Decreasing Word Line Delay

Driver
WL Polysilicon word line

Metal word line

(a) Driving the word line from both sides

Metal bypass

WL K cells Polysilicon word line

(b) Using a metal bypass

(c) Use silicides

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 21

Precharged MOS NOR ROM

f pre
V DD

Precharge devices

WL [0]

GND
WL [1]

WL [2]
GND
WL [3]

BL [0] BL [1] BL [2] BL [3]

PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.
Can be catastrophic in NAND ROM à why?
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 22
Non-Volatile Memories
The Floating-gate transistor (FAMOS)

Floating gate Gate

D
Source Drain

tox G

tox
S
n+ p n+_
Substrate

Device cross-section Schematic symbol

• Reduced transconductance, increased tox

• Programmable threshold
• Virtually identical to ROM structure
• Oxide thickness ~100nm

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 23

Floating-Gate Transistor Programming

FAMOS (floating gate avalance-injection MOS)

20 V 0V 5V

10 V 5V 20 V -5 V 0V -2.5 V 5V

S D S D S D

Avalanche injection Removing programming Programming results in

voltage leaves charge trapped higher V T .

• Gate voltage >10V à electrons acquire sufficient

energy to become hot à avalanch injection of electron
(traverse through first oxide layer)à trapped on the
floating gateà self limiting (field reduction)
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 24
 A “Programmable-Threshold” Transistor

Resulting threshold voltage is around 7V

Vth shift = (−∆𝑄,- )/𝐶,. , ∆𝑄,- : charge injected onto the
floating gate, 𝐶,. : capacitance btw external gate contant to
floating gate
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 25
 Erasable programmable read only memory (EPROM)

• UV radiation renders the exide slightly conductive by the

direct generation of electro-hole pairs in the material
• Erasure process is slow (~minutes)
• Limited endurance due to UV light (~ 1000 cycles)
• Large density cheap memory

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 26

FLOTOX EEPROM (Electrically erasable programmable read-only memory)

Floating gate Gate I

Source Drain

20–30 nm -10 V V GD

10 V

n1 n1
Substrate
p
10 nm

Fowler-Nordheim
FLOTOX transistor
I-V characteristic

FLOTOX: floating gate tunneling oxide

Electrically erasable programmable read-only memory à do
not need to remove
Large area and fabrication issues but long lasting.
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 27
FLOTOX EEPROM (Electrically erasable programmable read-only memory)

Floating gate Gate I

Source Drain

20–30 nm -10 V V GD

10 V

n1 n1
Substrate
p
10 nm

Fowler-Nordheim
FLOTOX transistor
I-V characteristic

• Current flows bidirectionally

• Vth can be too small (effectively depletion) when erased à
can not turn off.

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 28

EEPROM Cell

BL
Due to process variation (ftn of
thickness) à threshold control
is hard
WL
Unprogrammed transistor
might be depletion (hard to turn off)
VDD ð 2 transistor cell

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 29

Flash EEPROM

Density of EPROM and functionality of EEPROM

Control gate
Floating gate
SiO-SiN-SiO (ONO)

erasure Thin tunneling oxide

n + source n + drain
programming
p-substrate
Program mode: hot electron injection
Erase mode: Fowler-Nordheim tunneling applied to the bulk
Complex control circuits to control Vthà Extra access TR is
not required.
Similar to FAMOS but has thin tunneling oxide

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 30

Flash EEPROM

Control gate
Floating gate
SiO-SiN-SiO (ONO)

erasure Thin tunneling oxide

n + source n + drain
programming
p-substrate

Program mode: High control voltage (12V) at gate and drain

(~6V) and 0V for source
Erase mode: High Source voltage of 12V and 0V gate
Charge in floating gate: high threshold
No charge in floating gate: reg. threshold
Charge à 0, No charge à 1

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 31

NOR flash memory

𝑄,- = 𝐶,. 𝑉,- − 𝑉.- + 𝐶& 𝑉,- − 𝑉& + 𝐶! (𝑉,- − 𝑉! )+

𝐶/ (𝑉,- − 𝑉/ )
0!" .!$ .% . .
𝑉,- = + 𝑉 + 𝑉& + & 𝑉! + ' 𝑉/
.# .# .- .# .# .#

𝐶$ = 𝐶,. + 𝐶& + 𝐶! +𝐶/

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 32
NOR flash memory

If both source and bulk are grounded,

𝑄,- 𝐶,. 𝐶!
𝑉,- = + 𝑉.- + 𝑉!&
𝐶$ 𝐶$ 𝐶$

Transistor operation is determined by VT(FG) and VFG

VT(CG) is a function of VT(FG)
𝐶$ 𝑄,- 𝐶!
𝑉$ 𝐶𝐺 = 𝑉$ 𝐹𝐺 − − 𝑉!&
𝐶,. 𝐶,. 𝐶,.

Thereshold voltage is affected by QFG

∆𝑄,-
∆𝑉$ 𝐶𝐺 =
𝐶,.
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 33
Basic Operations in a NOR Flash Memory―Erase

Fowler-Nordheim tunneling for erase

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 34

Basic Operations in a NOR Flash Memory―Write

Drain voltage raisedà generation of hot electron à

injected to the floating gate

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 35

Basic Operations in a NOR Flash Memory―Read

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 36

Characteristics of State-of-the-art NVM

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 37

Read-Write Memories (RAM)

q STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential

q DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 38

6-transistor CMOS SRAM Cell

WL

V DD
M2 M4
Q
M5 Q M6

M1 M3

BL BL

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 39

CMOS SRAM Analysis (Read)

WL

V DD
BL M4
BL
Q= 0
Q= 1 M6
M5

V DD M1 V DD V DD

Cbit Cbit

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 40

CMOS SRAM Analysis (Read)

1.2
1
Voltage Rise (V)

0.8
0.6
0.4
0.2
0
0 0.5 1 1.2 1.5 2 2.5 3
Cell Ratio (CR)

CR has to be greater than 1.2 to prevent rising over VTN

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 41
CMOS SRAM Analysis (Write)

WL
V DD
M4

Q= 0 M6
M5 Q= 1

M1
V DD
BL = 1 BL = 0

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 42

CMOS SRAM Analysis (Write)

()
*)
PR= (+
*+

Pull up ratio (PR) has to be less than 1.8 to make VQ < VTN
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 43
6T-SRAM — Layout

VDD
M2 M4

Q Q
M1 M3

GND
M5 M6 WL

BL BL

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 44

Resistance-load SRAM Cell

WL
V DD
RL RL

Q Q
M3 M4

BL M1 M2 BL

Static power dissipation -- Want RL large

Bit lines precharged to V DD to address t p problem

30% Cell size reduction as compared to 6T

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 45
SRAM Characteristics

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 46

1-Transistor DRAM Cell

Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.

𝐶& + 𝐶/* 𝑉/* = 𝐶& 𝑉/1$ + 𝐶/* 𝑉+23

CS
DV = VBL – V PRE = V BIT – V PRE ------------
C S + CBL

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 47

3-Transistor DRAM Cell

BL 1 BL 2

WWL

RWL WWL

M3 RWL

M1 X X VDD 2 VT
M2
VDD
CS BL 1

BL 2 VDD 2 VT DV

No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a “1” = VWWL-VTN

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 48

DRAM Cell Observations

q 1T DRAM requires a sense amplifier for each bit line, due to

charge redistribution read-out.
q DRAM memory cells are single ended in contrast to SRAM
cells.
qThe read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
q Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
q When writing a “1” into a DRAM cell, a threshold voltage is
lost. This charge loss can be circumvented by bootstrapping
the word lines to a higher value than VDD

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 49

Sense Amp Operation

V BL V(1)

V PRE
V(1)

V(0)
Sense amp activated t
Word line activated

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 50