Department of Electrical & Electronic Engineering

Bangladesh University of Engineering & Technology

EEE458 VLSI II Laboratory

Laboratory Module 4:
Physical Design

Objectives:
In integrated circuit design, physical design is a step in the standard design cycle which follows
after the circuit design. At this step, circuit representations of the components (devices and
interconnects) of the design are converted into geometric representations of shapes which, when
manufactured in the corresponding layers of materials, will ensure the required functioning of the
components. This geometric representation is called integrated circuit layout. This step is usually
split into several sub-steps, which include both design and verification and validation of the layout.

Design Import & Timing mode setup

Floorplanning

Creating Power Mesh

Cell Placement and PreCTS Optimization

Clock Tree Synthesis and PostCTS opt.

Routing and post routing opt.

Metal and standard cell fill

Physical Verification

Modern day Integrated Circuit (IC) design is split up into Front-end design using HDLs,
functional Verification, and Back-end Design or Physical Design and verification. The next step

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 1 24/01/2024
after Physical Design is the Manufacturing process or Fabrication Process that is done in the Wafer
Fabrication Houses. Fab-houses fabricate designs onto silicon dies which are then packaged into
ICs.

Each of the phases mentioned above has Design Flows associated with them. These Design Flows
lay down the process and guide-lines/framework for that phase. Physical Design flow uses the
technology libraries that are provided by the fabrication houses. These technology files provide
information regarding the type of Silicon wafer used, the standard-cells used, the layout rules (like
DRC in VLSI), etc.

In the two previous experiment we have designed the logic of an Accumulator, we have done its
functional simulation and synthesized the netlist. All of these are related to Front-end design. In
this experiment we are going to start Physical design (Back-end) of our synthesized accumulator
netlist step-by-step as mentioned in the above flow diagram. Cadence Innovus Implementation
System will be used for that purpose.

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 2 24/01/2024
PRELAB:
Master the TCL commands by using the reference book provided. Familiarize yourself
with the tcl commands used in this labs, specially go through the files in the tcl directory
and try understand each commands.

Work Flow:
For this lab make a directory ./PnR under the /home/<group_name>/ directory.
From the ./PnR directory, type following commands with given order to invoke Cadence Innovus,

cd /home/<group_name>/PnR
csh
innovus

The command innovus (no &) starts Innovus Implementation System in the foreground and you
should get the encounter start up window:

The window has three main areas:

• Menu Bar (top)
• Select Bar (right)
• Display Area (middle)

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 3 24/01/2024
Please try to familiarize yourself with the main window, click on the menus, on the Toolbar
widgets, etc. For more information on the various Cadence tools I encourage you to read the
corresponding manuals. You can get to the menu reference manual by pressing Help on the right of
the Menu Bar.

1. Design Import & Timing mode setup

Now we can start using Innovus. First, we need to import the synthesized netlist (the result of RTL
synthesis with Genus). The purpose of this step is to import following items and bind them to the
design (checking coherence among them).

1) Our synthesized verilog netlist

2) Technology lef file
3) Standard cell lef file
4) Standard cell liberty files (through setting up timing mode)

Click on File → Import Design and the Design Import window should pop-up. Now you need to
fill in the Verilog netlist (use the browser button on the right to navigate to your synthesized netlist

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 4 24/01/2024
that you have generated in the previous class, in this case /home/vlsi20/RTL_synthesis/alu_synth.v ,
make sure you click on Add. Now click Top Cell →By user and type alu as top cell. Next click the
Load button of the design import window and click on map.conf and click OK. Make sure that the
following appears.

Now you need to add lef files. To do so click in the "LEF Files" under "Technology/Physical
Libraries" section. Now navigate to /home/cad/VLSI2Lab/Digital/library folder then select
gsclib045_tech.lef & gsclib045_macro.lef files and then click on the "Add" button. Remember,
selection order is important here.

Now in the Power section type VDD as Power Nets and VSS as Ground Nets.

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 5 24/01/2024
Next in the "Analysis Configuration" section in "MMMC View Definition File" click in the
browser button and navigate to /home/cad/VLSI2Lab/Digital/PnR folder and then select alu.view
file. Now your "Design Import" window should look like the above screenshot.

Finally click on OK in your Design Import pop-up window and import statistics should be shown in
the innovus shell. Get familiar with some of the widgets in the layout, for example the Design
Browser widget (the 9th from the right, top row) lets you see the design hierarchy, etc.

2. Floorplanning

Floorplanning is the area budgeting of the chip. We can specify floorplan in two ways

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 6 24/01/2024
 a) By specifying Aspect ratio and core utilization ratio
b) By explicitly specifying the width and height of the die/core

In this step we will specify floorplan information and add IO ports. Since our design is simple and
flat there is not much that needs to be done, but in general now is the time to decide how the big
blocks that make up the design should be placed with respect to each other. Click on Floorplan→
Specify Floorplan and click Die size by height and width. Change height and width value as
specified in the below picture. Also change Core to Left, Core to Right, Core to Top and Core to
Bottom. Then press apply.

You layout window should look like this,

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 7 24/01/2024
Now we will add IO ports in the design. To do so source IO pin file in the innovus command shell,

source /home/cad/VLSI2Lab/Digital/PnR/floorplan_iopins.tcl

Your layout should loop like below now. Please explore IO file commands for your own sake.

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 8 24/01/2024
3. Creating Power Mesh

To make sure power uniformity throughout the design separate power stripes for VDD and VSS
need to be created in higher metal layer. To do so click on and fill up the window following below
picture and click apply.
Power → Power Planning →Add Stripe

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 9 24/01/2024
Your layout should look like below now. You can use ruler to verify stripe width and spacing.

Now we will add standard cell M1 layer rail in the design. To do so click on
Route→Special Route and fill SRoute window as specified below,

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 10 24/01/2024
Restore you design by running the following command

$source your_last_saved_design_name.enc

start Innovus and from Innovus GUI execute

File--> Restore Design --> Click Innovus and now input the last saved file
(your_last_saved_design_name.enc) by browsing.

Now type following commands to logically connect M1 rails to respective M4 stripe,

globalNetConnect VDD -type pgpin -pin VDD -inst *

globalNetConnect VSS -type pgpin -pin VSS -inst *

After that your layout will be like below. You can see M1 horizontal rail has created.

Please don’t forget to save your design at this step. You can save design using following command,
saveDesign db/mesh.enc

4. Placement

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 11 24/01/2024
Now we need to place standard cells in the design and optimize placement. Tool optimize cell
placement following minimizing congestion and wire length. To do so run following command in
the Innovus command shell, place_opt_design now your layout will look like below picture. You
can see that your design got routed too. It’s because, to optimize the design tool invokes trialRoute
command.

Now, save the design, saveDesign db/placed.enc

5. Clock Tree Synthesis (CTS)

Now we need to synthesize clock tree for this accumulator design. To do so first we have to set
clock route and clock tree settings.

Create a route type to define NDR and layers to use for routing the clock rule

create_route_type -name clkroute -bottom_preferred_layer Metal3 -top_preferred_layer Metal4

Specify this route type should be used for trunk and leaf levels,

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 12 24/01/2024
set_ccopt_property route_type clkroute -net_type trunk
set_ccopt_property route_type clkroute -net_type leaf

Specify the buffers, inverters and clock gating cells to use,

set_ccopt_property buffer_cells {CLKBUFX8 CLKBUFX12}

set_ccopt_property inverter_cells {CLKINVX8 CLKINVX12}
set_ccopt_property clock_gating_cells TLATNTSCA*

Generate the ccopt spec file and source it,

create_ccopt_clock_tree_spec -file ccopt.spec
source ccopt.spec

Now, run CCOpt-CTS,

ccopt_design -cts

Now you can do a post CTS optimization and timing analysis using following commands and save.
optDesign -postCTS
timeDesign -postCTS
saveDesign db/cts.enc

Use report_timing command to generate timing reports if needed.

6. Running NanoRoute
Though timing is already closed in this design we need to know Nanoroute approach. In general,
timing is not closed on a design unless crosstalk is prevented, analysed and then fixed. To really
achieve the above, the design is run with global and detail routing using NanoRoute. When running
NanoRoute, we enable both the Timing Driven and SI Driven (Signal Integrity) options in the
NanoRoute form. These options are important in helping to close timing and preventing crosstalk.
Select, Route→NanoRoute→Route and then select options as shown below.

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 13 24/01/2024
7. Post-Route timing and SI Optimization
The design is fully routed and timing analysis should be run to analyze timing based on the actual
routes. At the Innovus prompt run Post-Route timing analysis to report any setup or hold violations.
The following increases the RC extraction effort level to medium so turboQRC is run which
correlates better to signoff extraction. Note an effort level of medium or higher requires a QRC
technology file and effort level of high or signoff also requires a QRC license.
Analyze post-route timing,

setExtractRCMode -engine postRoute

setExtractRCMode -effortLevel high
setAnalysisMode -analysisType onChipVariation -cppr both
timeDesign -postRoute
timeDesign -postRoute -hold

You can run setup and hold optimization simultaneously to fix any remaining violations,
optDesign -postRoute -setup -hold
Now we need to verify design for design rule checks (DRC). To do so select, Verify→Verify
Geometry→OK

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 14 24/01/2024
Now you can save the routed design if you do not have any DRC violations (check shell log),
saveDesign db/postroute.enc
8. Adding filler cell and metal filling
In order to avoid DRC errors later, it is usually a good idea to place fill cells to fill in the gaps
between your placed standard cells. This also provides mechanical stability and substrate
uniformity of your chip. To do this, go to Place → Physical cell → Add Filler... and in the
window, that comes up, press the top Select button next to the Cell Name(s) form. A window will
pop up and in the right column you should see 7 filler cell libraries. Select all the libraries from the
right side, click Add followed by OK. In the Add Filler window you should now see all the filler
cell libraries in the top form. Click Apply followed by OK.

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 15 24/01/2024
Now Route → Metal fill → Add, and select ‘Layer Selection’ options as shown below,

After metal fill of empty space, the layout will look like this

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 16 24/01/2024
Now do verifyConnectivity, verifyGeometry again and save the design,
saveDesign db/filled.enc

9. Exporting Data
Now we are going to export GDS & netlist to run DRC and LVS in Virtuoso Assura. Do following,
source /home/cad/VLSI2Lab/Digital/PnR/export_gds.tcl
this will generate two files accu.lvs_netlist.vg & acc.merged.gds in your run directory.

10. Run DRC

Now we will import this gds acc.merged.gds in Cadence virtuoso and cross check DRC result.
Invoke virtuoso from your run directory by typing ‘virtuoso &’. Now select File→Import→Stream.
A virtuoso XStream In window will pop up. Now fill up the windows as shown below and then
apply.

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 17 24/01/2024
GDS should be imported in the virtuoso without any error (ignore warnings). Now to open layout
select File→Open-->, a will pop up. From the right side of that window under Cells box select accu
and in the View option select Layout, then click OK. Your accumulator gds should show up. Now
type E and a display options will pop up. At the bottom of that windows under ‘Display Level’ at
‘Stop’ box type 32, then click OK.

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 18 24/01/2024
Now in the ‘Virtuoso Layout Suite L’ window at the left side panel under ‘Objects’ untick Label.
Then your layout window should look like this.

Please explore different layers from the layer selection panel at the left side and make yourself
familiar with it. This is a great opportunity for you to visualize physical view of different metal
layers, polysilicon, oxides, impurities, substrates, wells etc.

Now to run DRC you have to invoke PVS plugin first. To do so select Launch→Plugins→PVS.
After that you will find another tab in the top Menu bar named PVS (second from right). Now
select, PVS→Run DRC. A window will show up,

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 19 24/01/2024
In the ‘Run Data’ sheet under ‘Run Directory’ box set ‘./’ (current directory).

Now select ‘Rules’ sheet. In the ‘Technology mapping file’ box browse and navigate to
“/home/cad/VLSI2Lab/Analog/pvtech.lib” file. Then select ‘gpdk045_pvs’ as Technology. Let
‘Rule Set’ as default. Now it will look like below,

Now select red ‘Submit’ button at the bottom left corner. If your design doesn’t have any DRC
error then it will show a log like below,

After that you need to verify LVS of your design. If you get now DRC & LVS error then
CONGRATULATIONS! you are good to go for fabricating your chip in any semiconductor
foundry like TSMC, GLOBALFOUNDRIES after adding IO pads and packaging.

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 20 24/01/2024
If you get DRC/LVS error at last step then you need to load database in Innovus and fix reported
violations. Then you will need to export gds again and verify DRC & LVS until they come out
clean. Same approach is followed for timing closure also.

To sum up, we have done physical design (place & route), timing and physical verification in this
experiment. We started with our synthesized netlist from previous sessional class and ended up
with our tapeout quality signoff gds of accumulator. In semiconductor industry, this gds is then sent
to semiconductor foundry for fabrication.

We have followed a very simplified design flow in this experiment. Still lots of terms may seem
new to you. To have a better understanding you are encouraged to browse following websites,

➢ http://www.vlsi-expert.com/
➢ http://mantravlsi.blogspot.com/
➢ http://vlsi.pro/

©ABM H. Rashid (79) and Sazadur Rahman (08), EEE, BUET Page 21 24/01/2024