TM

CD14538BMS
CMOS Dual Precision
November 1994
Monostable Multivibrator

Features Description
• High-Voltage Type (20V Rating) CD14538BMS dual precision monostable multivibrator provides stable retrigger-
• Retriggerable/Resettable Capability able/resettable one-shot operation for any fixed-voltage timing application.
• Trigger and Reset Propagation Delays Inde- An external resistor (RX) and an external capacitor (CX) control the timing and
pendent of RX, CX accuracy for the circuit. Adjustment of RX and CX provides a wide range of out-
• Triggering From Leading or Trailing Edge put pulse widths from the Q and Q terminals. The time delay from trigger input to
• Q and Q Buffered Outputs Available output transition (trigger propagation delay) and the time delay from reset input
to output transition (reset propagation delay) are independent of RX and CX. Pre-
• Separate Resets
cision control of output pulse widths is achieved through linear CMOS tech-
• Wide Range of Output-Pulse Widths niques.
• Schmitt-Trigger Input Allows Unlimited Rise
Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) inputs are pro-
and Fall Times On +TR and -TR Inputs
vided for triggering from either edge of an input pulse. An unused +TR input
• 100% Tested For Maximum Quiescent Cur- should be tied to VSS. An unused -TR input should be tied to VDD. A RESET
rent at 20V (on low level) is provided for immediate termination of the output pulse or to pre-
• Maximum Input Current of 1µA at 18V Over vent output pulses when power is turned on. An unused RESET input should be
Full Package-Temperature Range: tied to VDD. However, if an entire section of the CD14538BMS is not used, its
- 100nA at 18V and +25oC inputs must be tied to either VDD or VSS. See Table 1.
• Noise Margin (Full Package-Temperature In normal operation the circuit retriggers (extends the output pulse one period)
Range): on the application of each new trigger pulse. For operation in the non-retrigger-
- 1V at VDD = 5V able mode, Q is connected to -TR when leading-edge triggering (+TR) is used
- 2V at VDD = 10V or Q is connected to +TR when trailing-edge triggering (-TR) is used. The time
- 2.5V at VDD = 15V period (T) for this multivibrator can be calculated by: T = RXCX.
• 5V, 10V and 15V Parametric Ratings The minimum value of external resistance, RX is 4KΩ. The minimum and maxi-
• Standardized Symmetrical Output Charac- mum values of external capacitance, CX, are 0pF and 100µF, respectively.
teristics The CD14538BMS is interchangeable with type MC14538 and is similar to and
• Meets All Requirements of JEDEC Tentative pin-compatible with the CD4098B* and CD4538B**.
Standards No. 13B, “Standard Specifica- * T = 0.5 RXCX for C X ≥ 1000pF.
tions for Description of “B” Series CMOS * T = RXCX; CX min = 5000pF.
Device’s
The CD14538BMS is supplied in these 16-lead outline packages:
Applications Braze Seal DIP H4X
• Pulse Delay and Timing Frit Seal DIP H1L
• Pulse Shaping Ceramic Flatpack H6W

Pinout Functional Diagram

CX1 RX1
CD14538BMS VDD
TOP VIEW
1 2 RXCX(1)

CX1 1 16 VDD +TR 4 6 Q1

RXCX (1) 2 15 CX2 -TR 5
MONO1
RESET (1) 3 14 RXCX (2) RESET 3 7 Q1
+TR (1) 4 13 RESET (2)

-TR (1) 5 12 +TR (2) +TR 12 10 Q2

Q1 6 11 -TR (2) -TR 11

MONO2
Q1 7 10 Q2 RESET 13 9 Q2

VSS 8 9 Q2
15 14 RXCX(2)
VDD = 16
VSS = 8 VDD
CX2 RX2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
FN3192
Copyright © Intersil Americas Inc. 2002. All Rights Reserved 7-640
 Specifications CD14538BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Maximum Package Power Dissipation (PD) at +125 C o

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25 C o
- 10 µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55 Co
- 10 µA
oC
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25 -100 - nA
oC
2 +125 -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
oC
2 +125 - 1000 nA
oC
VDD = 18V 3 -55 - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25 0.53 - mA
oC
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
oC
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25 - -0.53 mA
oC
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25 - -1.8 mA
oC
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25 - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
oC
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25 -2.8 -0.7 V
oC
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25 0.7 2.8 V
oC
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25 VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs

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 Specifications CD14538BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (Note 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 600 ns
+TR or -TR to Q or Q TPLH1 oC,
10, 11 +125 -55oC - 810 ns
o
Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND 9 +25 C - 500 ns
Reset to Q or Q TPLH2 oC,
10, 11 +125 -55oC - 675 ns
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH oC,
10, 11 +125 -55oC - 270 ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA
+125 C o
- 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 o
-55 C, +25 C o
- 10 µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125 oC
- 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 4.95 - V
-55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 9.95 - V
-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
o
-55 C 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
oC
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
o
-55 C - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA
oC
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125 - -2.4 mA
-55oC - -4.2 mA
o o
Input Voltage Low VIL1 VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25 C, +125 C, - 3 V
-55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1, 2 +25oC, +125oC, +7 - V
1V -55oC

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 Specifications CD14538BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
o
Propagation Delay +TR TPHL1 VDD = 10V 1, 2, 3 +25 C - 300 ns
OR -TR to Q or Q TPLH1 oC
VDD = 15V 1, 2, 3 +25 - 220 ns
Propagation Delay Reset TPHL2 VDD = 10V 1, 2, 3 +25oC - 250 ns
to Q or Q TPLH2 oC
VDD = 15V 1, 2, 3 +25 - 190 ns
oC
Transition Time TTHL VDD = 10V 1, 2, 3 +25 - 100 ns
TTLH
VDD = 15V 1, 2, 3 +25oC - 80 ns
Output Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 230 µs
Q or Q
VDD = 10V 1, 2, 3 +25oC - 232 µs
C X =.002µF, RX = 100K
VDD = 15V 1, 2, 3 o
+25 C - 234 µs
Output Pulse Width TW 1, 2, 3 +25oC - 10.5 ms
C X = 0.1µF
VDD = 10V 1, 2, 3 +25oC - 10.6 ms
R X = 100K
o
VDD = 15V 1, 2, 3 +25 C - 10.6 ms
o
Output Pulse Width TW VDD = 5V 1, 2, 3 +25 C - 1.06 s
C X = 10µF
VDD = 10V 1, 2, 3 +25oC - 1.06 s
R X = 100K
oC
VDD = 15V 1, 2, 3 +25 - 1.07 s
oC
Minimum Retrigger Time TRR VDD = 5V 1, 2, 3 +25 0 - ns
VDD = 10V 1, 2, 3 +25oC 0 - ns
o
VDD = 15V 1, 2, 3 +25 C 0 - ns
o
Minimum Input Pulse TW VDD = 5V 1, 2, 3 +25 C - 140 ns
Width
VDD = 10V 1, 2, 3 +25oC - 80 ns
+TR, -TR, or Reset
VDD = 15V 1, 2, 3 +25oC - 60 ns
o
Input Capacitance CIN Any Input 1, 2 +25 C - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25 oC
- 25 µA
o
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25 C -2.8 -0.2 V
N Threshold Voltage ∆VNTH VDD = 10V, ISS = -10µA 1, 4 +25 oC
- ±1 V
Delta
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VPTH VSS = 0V, IDD = 10µA 1, 4 o
+25 C - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

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 Specifications CD14538BMS

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
Static Burn-In 1 6, 7, 9, 10 1, 3 - 5, 8, 11 - 13, 2, 14, 16
(Note 1) 15
Static Burn-In 2 6, 7, 9, 10 1, 8, 15 2 - 5, 11 - 13, 14,
(Note 1) 16
Dynamic Burn- - 1, 4, 8, 12, 15 2, 14, 16 6, 7, 9, 10 5, 11 3, 13
In (Note 1)
Irradiation 2, 6, 7, 9, 10, 14 1, 8, 15 3 - 5, 11 - 13, 16
(Note 2)
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V

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 Specifications CD14538BMS

TABLE 9. FUNCTIONAL TERMINAL CONNECTIONS

VDD TO TERM # VSS TO TERM # INPUT PULSE TO TERM # OTHER CONNECTIONS

FUNCTION MONO1 MONO2 MONO1 MONO2 MONO1 MONO2 MONO1 MONO2
Leading-Edge Trigger/ 3, 5 11, 13 4 12
Retriggerable
Leading-Edge Trigger/ 3 13 4 12 5-7 11 - 9
Non-Retriggerable
Trailing-Edge Trigger/ 3 13 4 12 5 11
Retriggerable
Trailing-Edge Trigger/ 3 13 5 11 4-6 12 - 10
Non-Retriggerable
NOTE:
1. A triggerable one-shot multivibrator has an output pulse width
INPUT PULSE TRAIN
which is extended one full time period (T) after application of
the last trigger pulse.
RETRIGGERABLE MODE PULSE
2. A non-triggerable one-shot multivibrator has a time period (T) WIDTH (+TR MODE) T
referenced from the application of the first trigger pulse.
NON-RETRIGGERABLE MODE
PULSE WIDTH (+TR MODE)

Power-Down Mode VDD

During a rapid power-down condition, as would occur with a IN5395

OR RX
power-supply short circuit or with a poorly filtered power sup- EQUIVALENT 2(14) 16
ply, the energy stored in CX could discharge into Pin 2 or 14.
To avoid possible device damage in this mode, when C X is ≥ +
CX 1(15) 8
0.5 microfarad, a protection diode with a 1-ampere or higher
≥ 0.5µfd
rating (1N5395 or equivalent) and a separate ground return
VSS VSS
for CX should be provided as shown in Figure 1.
An alternate protection method is shown in Figure 2, where a FIGURE 1. RAPID POWER-DOWN PROTECTION CIRCUIT
51-ohm current-limiting resistor is inserted in series with C X. VDD
Note that a small pulse width decrease will occur however,
and RX must be appropriately increases to obtain the origi- RX
2(14) 16
nally desired pulse width.
51 OHMS
+ 1(15) 8
CX
≥ 0.5µfd VSS

FIGURE 2. ALTERNATE RAPID POWER-DOWN PROTECTION

CIRCUIT

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

645
 CD14538BMS

Logic Diagram
16

VDD
VDD VDD
VDD
RX VDD
COMP
I
2(14) R4 7 (9)
+ R2 COMP
- II Q
+
CX -
R3 R1
1(15)
VSS

VDD
8 VSS VDD
HIGH Z VSS
Q
6 (10)

VSS VDD
* 3(13)
R VDD
4(12)
*
TR D R1 R2 Q
FF
CL Q *ALL INPUTS ARE
5(11) CL PROTECTED BY CMOS
* CL
TR PROTECTION NETWORK
R1
VSS
VDD CL
p
R2 Q
VCC n
CL CL
=
CL
p p
R2
VSS VSS n n
Q
R1
CL FF DETAIL CL

FIGURE 3. 1/2 OF DEVICE SHOWN

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS

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 CD14538BMS

Typical Performance Characteristics (Continued)

DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15 -10 -5 0 -15 -10 -5 0
0 0
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10 -5

-15

-10V -10V
-20 -10

-25

-15V -15V
-30 -15

FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS

RESETPROPAGATION DELAY TIME (tPHL, tPLH) -ns

+TR, -TR PROPAGATION DELAY TIME (tPHL, tPLH)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

-ns

400 400
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V
300 300

200 200
10V 10V

15V 15V
100 100

0 20 40 60 80 100 0 20 40 60 80 100
LOAD CAPACITANCE (CL) pF LOAD CAPACITANCE (CL) pF
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNC-
OF LOAD CAPACITANCE (+TR OR -TR TO Q OR Q) TION OF LOAD CAPACITANCE (RESET TO Q OR Q)
PULSE WIDTH VARIATION - PERCENT NORMALIZED

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25o C

3
TRANSITION TIME (tTHL, tTLH) (ns)

2
200
1
TO VDD = 10V

SUPPLY VOLTAGE (VDD) = 5V

150 0

-1
100
10V
-2
15V
50
-3

0
0 20 40 60 80 100 4 6 8 10 12 14 16 18 20
LOAD CAPACITANCE (CL) (pF) VDD SUPPLY VOLTAGE (VOLTS)
FIGURE 10. TYPICAL TRANSITION TIME AS A FUNCTION OF FIGURE 11. TYPICAL PULSE-WIDTH VARIATION AS A
LOAD CAPACITANCE FUNCTION OF SUPPLY VOLTAGE

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 CD14538BMS

Typical Performance Characteristics

TYPICAL PULSE WIDTH VARIATION - PERCENT (Continued)

TYPICAL PULSE WIDTH VARIATION - PERCENT

NORMALIZED TO VDD = 10V, TA = 25oC

NORMALIZED TO VDD = 10V, TA = 25 oC

3 3

SUPPLY VOLTAGE (VDD) = 5V

2 SUPPLY VOLTAGE (VDD) = 15V 2

1 1
10V 10V

0 0
5V
-1 5V
-1

-2 -2

-3 -3

-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE (o C) AMBIENT TEMPERATURE (oC)
FIGURE 12. TYPICAL PULSE-WIDTH VARIATION AS A FUNCTION FIGURE 13. TYPICAL PULSE-WIDTH VARIATION AS A FUNCTION
OF TEMPERATURE (RX = 100 KΩ, CX = 0.1µF) OF TEMPERATURE (RX = 100 KΩ, CX = 2000pF)

6 8
CL = 50pF, RL = 200KΩ 6 RX = 100KΩ
4
2 RX = 100KΩ 4 TA = +25oC
1000 8 AMBIENT TEMPERATURE (TA) =25 oC 2
TOTAL SUPPLY CURRENT (µA)

6 ONE MONOSTABLE OPERATING

IDD CURRENT (µA) 50% DC

4 1000
2 8 SUPPLY VOLTAGE (VDD) = 15V
100 8 6
6 4
4
2 2 10V
10V
100
10 8 8
6 15V 6
4 4
2 18V
1 8 2
6
4 10 5V
2 SUPPLY VOLTAGE 8
(VDD) = 5V 6
0.1 8 4
6
4 2
2
0.01 0
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
0.0001 0.001 0.01 0.1 1 10 100 10 100 1000 10K 100K
OUTPUT DUTY CYCLE (%) CX CAPACITANCE (pfs)

FIGURE 14. TYPICAL TOTAL SUPPLY CURRENT AS A FUNC- FIGURE 15. TYPICAL TOTAL SUPPLY CURRENT AS A FUNC-
TION OF OUTPUT DUTY CYCLE TION OF LOAD CAPACITANCE

Chip Dimension and Pad Layout

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)

7-648