Fully Automated Traffic Light Controller system for

a four-way intersection using Verilog

2022 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) | 978-1-6654-9781-7/22/$31.00 ©2022 IEEE | DOI: 10.1109/CONECCT55679.2022.9865755

Pranaav Jothi M Srivatsan M Krishna Kumar P

Department of Electronics Engineering Department of Electronics Engineering Department of Electronics Engineering
Madras Institute of Technology Madras Institute of Technology Madras Institute of Technology
Anna University Anna University Anna University
Chennai, India Chennai, India Chennai, India
[email protected] [email protected] [email protected]

Prakash P Kasthuri P
Department of Electronics Engineering Department of Electronics Engineering
Madras Institute of Technology Madras Institute of Technology
Anna University Anna University
Chennai, India Chennai, India
[email protected] [email protected]

Abstract—Traffic lights are placed in roads to control the high performance. It is used in systems so as to have
flow of traffic and to prevent accidents. This paper proposes a optimum power consumption.
Moore machine based fully automated and efficient traffic
light controller system for four-way intersection. The system is There are different types of traffic control systems which
designed on Xilinx Artix-7 xc7a100tcsg324-1 FPGA using are put forth by researchers for different real time situations.
Xilinx Vivado and Verilog Hardware Description Language. A traffic light controller was designed using Verilog HDL
The designed system runs up to a maximum operating considering two roads [1] and for a T-junction [2]. A system
frequency of 10 MHz. for four-way intersection was implemented using two
signals, red and green [3]. Another system makes use of
Keywords— Field Programmable Gate Array, Finite State three signals, red, yellow and green to regulate the traffic [4].
Machine, Hardware Description Language, Light Emitting But the drawback of these systems for four-way intersection
Diode, Verilog. was that they don’t allow the maximum possible movement
of vehicles across the intersection [3][4]. Vehicles from few
roads are made to wait at the intersection unnecessarily as
I. INTRODUCTION allowing them doesn’t disturb the moving vehicles. The
Traffic congestion is one of the predominant problems proposed system makes sure that this drawback is removed
prevailing in cities and towns. In T-intersection and four-way to allow the maximum transportation of vehicles across the
intersection, the probabilities of accidents are slightly higher. intersection and to prevent the unnecessary waiting time of
So, to ensure smooth flow of traffic and to avoid road the motorists.
accidents, traffic light systems are used. Moore model of Finite State Machine (FSM) is used to
The proposed traffic light controller system is designed design the traffic light controller system as the output of the
for four-way intersection roads. In this system, the waiting system (traffic light signals) depends only upon the current
time of vehicles at the intersection is reduced by a great state of the system. This feature makes the system fully
extent. Microcontroller and Microprocessor based traffic automated. The system considers the four roads to have
light systems are already present. But the disadvantage equal traffic and makes use of the Binary encoding scheme.
associated with these systems is that, they work on fixed Compared to other works, the proposed system is more
time, and doesn’t have flexibility. So, this paper concentrates efficient by making use of minimal number of states which
on developing a reconfigurable traffic light controller are necessary enough to allow the maximum transportation
system, which works on Field Programmable Gate Array of vehicles across the intersection. The reduction in number
(FPGA) as it doesn’t have a fixed hardware structure and can of states also helps in achieving minimal power
be reprogrammed by using Hardware Description Language consumption. The traffic controller system also makes use
(HDL). Verilog is chosen for modelling the traffic light of the maximum possible number of safe states. Before the
controller system, as usage of Verilog HDL allows to define stoppage of traffic across each direction, yellow signal is
the specifications of the parameters used in the design of the displayed in the corresponding displays which indicate that
system. Also, Verilog HDL is one of the commonly used the flow of traffic will be stopped in few seconds. The states
HDLs as it has simple syntax and it resembles software containing yellow signals act as safe states and prevent the
programming languages to some extent. possibility of accidents. A Simulation based system is
designed and the same is done using Xilinx Vivado.
FPGA boards have many input switches and output Light Complete information of the system designed is obtained
Emitting Diodes (LEDs) in it, which make it suitable for the using various facilities present in this software like timing
design of traffic light controller systems. FPGAs are used for report, utilization report, power report, etc.
designing prototypes for many electronic applications.
Another advantage of FPGA is that, it makes the whole
system more efficient. The FPGA chosen here is Artix-7, II. METHODOLOGY
which is a product of Xilinx, a semiconductor manufacturing
company. Artix-7 is preferred as it is cost efficient and for its The paper concentrates on developing a traffic light
controller system for a four-way intersection. Each road has
three light displays corresponding to the flow of traffic
978-1-6654-9781-7/22/$31.00 ©2022 IEEE

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towards the other three roads. Hence there are twelve light
D8
displays in total at the intersection. By using a common
control logic, the system is designed in such a way that,
certain light displays operate in the same manner. This D9
simplifies the design with ten light displays. Each of these
light displays have the provision to show red, green and
yellow signals. The red signal specifies to stop, the green
signal allows the flow of traffic and the yellow signal B. State assignment
specifies that the flow of traffic will be stopped in few Based on the 10 light displays and according to the
seconds. The proposed system helps to prevent vehicle movement of the vehicles, 12 different states are used for
collisions at the intersection by use of ‘safe’ states. The red, traffic control. The assignment of states is given in Fig. 1.
yellow and green signals of each of the light displays are
modeled as individual output LEDs. So a total of thirty
output LEDs are used. A state diagram and a state table are
constructed based upon the simplified logic to model a finite
state machine for the proposed traffic light controller system.

III. IMPLEMENTATION OF TRAFFIC LIGHT CONTROLLER

SYSTEM

A. Light Display assignment

The proposed traffic light controller system is designed to
operate at a maximum frequency of 10.0 MHz. The time
period (T) of the clock used in this system is given by the
formula
(1)

Where f is the maximum operating frequency of the

system. The ten light displays are labelled as D0, D1, D2,
D3, D4, D5, D6, D7, D8 and D9 respectively. Light displays
are assigned according to the direction of traffic flow. Two
directions are grouped together in D0 and D2 states instead Fig. 1. Assignment of states
of employing separate light displays representing the traffic C. State Diagram
flow along those directions. Table I represents the
assignment of light displays according to the directions of The vehicle movement during the even states such as
flow of traffic. S0, S2, S4, S6, S8 and S10 are comparatively higher than
that during the odd states such as S1, S3, S5, S7, S9 and
TABLE I. LIGHT DISPLAYS AND THE CORRESPONDING
DIRECTIONS S11. So, the green signal timing for even states are set to be
more than that of odd states. The signal timing for even
Direction name Corresponding movement of vehicles at the states are set to 10 seconds and for odd states, the signal
intersection
timing is set to 5 seconds. This implies that during the even
D0 states, the present state of the displays will continue for 10
seconds and when the time exceeds 10 seconds, the system
goes into the succeeding odd state. Similarly, in odd states,
D1
the present status of the displays will continue for 5 seconds
and when the time exceeds 5 seconds, it moves into the
succeeding even state. After S11 state, the system again
D2
enters into S0 state and this cycle continues. The time taken
for the system to complete one full cycle is 90 seconds. The
D3 system also makes use of Reset signal. Once the system
detects the Reset signal, the system enters into the initial
state S0. Fig. 2 illustrates the state diagram of the proposed
D4
system.

D5

D6

D7

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 IV. RESULTS
The proposed system is designed as a Moore FSM using
Xilinx Vivado and Verilog HDL. Simulation, synthesis,
implementation and generation of bit stream were done and
no DRC violations were found.
A. Simulation
Fig. 3 displays the result of behavioral simulation
showing the waveform of the Traffic light controller system
for the test bench applied using Verilog HDL.

Fig. 2. State diagram of the proposed system

D. State Table
Having defined the state diagram, a state table is now
formed. Initially, in state S0, vehicle movement is allowed
only for directions corresponding to the light displays D0,
D4 and D7. So, green signal is enabled only for these
directions, and for the other directions, red signal is enabled
on their corresponding light displays. Similarly, according to Fig. 3. Simulated waveform of the system
each state, red, yellow and green signals are enabled for each
of the light displays. Binary encoding scheme is used in the
proposed system. Table II illustrates the state table of the B. RTL Schematic
system. Fig. 4 shows the RTL schematic of the designed system.
TABLE II. STATE TABLE OF THE PROPOSED SYSTEM
Traffic signal status for
each direction
State
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
S0 001 100 100 100 001 100 100 001 100 100
S1 010 100 100 100 001 100 100 001 100 100
S2 100 100 100 100 001 001 100 001 100 100
S3 100 100 100 100 010 001 100 001 100 100
S4 100 100 100 001 100 001 100 001 001 100
S5 100 100 100 010 100 001 100 010 001 100
S6 100 001 100 100 100 001 100 100 001 100
S7 100 010 100 100 100 001 100 100 010 100 Fig. 4. RTL schematic of the system
S8 100 100 001 100 100 001 001 100 100 100 C. Timing report
S9 100 100 010 100 100 010 001 100 100 100 It was observed that the timing report generated during
S10 100 100 100 001 100 100 001 001 100 001 synthesis matched with the timing report generated during
S11 100 100 100 010 100 100 010 001 100 010 implementation. The obtained timing report is shown in Fig.
5.

In each of the states, if MSB is 1, it indicates that the light

display is showing red signal, and so, the movement of
vehicles in the direction corresponding to the light display is
restricted. Similarly, if the middle bit is 1, it corresponds to
yellow signal, and indicates that the traffic flow will stop
soon. If LSB is 1, it corresponds to green signal and the flow
of traffic in the corresponding direction is allowed. The odd Fig. 5. Timing report of the system
states act as ‘safe’ states as few of the light displays show
D. Utilization report
yellow signal indicating that the flow of traffic will be
stopped soon, so that vehicles from those directions can stop, It was observed that the utilization report generated
since crossing the intersection during the period of the during synthesis matched with the utilization report
yellow signal of the current state may lead to accidents due generated during implementation. The obtained utilization
to the flow of traffic regulated during the succeeding even report is shown in Fig. 6.
state.

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 Fig. 6. Utilization report of the system
E. Power report
It was observed that the power report generated during
synthesis matched with the power report generated during
implementation. The obtained power report is shown in Fig.
7. Fig. 9. Device layout of the system

V. CONCLUSION AND FUTURE WORK

The traffic light controller system designed is well suited
to regulate traffic at four-way intersection. The system is
designed in Artix-7 FPGA so as to utilize its advantage of
efficient power consumption. Verilog HDL is used for
programming purpose because if the user wishes to make
any changes in the system, it is possible to apply the required
Fig. 7. Power report of the system changes easily through Verilog HDL code. One of the
advantages of this system is its ‘safe state’ feature
F. Technology schematic implemented in every odd state, which plays a major role in
It was observed that the technology schematic generated preventing vehicle collisions.
during synthesis matched with the technology schematic The simulated waveform matched the traffic light signals
generated during implementation. The obtained technology obtained from the state table. The implemented system had a
schematic is shown in Fig. 8. minimal power utilisation of 0.098 W and had used only
0.01% of the flip flops and 15.24% of the total IO (Input
Output) facilities present in the FPGA.
As a future scope, cameras and sensors can be integrated
to the designed system so that when the traffic controller
system sees an ambulance, it can automatically divert the
traffic accordingly so as to ensure that there is no obstacle
and the way for the ambulance is clear.

REFERENCES
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Fig. 8. Technology schematic of the system Light System Design on FPGA”, Proceedings of 2009 IEEE
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Fig. 9 shows the device layout obtained after Malaysia.
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