At 0vFRvlFw 0F 8051

The most widely used registers

A (Accumulator) For all arithmetic and logic instructions B, R0, R1, R2, R3, R4, RS, R6, R7 DPTR
(data pointer), and PC (program counter).
MOV destination, source copy source to destiny.
The instruction tells the CPU to move (in reality,
COPY) the source operand to the destination operand

'# signiIies that it is a value
MJV A,#55H ;load value 55H into reg. A

MJV R0,A ;copy contents of A into R0
;(now A=R0=55H)
Notes on programming
alue (proceeded with #) can be loaded directly to registers A, B, or R0 -
R7
MJV A, #23H I it`s not preceded with #,it means to load Irom A ,
MJV R5, #0F9H Add a 0 to indicate that memory location F is a hex number
and



I i
All 80S1 members start at memory address 0000 when they're powered up
Program Counter has the value of 0000. The first opcode is burned into RON address 0000H, since this is where
the 80S1 looks for the first instruction when it is booted ,We achieve this by the JRG statement in the source
program.


RON ADRESS NACH!NE ADRESS ASSENBLY LANCUACE
000A 80EF HERE: S]NP HERE
0008 2412 ADD A, #12H
0007 2F ADD A, R7
0006 2D ADD A, RS
0004 7400 NO A, #0
0002 7F34 NO R7, #34H
0000 7D2S NO RS, #2SH

After the program is burned into RON, the opcode and operand are placed in RON memory location
starting at 0000

ADDRESS CODE
000B FE
000A 80
0003 12
0008 24
0007 2F
0006 2D
000S 00
0004 74
0003 34
0002 7F
0001 2S
0000 7D
A stepbystep description of the action of the 80S1 upon applying power on it
1. When 80S1 is powered up, the PC has 0000 and starts to fetch the first opcode from location 0000 of
programRON Upon executing the opcode 7D, the CPU fetches the value 2S and places it in RS Now one instruction
is finished, and then the PC is incremented to point to 0002, containing
opcode 7F
2. Upon executing the opcode 7F, the value 34H is moved into R7.The PC is incremented to 0004
3. The instruction at location 0004 is executed and now PC = 0006
4. After the execution of the 1byte instruction at location 0006, PC = 0007
S. Upon execution of this 1byte instruction at 0007, PC is incremented to 0008
This process goes on until all the instructions are fetched and executed
The fact that program counter points at the next instruction to be executed explains some microprocessors call it
the instruction pointer



EQU: (Equate),!f the value to be used for many times.


The program status word (PSW) register, also referred to as the flag register, is an 8 bit register
Only 6 bits are used
These four are CY (carry), AC (auxiliary carry), P
(parity), and O (overflow)
They are called conditional flags, meaning
that they indicate some conditions that
resulted after an instruction was executed
The PSW3 and PSW4 are designed as RS0 and
RS1, and are used to change the bank
The two unused bits are userdefinable


There are 128 bytes of RAN in the
80S1
Assigned addresses 00 to 7FH
The 128 bytes are divided into three different groups as follows:
1) A total of 32 bytes from locations 00 to 1F hex are set aside for register banks and the stack
2) A total of 16 bytes from locations 20H to 2FH are set aside for bitaddressable read/write memory
3) A total of 80 bytes from locations 30H to 7FH are used for read and write storage, called scratch pad



Register bank 0 is the default when 80S1 is powered up.

We can switch to other banks by use
of the PSW register
Bits D4 and D3 of the PSW are used to select the desired register bank
Use the bitaddressable instructions SETB and CLR to access PSW.4 and PSW.3




Register RS1(PSW.4) RS0(PSW.3)

Bank 3 1 1
Bank 2 1 0
Bank 1 0 1
Bank 0 0 0

xample 2-5
MJV R0, #99H ;load R0 with 99H
MJV R1, #85H ;load R1 with 85H
xample 2-6
MJV 00, #99H ;RAM location 00H has 99H
MJV 01, #85H ;RAM location 01H has 85H
xample 2-7
SETB PSW.4 ;select bank 2
MJV R0, #99H ;RAM location 10H has 99H
MJV R1, #85H ;RAM location 11H has 85H

Example 5-13
rite a program to save the accumulator in R7 oI bank 2.
Solution:
CLR PS.3
S% PS.4
MOV R7,A

The stack is a section of RAN used by the CPU to store information temporarily
This information could be data or an address
The register used to access the stack is called the SP (stack pointer) register
The stack pointer in the 80S1 is only 8 bit wide, which means that it can take value of 00 to FFH
When the 80S1 is powered up, the SP register contains value 07
RAN location 08 is the first location begin used for the stack by the 80S1
The CPU also uses the stack to save the address of the instruction just below the ALL instruction
This is how the CPU knows where to resume when it returns from the called subroutine
!f we want to repeat an action more times than 2S6, we use a loop inside a loop, which is called nested loop.

The unconditional jump is a jump in which control is transferred unconditionally to the target location
MP (long jump)
3byte instruction
First byte is the opcode
Second and third bytes represent the 16bit target address
Any memory location from 0000 to FFFFH
$MP (short jump)
2byte instruction
First byte is the opcode
Second byte is the relative target address 00 to FFH (forward +127 and backward 128 bytes from the current PC)
(long call)
3byte instruction
First byte is the opcode
Second and third bytes are used for address of target subroutine Subroutine is located anywhere within 64K
byte address space
(absolute call)
2byte instruction
11 bits are used for address within 2Kbyte range

When a subroutine is called, control is transferred to that subroutine, the processor
Saves on the stack the the address of the instruction immediately below the LCALL
Begins to fetch instructions form the new location
After finishing execution of the subroutine
The instruction RET transfers control back to the caller
Every subroutine needs RET as the last instruction.

The only difference between AALL and LALL is
The target address for LALL can be anywhere within the 64K byte address
The target address of AALL must be within a 2Kbyte range
The use of AALL instead of LALL can save a number of bytes of program RON space

Find the period oI the machine cycle Ior 11.0592 MHz crystal Irequency
Solution:
11.0592/12 = 921.6 kHz;machine cycle is 1/921.6 kHz = 1.085s.






!n order to make port 0 an input, the port must be programmed by writing 1 to all the bits
Port 0 is conIigured Iirst as an input port by writing 1s to it, and then data is received Irom that port and sent to P1

MJV A,#0FFH ;A=FF hex
MJV P0,A ;make P0 an i/p port;by writing it all 1s
BA MJV A,P0 ;get data from P0
MJV P1,A ;send it to port 1
SJMP BA ;keep doing

To make port 1,2 as an input,Repeat the process by writing 1 to p1..
!n 8031based systems, port 2 must be used along with P0 to provide the 16bit address for the external memory
Port 2 is also designated as A8 A1S, indicating its dual function
Port 0 provides the lower 8 bits via A0 A7

Port 3 does not need any pullup resistors.
]ust like P1, port 2 does not need any pull up resistors since it already has pullup resistors internally.But port0 needs
pull up resistors.
t(p0) can be used Ior input or output, each pin must be connected externally to a 10K ohm pull-up
resistor
%his is due to the Iact that P0 is an open drain, unlike P1, P2, and P3






25ortant instructions.
AGAIN JNB P1.2,AGAIN ; get out when P1.2=1
HERE JNB P2.3,HERE ;keep monitoring for high
SJMP HERE ;keep repeating
Example :rite the Iollowing programs. Create a square wave oI 50 duty cycle on bit 0 oI port 1.
Solution:
%he 50 duty cycle means that the 'on and 'oII state (or the high and low portion oI the pulse) have
the same length. %hereIore, we toggle P1.0 with a time delay in between each state.
HR: S% P1.0 ; set to high bit 0 oI port 1
LCALL DLAY ; call the delay subroutine
CLR P1.0 ; P1.00
LCALL DLAY
SJMP HR ; keep doing it
Another way to write the above program is:
HR: CPL P1.0 ; set to high bit 0 oI port 1
LCALL DLAY ; call the delay subroutine
SJMP HR ; keep doing it



J bit, target ; Jump to target iI bit 1 (jump iI bit)
JN bit, target ; Jump to target iI bit 0 (jump iI no bit)
JC bit, target ; Jump to target iI bit 1, clear bit (jump iI bit, then clear

rite a program to perIorm the Iollowing:
(a) Keep monitoring the P1.2 bit until it becomes high
(b) hen P1.2 becomes high, write value 45H to port 0
(c) Send a high-to-low (H-to-L) pulse to P2.3

Solution:
S% P1.2 ; make P1.2 an input
MOV A,#45H ; A45H
AGAN: JN P1.2,AGAN ; get out when P1.21
MOV P0,A ; issue A to P0
S% P2.3 ; make P2.3 high
CLR P2.3 ; make P2.3 low Ior H-to-L

EXAMPLE cont: Assume that bit P2.3 is an input and represents the condition oI an oven. I it goes high, it means
that the oven is hot. Monitor the bit continuously. henever it goes high, send a high-to-low pulse to port P1.5 to
turn on a buzzer.
Solution:
HR: JN P2.3,HR ; keep monitoring Ior high
S% P1.5 ; set bit P1.51
CLR P1.5 ; make high-to-low
SJMP HR ; keep repeating

EXAMPLE: A switch is connected to pin P1.7. rite a program to check the status oI S and perIorm
the Iollowing:
(a) I S0, send letter N` to P2
(b) I S1, send letter Y` to P2
Use the carry Ilag to check the switch status.
Solution:
S% P1.7 ; make P1.7 an input
AGAN: MOV C,P1.2 ; read S status into CF
JC OVR ; jump iI S1
MOV P2,#`N` ; S0, issue N` to P2
SJMP AGAN ; keep monitoring
OVR: MOV P2,#`Y` ; S1, issue Y` to P2
SJMP AGAN ; keep monitoring

!n reading a port
Some instructions read the status of port pins
Others read the status of an internal port latch
Therefore, when reading ports there are two possibilities:
Read the status of the input pin
Read the internal latch of the output port
Confusion between them is a major source of errors in 80S1 programming
Especially where external hardware is concerned.

Some instructions read the contents of an internal port latch instead of reading the status of an external pin
.. For example, look at the ANL P1,A instruction and the sequence of actions is executed as follow
1. !t reads the internal latch of the port and brings that data into the CPU
2. This data is ANDed with the contents of register A
3. The result is rewritten back to the port latch
4. The port pin data is changed and now has the same value as port latch


ReadNodifyWrite The instructions read the port latch normally read a value, perform an operation then rewrite it
back to the port latch
Nnemonics Example
ANL PX ANL P1,A
ORL PX ORL P2,A
XRL PX XRL P0,A
]BC PX.Y,TARCET ]BC P1.1,TARCET
CPL PX.Y CPL P1.2
!NC PX !NC P1
DEC PX DEC P2
D]NZ PX.Y,TARCET D]NZ P1,TARCET
NO PX.Y,C NO P1.2,C
CLR PX.Y CLR P2.3
SETB PX.Y SETB P2.3

%he ports in 8051 can be accessed by the #ead-modify-write technique
%his Ieature saves many lines oI code by
combining in a single instruction all three
actions
1. Reading the port
2. ModiIying it
3. riting to the port
MOV P1,#55H ; P101010101
AGAN: XRL P1,#0FFH ; X-OR P1 with 1111 1111
ACALL DLAY
SJMP ACK


ADDRESS!NC NODES
The CPU can access data in various ways, which are called
addressing modes
!mmediate
Register
Direct
Register indirect
!ndexed



The SFR (Special Function Register) can be accessed by their names or by their addresses
The SFR registers have addresses between 80H and FFH
Not all the address space of 80 to FF is used by SFR
The unused locations 80H to FFH are reserved and must not be used by the 80S1 programmer
MJV 0E0H,#55H ; is the same as
MJV A,#55h ; load 55H into A
MJV 0F0H,R0 ; is the same as
MJV B,R0 ; copy R0 into B




Bit addressable


Example 5-1
rite code to send 55H to ports P1 and P2, using
(a) their names (b) their addresses
Solution :
(a) MJV A,#55H ;A=55H
MJV P1,A ;P1=55H
MJV P2,A ;P2=55H
(b) From %able 5-1, P1 address80H; P2 addressA0H
MJV A,#55H ;A=55H
MJV 80H,A ;P1=55H
MJV 0A0H,A ;P2=55H

PUSH A is invalid
Pushing the accumulator onto the stack must be coded as PUSH 0E0H
Looping is not possible in direct addressing mode
Example 5-2
Show the code to push R5 and A onto the stack and then pop them back them into R2 and , where A and
R2 R5.
Solution:
PUSH 05 ;push R5 onto stack
PUSH 0E0H ;push register A onto stack
PJP 0F0H ;pop top of stack into B;now register B = register A
PJP 02 ;pop top of stack into R2;now R2=R6

A register is used as a pointer to the data
Only register R0 and R1 are used for this purpose
R2 R7 cannot be used to hold the address of an operand located in RAN
When R0 and R1 hold the addresses of RAN locations, they must be preceded by the @" sign.

Example 5-3
rite a program to copy the value 55H into RAM memory locations
40H to 41H using
(a) direct addressing mode, (b) register indirect addressing mode
without a loop, and (c) with a loop
Solution:
(a)

MOV A,#55H ;load A with value 55H
MOV 40H,A ;copy A to RAM location 40H
MOV 41H.A ;copy A to RAM location 41H
(b)

MOV A,#55H ;load A with value 55H
MOV R0,#40H ;load the pointer. R040H
MOV R0,A ;copy A to RAM R0 points to
NC R0 ;increment pointer. Now R041h
MOV R0,A ;copy A to RAM R0 points to
(c)

MOV A,#55H ;A55H
MOV R0,#40H ;load pointer.R040H,
MOV R2,#02 ;load counter, R23
AGAN: MOV R0,A ;copy 55 to RAM R0 points to
NC R0 ;increment R0 pointer
DJNZ R2,AGAN ;loop until counter zero

NOTE: Looping is not possible in direct addressing mode

rite a program to clear 16 RAM locations starting at RAM address 60H
Solution:
LR A ;A=0
MJV R1,#60H ;load pointer. R1=60H
MJV R7,#16 ;load counter, R7=16
AGAIN MJV @R1,A ;clear RAM R1 points to
IN R1 ;increment R1 pointer
DJNZ R7,AGAIN ;loop until counter=zero

R0 and R1 are the only registers that can be used for pointers in register indirect addressing mode
Since R0 and R1 are 8 bits wide, their use is limited to access any information in the internal RAN
Whether accessing externally connected RAN or onchip RON, we need 16bit pointer
!n such case, the DPTR register is used.


!ndexed addressing mode is widely used in accessing data elements of lookup table entries located in the
program RON
The instruction used for this purpose is MJV A,@A+DPTR
Use instruction MJV, C" means code
The contents of A are added to the 16bit register DPTR to form the 16bit address of the needed data

The lookup table allows access to elements of a frequently used table with minimum operations



rite a program to get the x value Irom P1 and send x2 to P2, continuously
Solution:
JRG 0
MJV DPTR,#300H ;LJAD TABLE ADDRESS
MJV A,#0FFH ;A=FF
MJV P1,A ;JNFIGURE P1 INPUT PJRT
BAMJV A,P1 ;GET X
MJV A,@A+DPTR ;GET X SQAURE FRJM TABLE
MJV P2,A ;ISSUE IT TJ P2
SJMP BA ;EEP DJING IT
JRG 300H
XSQR_TABLE
DB 0,1,4,9,16,25,36,49,64,81
END
The 80S1 has a total of 128K bytes of memory space
64K bytes of code and 64K bytes of data
The data space cannot be shared between code and data
!n many applications we use RAN locations 30 7FH as scratch pad
We use R0 R7 of bank 0
Leave addresses 8 1FH for stack usage
!f we need more registers, we simply use RAN locations 30 7FH

rite a program to toggle P1 a total oI 200 times. Use RAM location 32H to hold your counter value instead oI
registers R0 R7
Solution:
MJV P1,#55H ;P1=55H
MJV 32H,#200 ;load counter value;into RAM loc 32H
LJP1 PL P1 ;toggle P1
AALL DELAY
DJNZ 32H,LJP1 ;repeat 200 times

Nany microprocessors allow program to access registers and !/O ports in byte size only
However, in many applications we need to check a single bit
One unique and powerful feature of the 80S1 is singlebit operation
Singlebit instructions allow the programmer to set, clear, move, and complement individual bits of a
port,memory, or register
!t is registers, RAN, and !/O ports that need to be bitaddressable
RON, holding program code for execution, is not bitaddressable

The bitaddressable RAN location are 20H to 2FH
These 16 bytes provide 128 bits of RAN bitaddressability, since 16 b8 = 128
0 to 127 (in decimal) or 00 to 7FH
The first byte of internal RAN location 20H has bit address 0 to 7H
The last byte of 2FH has bit address 78H to 7FH
!nternal RAN locations 202FH are both byteaddressable and bitaddressable
Bit address 007FH belong to RAN byte addresses 202FH
Bit address 80F7H belong to SFR P0, P1,


To avoid confusion regarding the addresses 00 - 7FH
%he 128 bytes oI RAM have the byte
addresses oI 00 7FH can be accessed in
byte size using various addressing modes
Direct and register-indirect
%he 16 bytes oI RAM locations 20 2FH
have bit address oI 00 7FH
e can use only the single-bit instructions and
these instructions use only direct addressing
mode
While all of the SFR registers are byte addressable,
some of them are also bit addressable
The P0 P3 are bit addressable
We can access either the entire 8 bits
or any single bit of !/O ports P0, P1, P2, and P3 without altering the rest
When accessing a port in a singlebit
manner, we use the syntax SETB X.Y
X is the port number P0, P1, P2, or P3
Y is the desired bit number from 0 to 7 for
data bits D0 to D7
ex. SETB P1.5 sets bit S of port 1 high


NO%:Only registers A, , PS, P, , ACC, SCON, and %CON are bit-addressable
hile all O ports are bit-addressable





AR!THNET!C AND LOC!C



A A ;decimal adjust Ior addition
%he DA instruction is provided to correct the aIorementioned problem associated with CD addition
%he DA instruction will add 6 to the lower nibble or higher nibble iI need


n many microprocessor there are two diIIerent instructions Ior subtraction:SUB and SUBB (subtract with borrow)

SUBB when CY 0
1. %ake the 2`s complement oI the
subtrahend (source operand)
2. Add it to the minuend (A)
3. nvert the carry



SU when CY 1
%his instruction is used Ior multi-byte numbers and will take care oI the borrow oI the lower operand



%he 8051 supports byte by byte multiplication only
%he byte are assumed to be unsigned data
MUL A ;Ax, 16-bit result in , A
MOV A,#25H ;load 25H to reg. A
MOV ,#65H ;load 65H to reg.
MUL A ;25H * 65H 99 where; OH and A 99H.

a) rite a program to get hex data in the range oI 00 FFH Irom port 1 and convert it to decimal. Save it in R7, R6
and R5.
(b) Assuming that P1 has a value oI FDH Ior data, analyze program.
Solution:
(a)
MOV A,#0FFH
MOV P1,A ;make P1 an input port
MOV A,P1 ;read data Irom P1
MOV ,#10 ;0A hex
DV A ;divide by 10
MOV R7, ;save lower digit
MOV ,#10
DV A ;divide by 10 once more
MOV R6, ;save the next digit
MOV R5,A ;save the last digit
(b) %o convert a binary (hex) value to decimal, we divide it by 10 repeatedly until the quotient is less than 10. AIter
each division the remainder is saves.
Q #
FD0A 19 3 (low digit)
190A 2 5 (middle digit)
2 (high digit)
%hereIore, we have FDH253.

,,,%o make the 2`s complement oI a number
CPL A ;1`s complement (invert)
ADD A,#1 ;add 1 to make 2`s comp.

ANL destination,source; dest dest AN source
%his instruction will perIorm a logic AND on the two operands and place the result in the destination
%he destination is normally the accumulator
%he source operand can be a register, in memory, or immediate
Y AND Y
Show the results oI the Iollowing.
MOV A,#35H ;A 35H
ANL A,#0FH ;A A AND 0FH
35H 0 0 1 1 0 1 0 1
0FH 0 0 0 0 1 1 1 1
05H 0 0 0 0 0 1 0 1

Similarly ORL, XRL.




C1NE destination,source,rel. addr.

%he actions oI comparing and jumping are combined into a single instruction called CJN (compare and
jump iI not equal)
%he CJN instruction compares two operands, and jumps iI they are not equal
%he destination operand can be in the accumulator or in one oI the Rn registers
%he source operand can be in a register, in memory, or immediate
%he operands themselves remain unchanged
t changes the CY Ilag to indicate iI the destination operand is larger or smaller

rite a program to read the temperature and test it Ior the value 75.
According to the test results, place the temperature value into the registers indicated by the Iollowing.
I % 75 then A 75
I % 75 then R1 %
I % ~ 75 then R2 %
Solution:
MOV P1,#0FFH ; make P1 an input port
MOV A,P1 ; read P1 port
CJN A,#75,OVR ; jump iI A is not 75
SJMP X% ; A75, exit
OVR: JNC NX% ; iI CY0 then A~75
MOV R1,A ; CY1, A75, save in R1
SJMP X% ; and exit
NX%: MOV R2,A ; A~75, save it in R2
X%: ...


## A ;rotate right A

MOV A,#36H ;A 0011 0110
RR A ; A 0001 1011
RR A ; A 1000 1101
RR A ; A 1100 0110
RR A ; A 0110 0011

Similarly RLA: Rotate leIt.

##C A ;rotate right through carry

CLR C ;make CY 0
MOV A,#26H ;A 0010 0110
RRC A ;A 0001 0011 CY 0
RRC A ;A 0000 1001 CY 1
RRC A ;A 1000 0100 CY 1





XA: Assume that bit P2.2 is used to control an outdoor light and bit P2.5 a light inside a building. Show
how to turn on the outside light and turn oII the inside one.
Solution:
S% C ;CY 1
ORL C,P2.2 ;CY P2.2 ORed w CY
MOV P2.2,C ;turn it on iI not on
CLR C ;CY 0
ANL C,P2.5 ;CY P2.5 ANDed w CY
MOV P2.5,C ;turn it oII iI not oII

XA:rite a program that Iinds the number oI 1s in a given byte.
Solution:
MOV R1,#0 ;R1 keeps number oI 1s
MOV R7,#8 ;counter, rotate 8 times
MOV A,#97H ;Iind number oI 1s in 97H
AGAN: RLC A ;rotate it thru CY
JNC NX% ;check CY
NC R1 ;iI CY1, inc count
NX%: DJNZ R7,AGAN ;go thru 8 times

$P
!t swaps the lower nibble and the higher nibble
!n other words, the lower 4 bits are put into the higher 4 bits and the higher 4 bits are put
into the lower 4 bits

(a) Find the contents oI register A in the Iollowing code.
(b) n the absence oI a SAP instruction, how would you exchange the nibbles? rite a simple program to show
the process.
Solution:


(a)
MOV A,#72H ;A 72H
SAP A ;A 27H
(b)
MOV A,#72H ;A 0111 0010
RL A ;A 0111 0010
RL A ;A 0111 0010
RL A ;A 0111 0010
RL A ;A 0111 0010

Many AC (analog-to-digital converter) chips provide output data in binary
(hex)
%o display the data on an LCD or PC screen, we need to convert it to ASC
Convert 8-bit binary (hex) data to decimal digits, 000 255
Convert the decimal digits to ASC digits, 30H 39H





%o convert ASC to packed CD
t is Iirst converted to unpacked CD (to get rid oI the 3)
Combined to make packed CD



MOV A, #`4` ; A34H, hex Ior 4`
MOV R1,#`7` ; R137H,hex Ior 7`
ANL A, #0FH ; mask upper nibble (A04)
ANL R1,#0FH ; mask upper nibble (R107)
SAP A ; A40H
ORL A, R1 ; A47H, packed CD



X:Assume that register A has packed CD, write a program to convert packed CD to two ASC numbers and
place them in R2 and R6.

MOV A,#29H ; A29H, packed CD
MOV R2,A ; keep a copy oI CD data
ANL A,#0FH ; mask the upper nibble (A09)
ORL A,#30H ; make it an ASC, A39H(9`)
MOV R6,A ; save it
MOV A,R2 ; A29H, get the original data
ANL A,#0F0H ; mask the lower nibble
RR A ;rotate right
RR A ;rotate right
RR A ;rotate right
RR A ;rotate right
ORL A,#30H ; A32H, ASC char. `2`
MOV R2,A ; save ASC char in R2

HA#A#E CONNECTIONS

EA, ~external access``, is an input pin and must be connected to Vcc or GND
%he 8051 Iamily members all come with on-chip ROM to store programs
-A pin is connected to Vcc
%he 8031 and 8032 Iamily members do no have on-chip ROM, so code is stored on an external ROM
and is Ietched by 803132
-A pin must be connected to GND to indicate that the code is stored externally

%he Iollowing two pins are used mainly
in 8031-based systems
PSN, 'program store enable``, is an output pin
%his pin is connected to the O pin oI the ROM
AL, 'address latch enable, is an output pin and is active high
Port 0 provides both address and data
%he 8031 multiplexes address and data through port 0 to save pins
AL pin is used Ior demultiplexing the address and data by connecting to the G pin oI the 74LS373
chip

Port 0 is also designated as AD0-AD7, allowing it to be used Ior both address and data
hen connecting an 805131 to an external memory, port 0 provides both address and data
%he 8051 multiplexes address and data through port 0 to save pins
AL indicates iI P0 has address or data
hen AL0, it provides data D0-D7
hen AL1, it has address A0-A7

n 8051-based systems with no external memory connection
oth P1 and P2 are used as simple O
n 803151-based systems with external memory connections
Port 2 must be used along with P0 to provide the 16-bit address Ior the external memory
P0 provides the lower 8 bits via A0 A7
P2 is used Ior the upper 8 bits oI the 16-bit address, designated as A8 A15, and it cannot be used Ior
O


NENORY ORCAN!SAT!ON:

A memory chip contain 2x location, where x is the number oI address pins
ach location contains y bits, where y is the number oI data pins on the chip
%he entire chip will contain 2x y bits

A given memory chip has 12 address pins and 4 data pins. Find:
(a) %he organization, and (b) the capacity.
Solution:
(a) %his memory chip has 4096 locations (212 4096), and each location can hold 4 bits oI data. %his gives an
organization oI 4096 4, oIten represented as 4K 4.
(b) %he capacity is equal to 16K bits since there is a total oI 4K locations and each location can hold 4 bits oI data.


n connecting a memory chip to the CPU, note the Iollowing points
%he data bus oI the CPU is connected directly to the data pins oI the memory chip
Control signals RD (read) and R (memory write) Irom the CPU are connected to the
O (output enable) and (write enable) pins oI the memory chip
n the case oI the address buses, while the lower bits oI the address Irom the CPU go
directly to the memory chip address pins, the upper ones are used to activate the CS pin oI the memory
chip

%his is one oI the most widely used
address decoders
%he 3 inputs A, , and C generate 8 activelow outputs Y0 Y7
ach Y output is connected to CS oI a memory chip, allowing control oI 8 memory blocks by a single 74LS138
n the 74LS138, where A, , and C select which output is activated, there are three additional inputs, G2A, G2,
and G1
G2A and G2 are both active low, and G1 is active high
I any one oI the inputs G1, G2A, or G2 is not connected to an address signal, they must be activated
permanently either by Vcc or ground, depending on the activation level





Since the PC (program counter) oI the 803151 is 16-bit, it is capable oI accessing up to 64K bytes oI program
code
n the 803151, port 0 and port 2 provide the 16-bit address to access external memory
P0 provides the lower 8 bit address A0 A7, and P2 provides the upper 8 bit address A8 A15
P0 is also used to provide the 8-bit data bus D0 D7
P0.0 P0.7 are used Ior both the address and data paths
addressdata multiplexing

AL (address latch enable) pin is an output pin Ior 803151
AL 0, P0 is used Ior data path
AL 1, P0 is used Ior address path
74LS373 D Latch
%o extract the address Irom the P0 pins we connect P0 to a 74LS373 and
use the AL pin to latch the address






PSN (program store enable) signal is an output signal Ior the 803151 microcontroller and must be connected
to the O pin oI a ROM containing the program code
t is important to emphasize the role oI A and PSN when connecting the 803151 to external ROM
hen the A pin is connected to GND, the 803151 Ietches opcode Irom external ROM by using PSN

%he connection oI the PSN pin to the
O pin oI ROM
n systems based on the 875189C51
DS5000 where A is connected to Vcc,
these chips do not activate the PSN pin
%his indicates that the on-chip ROM
contains program code Connection to xternal
Program ROM





e use RD to connect the 803151 to
external ROM containing data
For the ROM containing the program code,
PSN is used to Ietch the code

MOVX is a widely used instruction
allowing access to external data
memory space
%o bring externally stored data into the
CPU, we use the instruction
MOVX A,DP%R




To connect the 80S1 to an external SRAN, we must use both RD (P3.7) and
WR (P3.6)

n writing data to external data RAM, we use the instruction
MOVX DP%R,A
(a) rite a program to read 200 bytes oI data Irom P1 and save the data in external RAM starting at RAM location
5000H.
(b) hat is the address space allocated to data RAM in Figure 14-15?
Solution:
(a)
RAMDA%A "U 5000H
COUN% "U 200
MOV DP%R,#RAMDA%A
MOV R3,#COUN%
AGAN: MOV A,P1
MOVX DP%R,A
ACALL DLAY
NC DP%R
DJNZ R3,AGAN
HR: SJMP HR
(b) %he data address space is 8000H to FFFH.


To allow a single RON chip to
provide
both program code space and data
space, we use an AND gate to
signal
the OE pin of the RON chip











To generate a time delay
1. Load the TNOD value register indicating which timer (timer 0 or timer 1) is to be used and which timer
mode (0 or 1) is selected
2. Load registers TL and TH with initial count value
3. Start the timer
4. Keep monitoring the timer flag (TF) with the JNB TFx,target instruction to see if it is raised
Cet out of the loop when TF becomes high
S. Stop the timer
6. Clear the TF flag for the next round
7. Co back to Step 2 to load TH and TL again
Example 9-4
n the Iollowing program, we create a square wave oI 50 duty cycle (with equal portions high and low) on the P1.5
bit. %imer 0 is used to generate the time delay. Analyze the program
MJV TMJD,#01 ;Timer 0, mode 1(16-bit mode)
HERE MJV TL0,#0F2H ;TL0=F2H, the low byte
MJV TH0,#0FFH ;TH0=FFH, the high byte
PL P1.5 ;toggle P1.5
AALL DELAY
SJMP HERE
n the above program notice the Iollowing step.
1. %MOD is loaded.
2. FFF2H is loaded into %H0-%L0.
3. P1.5 is toggled Ior the high and low portions oI the pulse.
DELAY
SETB TR0 ;start the timer 0
AGAIN JNB TF0,AGAIN ;monitor timer flag 0
;until it rolls over
LR TR0 ;stop timer 0
LR TF0 ;clear timer 0 flag
RET
4. %he DLAY subroutine using the timer is called.
5. n the DLAY subroutine, timer 0 is started by the SETB TR0 instruction.
6. %imer 0 counts up with the passing oI each clock, which is provided by the crystal oscillator. As the timer counts
up, it goes through the states oI FFF3, FFF4, FFF5, FFF6, FFF7, FFF8, FFF9, FFFA, FFF, and so on until it
reaches FFFFH. One more clock rolls it to 0, raising the timer Ilag (%F01).At that point, the JN instruction Ialls
through.
7. %imer 0 is stopped by the instruction LR TR0. %he DLAY subroutine ends, and the process is repeated.

Notice that to repeat the process, we must reload the %L and %H registers, and start the process is repeated
%he number oI counts Ior the roll over is FFFFH FFF2H 0DH (13 decimal). However, we add one to 13 because
oI the extra clock needed when it rolls over Irom FFFF to 0 and raise the %F Ilag. %his gives 14 b1.085us
15.19us Ior halI the pulse. For the entire period it is % 2 b15.19us 30.38us as the time delay generated by the
timer.

n the timer delay calculation we did not include the overhead due to instruction in the loop. %o get a more accurate
timing, we need to add clock cycles due to this instructions in the loop. %o do that, we use the machine cycle Irom %
as shown below.


Cycles
HERE MJV TL0,#0F2H 2
MJV TH0,#0FFH 2
PL P1.5 1
AALL DELAY 2
SJMP HERE 2
DELAY
SETB TR0 1
AGAIN JNB TF0,AGAIN 14
LR TR0 1
LR TF0 1
RET 2
Total 28
% 2 b28 b1.085 us 60.76 us and F 16458.2 Hz

Example
Assume that X%AL 11.0592 MHz. hat value do we need to load the timer`s register iI we want to have a time
delay oI 5 ms (milliseconds)? Show the program Ior timer 0 to create a pulse width oI 5 ms on P2.3.
Solution:
Since X%AL 11.0592 MHz, the counter counts up every 1.085 us. %his means that out oI many 1.085 us intervals
we must make a 5 ms pulse. %o get that, we divide one by the other. e need 5 ms 1.085 us 4608 clocks. %o
Achieve that we need to load into %L and %H the value 65536 4608 00H. %hereIore, we have %H and
%L 00.
LR P2.3 ;lear P2.3
MJV TMJD,#01 ;Timer 0, 16-bitmode
HERE MJV TL0,#0 ;TL0=0, the low byte
MJV TH0,#0EEH ;TH0=EE, the high byte
SETB P2.3 ;SET high P2.3
SETB TR0 ;Start timer 0
AGAIN JNB TF0,AGAIN ;Monitor timer flag 0
LR TR0 ;Stop the timer 0
LR TF0 ;lear timer 0 flag

Example
Assume that X%AL 11.0592 MHz, write a program to generate a square wave oI 2 kHz Irequency on pin P1.5.
Solution:
%his is similar to xample 9-10, except that we must toggle the bit to generate the square wave. Look at the
Iollowing steps.
(a) % 1 I 1 2 kHz 500 us the period oI square wave.
(b) 1 2 oI it Ior the high and low portion oI the pulse is 250 us.
(c) 250 us 1.085 us 230 and 65536 230 65306 which in hex is FF1AH.
(d) %L 1A and %H FF, all in hex. %he program is as Iollow.
MJV TMJD,#01 ;Timer 0, 16-bitmode
AGAIN MJV TL1,#1AH ;TL1=1A, low byte of timer
MJV TH1,#0FFH ;TH1=FF, the high byte
SETB TR1 ;Start timer 1
BA JNB TF1,BA ;until timer rolls over
LR TR1 ;Stop the timer 1
LR P1.5 ;lear timer flag 1
LR TF1 ;lear timer 1 flag
SJMP AGAIN ;Reload timer





COUNTERSNDTIMERS
8 you already know, the microcontroller o8cillator u8e8 quartz cry8tal for it8 operation. 8 the frequency
of thi8 o8cillator i8 preci8ely defined and very 8table, pul8e8 it generate8 are alway8 of the 8ame width,
which make8 them ideal for time mea8urement. Such cry8tal8 are al8o u8ed in quartz watche8. n order to
mea8ure time between two event8 it i8 8ufficient to count up pul8e8 coming from thi8 o8cillator. That i8
exactly what the timer doe8. f the timer i8 properly programmed, the value 8tored in it8 regi8ter will be
incremented (or decremented) with each coming pul8e, i.e. once per each machine cycle. 8ingle
machine-cycle in8truction la8t8 for 12 quartz o8cillator period8, which mean8 that by embedding quartz
with o8cillator frequency of 12MHz, a number 8tored in the timer regi8ter will be changed million time8 per
8econd, i.e. each micro8econd.
The 8051 microcontroller ha8 2 timer8counter8 called T0 and T1. 8 their name8 8ugge8t, their main
purpo8e i8 to mea8ure time and count external event8. Be8ide8, they can be u8ed for generating clock
pul8e8 to be u8ed in 8erial communication, 8o called Baud Rate.
TMER T0
8 8een in figure below, the timer T0 con8i8t8 of two regi8ter8 TH0 and TL0 repre8enting a low and a
high byte of one 16-digit binary number.

ccordingly, if the content of the timer T0 i8 equal to 0 (T0=0) then both regi8ter8 it con8i8t8 of will contain
0. f the timer contain8 for example number 1000 (decimal), then the TH0 regi8ter (high byte) will contain
the number 3, while the TL0 regi8ter (low byte) will contain decimal number 232.

Formula u8ed to calculate value8 in the8e two regi8ter8 i8 very 8imple:
TH0 256 + TL0 = T
Matching the previou8 example it would be a8 follow8:
3 256 + 232 = 1000

Since the timer T0 i8 virtually 16-bit regi8ter, the large8t value it can 8tore i8 65 535. n ca8e of exceeding
thi8 value, the timer will be automatically cleared and counting 8tart8 from 0. Thi8 condition i8 called an
overflow. Two regi8ter8 TMOD and TCON are clo8ely connected to thi8 timer and control it8 operation.
TMOD REGSTER (TMER MODE)
The TMOD regi8ter 8elect8 the operational mode of the timer8 T0 and T1. 8 8een in figure below, the
low 4 bit8 (bit0 - bit3) refer to the timer 0, while the high 4 bit8 (bit4 - bit7) refer to the timer 1. There are 4
operational mode8 and each of them i8 de8cribed herein.

Bit8 of thi8 regi8ter have the following function:
O TE1 enable8 and di8able8 Timer 1 by mean8 of a 8ignal brought to the NT1 pin
(P3.3):
o 1 - Timer 1 operate8 only if the NT1 bit i8 8et.
o - Timer 1 operate8 regardle88 of the logic 8tate of the NT1 bit.
O C/T1 8elect8 pul8e8 to be counted up by the timercounter 1:
o 1 - Timer count8 pul8e8 brought to the T1 pin (P3.5).
o - Timer count8 pul8e8 from internal o8cillator.
O T1M1,T1M The8e two bit8 8elect the operational mode of the Timer 1.
T1 M1 T1 M MODE DESCRI PTI ON
0 0 0 13-bit timer
0 1 1 16-bit timer
1 0 2 8-bit auto-reload
1 1 3 Split mode
O TE enable8 and di8able8 Timer 1 u8ing a 8ignal brought to the NT0 pin (P3.2):
o 1 - Timer 0 operate8 only if the NT0 bit i8 8et.
o - Timer 0 operate8 regardle88 of the logic 8tate of the NT0 bit.
O C/T 8elect8 pul8e8 to be counted up by the timercounter 0:
o 1 - Timer count8 pul8e8 brought to the T0 pin (P3.4).
o - Timer count8 pul8e8 from internal o8cillator.
O TM1,TM The8e two bit8 8elect the oprtaional mode of the Timer 0.

T M1

T M

MODE

DESCRI PTI ON
0 0 0 13-bit timer
0 1 1 16-bit timer
1 0 2 8-bit auto-reload
1 1 3 Split mode
TMER 0 N MODE 0 (13-BT TMER)
Thi8 i8 one of the raritie8 being kept only for the purpo8e of compatibility with the previuo8 ver8ion8 of
microcontroller8. Thi8 mode configure8 timer 0 a8 a 13-bit timer which con8i8t8 of all 8 bit8 of TH0 and the
lower 5 bit8 of TL0. 8 a re8ult, the Timer 0 u8e8 only 13 of 16 bit8. How doe8 it operate? Each coming
pul8e cau8e8 the lower regi8ter bit8 to change their 8tate8. fter receiving 32 pul8e8, thi8 regi8ter i8
loaded and automatically cleared, while the higher byte (TH0) i8 incremented by 1. Thi8 proce88 i8
repeated until regi8ter8 count up 8192 pul8e8. fter that, both regi8ter8 are cleared and counting 8tart8
from 0.

TMER 0 N MODE 1 (16-BT TMER)
Mode 1 configure8 timer 0 a8 a 16-bit timer compri8ing all the bit8 of both regi8ter8 TH0 and TL0. That'8
why thi8 i8 one of the mo8t commonly u8ed mode8. Timer operate8 in the 8ame way a8 in mode 0, with
difference that the regi8ter8 count up to 65 536 a8 allowable by the 16 bit8.

TMER 0 N MODE 2 (&TO-RELOD TMER)
Mode 2 configure8 timer 0 a8 an 8-bit timer. ctually, timer 0 u8e8 only one 8-bit regi8ter for counting and
never count8 from 0, but from an arbitrary value (0-255) 8tored in another (TH0) regi8ter.
The following example 8how8 the advantage8 of thi8 mode. Suppo8e it i8 nece88ary to con8tantly count
up 55 pul8e8 generated by the clock.
f mode 1 or mode 0 i8 u8ed, t i8 nece88ary to write the number 200 to the timer regi8ter8 and con8tantly
check whether an overflow ha8 occured, i.e. whether they reached the value 255. When it happen8, it i8
nece88ary to rewrite the number 200 and repeat the whole procedure. The 8ame procedure i8
automatically performed by the microcontroller if 8et in mode 2. n fact, only the TL0 regi8ter operate8 a8
a timer, while another (TH0) regi8ter 8tore8 the value from which the counting 8tart8. When the TL0
regi8ter i8 loaded, in8tead of being cleared, the content8 of TH0 will be reloaded to it. Referring to the
previou8 example, in order to regi8ter each 55th pul8e, the be8t 8olution i8 to write the number 200 to the
TH0 regi8ter and configure the timer to operate in mode 2.

TMER 0 N MODE 3 (SPLT TMER)
Mode 3 configure8 timer 0 8o that regi8ter8 TL0 and TH0 operate a8 8eparate 8-bit timer8. n other word8,
the 16-bit timer con8i8ting of two regi8ter8 TH0 and TL0 i8 8plit into two independent 8-bit timer8. Thi8
mode i8 provided for application8 requiring an additional 8-bit timer or counter. The TL0 timer turn8 into
timer 0, while the TH0 timer turn8 into timer 1. n addition, all the control bit8 of 16-bit Timer 1 (con8i8ting
of the TH1 and TL1 regi8ter), now control the 8-bit Timer 1. Even though the 16-bit Timer 1 can 8till be
configured to operate in any of mode8 (mode 1, 2 or 3), it i8 no longer po88ible to di8able it a8 there i8 no
control bit to do it. Thu8, it8 operation i8 re8tricted when timer 0 i8 in mode 3.

The only application of thi8 mode i8 when two timer8 are u8ed and the 16-bit Timer 1 the operation of
which i8 out of control i8 u8ed a8 a baud rate generator.
TMER CONTROL (TCON) REGSTER
TCON regi8ter i8 al8o one of the regi8ter8 who8e bit8 are directly in control of timer operation.
Only 4 bit8 of thi8 regi8ter are u8ed for thi8 purpo8e, while re8t of them i8 u8ed for interrupt control to be
di8cu88ed later.

O TF1 bit i8 automatically 8et on the Timer 1 overflow.
O TR1 bit enable8 the Timer 1.
o 1 - Timer 1 i8 enabled.
o - Timer 1 i8 di8abled.
O TF bit i8 automatically 8et on the Timer 0 overflow.
O TR bit enable8 the timer 0.
o 1 - Timer 0 i8 enabled.
o - Timer 0 i8 di8abled.
HOW TO &SE THE TMER 0 ?
n order to u8e timer 0, it i8 fir8t nece88ary to 8elect it and configure the mode of it8 operation. Bit8 of the
TMOD regi8ter are in control of it:

Referring to figure above, the timer 0 operate8 in mode 1 and count8 pul8e8 generated by internal clock
the frequency of which i8 equal to 112 the quartz frequency.
Turn on the timer:

The TR0 bit i8 8et and the timer 8tart8 operation. f the quartz cry8tal with frequency of 12MHz i8
embedded then it8 content8 will be incremented every micro8econd. fter 65.536 micro8econd8, the both
regi8ter8 the timer con8i8t8 of will be loaded. The microcontroller automatically clear8 them and the timer
keep8 on repeating procedure from the beginning until the TR0 bit value i8 logic zero (0).
HOW TO 'RED' TMER?
Depending on application, it i8 nece88ary either to read a number 8tored in the timer regi8ter8 or to
regi8ter the moment they have been cleared.
- t i8 extremely 8imple to read a timer by u8ing only one regi8ter configured in mode 2 or 3. t i8 8ufficient
to read it8 8tate at any moment. That'8 all!
- t i8 8omehow complicated to read a timer configured to operate in mode 2. Suppo8e the lower byte i8
read fir8t (TL0), then the higher byte (TH0). The re8ult i8:
TH0 = 15 TL0 = 255
Everything 8eem8 to be ok, but the current 8tate of the regi8ter at the moment of reading wa8:
TH0 = 14 TL0 = 255
n ca8e of negligence, 8uch an error in counting (255 pul8e8) may occur for not 8o obviou8 but quite
logical rea8on. The lower byte i8 correctly read (255), but at the moment the program counter wa8 about
to read the higher byte TH0, an overflow occurred and the content8 of both regi8ter8 have been changed
(TH0: 1415, TL0: 2550). Thi8 problem ha8 a 8imple 8olution. The higher byte 8hould be read fir8t,
then the lower byte and once again the higher byte. f the number 8tored in the higher byte i8 different
then thi8 8equence 8hould be repeated. t'8 about a 8hort loop con8i8ting of only 3 in8truction8 in the
program.
There i8 another 8olution a8 well. t i8 8ufficient to 8imply turn the timer off while reading i8 going on (the
TR0 bit of the TCON regi8ter 8hould be cleared), and turn it on again after reading i8 fini8hed.
TMER 0 OVERFLOW DETECTON
&8ually, there i8 no need to con8tantly read timer regi8ter8. t i8 8ufficient to regi8ter the moment they are
cleared, i.e. when counting 8tart8 from 0. Thi8 condition i8 called an overflow. When it occurr8, the TF0 bit
of the TCON regi8ter will be automatically 8et. The 8tate of thi8 bit can be con8tantly checked from within
the program or by enabling an interrupt which will 8top the main program execution when thi8 bit i8 8et.
Suppo8e it i8 nece88ary to provide a program delay of 0.05 8econd8 (50 000 machine cycle8), i.e. time
when the program 8eem8 to be 8topped:
Fir8t a number to be written to the timer regi8ter8 8hould be calculated:

Then it 8hould be written to the timer regi8ter8 TH0 and TL0:

When enabled, the timer will re8ume counting from thi8 number. The 8tate of the TF0 bit, i.e. whether it i8
8et, i8 checked from within the program. t happen8 at the moment of overflow, i.e. after exactly 50.000
machine cycle8 or 0.05 8econd8.



HOW TO MES&RE P&LSE D&RTON?

Suppo8e it i8 nece88ary to mea8ure the duration of an operation, for example how long a device ha8
been turned on? Look again at the figure illu8trating the timer and pay attention to the function of the
GTE0 bit of the TMOD regi8ter. f it i8 cleared then the 8tate of the P3.2 pin doe8n't affect timer
operation. f GTE0 = 1 the timer will operate until the pin P3.2 i8 cleared. ccordingly, if thi8 pin i8
8upplied with 5V through 8ome external 8witch at the moment the device i8 being turned on, the timer will
mea8ure duration of it8 operation, which actually wa8 the objective.
HOW TO CO&NT &P P&LSES?
Similarly to the previou8 example, the an8wer to thi8 que8tion again lie8 in the TCON regi8ter. Thi8 time
it'8 about the CT0 bit. f the bit i8 cleared the timer count8 pul8e8 generated by the internal o8cillator, i.e.
mea8ure8 the time pa88ed. f the bit i8 8et, the timer input i8 provided with pul8e8 from the P3.4 pin (T0).
Since the8e pul8e8 are not alway8 of the 8ame width, the timer cannot be u8ed for time mea8urement and
i8 turned into a counter, therefore. The highe8t frequency that could be mea8ured by 8uch a counter i8
124 frequency of u8ed quartz-cry8tal.
TMER 1
Timer 1 i8 identical to timer 0, except for mode 3 which i8 a hold-count mode. t mean8 that they have the
8ame function, their operation i8 controlled by the 8ame regi8ter8 TMOD and TCON and both of them can
operate in one out of 4 different mode8.

2.7 &RT (&NVERSL SYNCHRONO&S RECEVER ND TRNSMTTER)
One of the microcontroller feature8 making it 8o powerful i8 an integrated &RT, better known a8 a 8erial
port. t i8 a full-duplex port, thu8 being able to tran8mit and receive data 8imultaneou8ly and at different
baud rate8. Without it, 8erial data 8end and receive would be an enormou8ly complicated part of the
program in which the pin 8tate i8 con8tantly changed and checked at regular interval8. When u8ing
&RT, all the programmer ha8 to do i8 to 8imply 8elect 8erial port mode and baud rate. When it'8 done,
8erial data tran8mit i8 nothing but writing to the SB&F regi8ter, while data receive repre8ent8 reading the
8ame regi8ter. The microcontroller take8 care of not making any error during data tran8mi88ion.

Serial port mu8t be configured prior to being u8ed. n other word8, it i8 nece88ary to determine how many
bit8 i8 contained in one 8erial "word, baud rate and 8ynchronization clock 8ource. The whole proce88 i8 in
control of the bit8 of the SCON regi8ter (Serial Control).
SERL PORT CONTROL (SCON) REGSTER

O SM - Serial port mode bit 0 i8 u8ed for 8erial port mode 8election.
O SM1 - Serial port mode bit 1.
O SM2 - Serial port mode 2 bit, al8o known a8 multiproce88or communication enable bit.
When 8et, it enable8 multiproce88or communication in mode 2 and 3, and eventually
mode 1. t 8hould be cleared in mode 0.
O REN - Reception Enable bit enable8 8erial reception when 8et. When cleared, 8erial
reception i8 di8abled.
O TB8 - Tran8mitter bit 8. Since all regi8ter8 are 8-bit wide, thi8 bit 8olve8 the problem of
tran8miting the 9th bit in mode8 2 and 3. t i8 8et to tran8mit a logic 1 in the 9th bit.
O RB8 - Receiver bit 8 or the 9th bit received in mode8 2 and 3. Cleared by hardware if 9th
bit received i8 a logic 0. Set by hardware if 9th bit received i8 a logic 1.
O TI - Tran8mit nterrupt flag i8 automatically 8et at the moment the la8t bit of one byte i8
8ent. t'8 a 8ignal to the proce88or that the line i8 available for a new byte tran8mite. t
mu8t be cleared from within the 8oftware.
O RI - Receive nterrupt flag i8 automatically 8et upon one byte receive. t 8ignal8 that byte
i8 received and 8hould be read quickly prior to being replaced by a new data. Thi8 bit i8
al8o cleared from within the 8oftware.
8 8een, 8erial port mode i8 8elected by combining the SM0 and SM2 bit8:
SM SM1 MODE DESCRI PTI ON BUD RT E
0 0 0 8-bit Shift Register 1/12 the quartz frequency
0 1 1 8-bit UART Determined by the timer 1
1 0 2 9-bit UART 1/32 the quartz frequency (1/64 the quartz frequency)
1 1 3 9-bit UART Determined by the timer 1

n mode 0, 8erial data are tran8mitted and received through the RXD pin, while the TXD pin output clock8.
The bout rate i8 fixed at 112 the o8cillator frequency. On tran8mit, the lea8t 8ignificant bit (LSB bit) i8
8entreceived fir8t.
TRNSMIT - Data tran8mit i8 initiated by writing data to the SB&F regi8ter. n fact, thi8 proce88 8tart8
after any in8truction being performed upon thi8 regi8ter. When all 8 bit8 have been 8ent, the T bit of the
SCON regi8ter i8 automatically 8et.

RECEIVE - Data receive through the RXD pin 8tart8 upon the two following condition8 are met: bit REN=1
and R=0 (both of them are 8tored in the SCON regi8ter). When all 8 bit8 have been received, the R bit of
the SCON regi8ter i8 automatically 8et indicating that one byte receive i8 complete.

Since there are no STRT and STOP bit8 or any other bit except data 8ent from the SB&F regi8ter in the
pul8e 8equence, thi8 mode i8 mainly u8ed when the di8tance between device8 i8 8hort, noi8e i8
minimized and operating 8peed i8 of importance. typical example i8 O port expan8ion by adding a
cheap C (8hift regi8ter8 74HC595, 74HC597 and 8imilar).




MODE 1

n mode 1, 10 bit8 are tran8mitted through the TXD pin or received through the RXD pin in the following
manner: a STRT bit (alway8 0), 8 data bit8 (LSB fir8t) and a STOP bit (alway8 1). The STRT bit i8 only
u8ed to initiate data receive, while the STOP bit i8 automatically written to the RB8 bit of the SCON
regi8ter.
TRNSMIT - Data tran8mit i8 initiated by writing data to the SB&F regi8ter. End of data tran8mi88ion i8
indicated by 8etting the T bit of the SCON regi8ter.

RECEIVE - The STRT bit (logic zero (0)) on the RXD pin initiate8 data receive. The following two
condition8 mu8t be met: bit REN=1 and bit R=0. Both of them are 8tored in the SCON regi8ter. The R bit
i8 automatically 8et upon data reception i8 complete.

The Baud rate in thi8 mode i8 determined by the timer 1 overflow.
MODE 2

n mode 2, 11 bit8 are tran8mitted through the TXD pin or received through the RXD pin: a STRT bit
(alway8 0), 8 data bit8 (LSB fir8t), a programmable 9th data bit and a STOP bit (alway8 1). On tran8mit,
the 9th data bit i8 actually the TB8 bit of the SCON regi8ter. Thi8 bit u8ually ha8 a function of parity bit. On
receive, the 9th data bit goe8 into the RB8 bit of the 8ame regi8ter (SCON).The baud rate i8 either 132 or
164 the o8cillator frequency.
TRNSMIT - Data tran8mit i8 initiated by writing data to the SB&F regi8ter. End of data tran8mi88ion i8
indicated by 8etting the T bit of the SCON regi8ter.

RECEIVE - The STRT bit (logic zero (0)) on the RXD pin initiate8 data receive. The following two
condition8 mu8t be met: bit REN=1 and bit R=0. Both of them are 8tored in the SCON regi8ter. The R bit
i8 automatically 8et upon data reception i8 complete.




MODE 3
Mode 3 i8 the 8ame a8 Mode 2 in all re8pect8 except the baud rate. The baud rate in Mode 3 i8 variable.

The parity bit i8 the P bit of the PSW regi8ter. The 8imple8t way to check correctne88 of the received byte
i8 to add a parity bit to it. Simply, before initiating data tran8mit, the byte to tran8mit i8 8tored in the
accumulator and the P bit goe8 into the TB8 bit in order to be "a part of the me88age. The procedure i8
oppo8ite on receive, received byte i8 8tored in the accumulator and the P bit i8 compared with the RB8
bit. f they are the 8ame- everything i8 OK!
B&D RTE
Baud Rate i8 a number of 8entreceived bit8 per 8econd. n ca8e the &RT i8 u8ed, baud rate depend8
on: 8elected mode, o8cillator frequency and in 8ome ca8e8 on the 8tate of the SMOD bit of the SCON
regi8ter. ll the nece88ary formula8 are 8pecified in the table:

BUD RT E BI TSMOD
ode 0 Fosc. / 12

ode 1
1 Fosc.
16 12 (256-TH1)
BitSD
ode 2
Fosc. / 32
Fosc. / 64
1
0
ode 3
1 Fosc.
16 12 (256-TH1)



TMER 1 S CLOCK GENERTOR
Timer 1 i8 u8ually u8ed a8 a clock generator a8 it enable8 variou8 baud rate8 to be ea8ily 8et. The whole
procedure i8 8imple and i8 a8 follow8:
O Fir8t, enable Timer 1 overflow interrupt.
O Configure Timer T1 to operate in auto-reload mode.
O Depending on need8, 8elect one of the 8tandard value8 from the table and write it to the
TH1 regi8ter. That'8 all.
BUD RT E
FOSC. MHZ)
BI T SMOD
11.0592 12 14.7456 16 20
150 40 h 30 h 00 h

0
300 A0 h 98 h 80 h 75 h 52 h 0
600 D0 h CC h C0 h BB h A9 h 0
1200 E8 h E6 h E0 h DE h D5 h 0
2400 F4 h F3 h F0 h EF h EA h 0
4800

F3 h EF h EF h

1
4800 FA h

F8 h

F5 h 0
9600 FD h

FC h

0
9600

F5 h 1
19200 FD h

FC h

1
38400

FE h

1
76800

FF h

1
M&LTPROCESSOR COMM&NCTON
8 you may know, additional 9th data bit i8 a part of me88age in mode 2 and 3. t can be u8ed for
checking data via parity bit. nother u8eful application of thi8 bit i8 in communication between two or
more microcontroller8, i.e. multiproce88or communication. Thi8 feature i8 enabled by 8etting the SM2 bit
of the SCON regi8ter. 8 a re8ult, after receiving the STOP bit, indicating end of the me88age, the 8erial
port interrupt will be generated only if the bit RB8 = 1 (the 9th bit).
Thi8 i8 how it look8 like in practice:
Suppo8e there are 8everal microcontroller8 8haring the 8ame interface. Each of them ha8 it8 own
addre88. n addre88 byte differ8 from a data byte becau8e it ha8 the 9th bit 8et (1), while thi8 bit i8
cleared (0) in a data byte. When the microcontroller (ma8ter) want8 to tran8mit a block of data to one of
8everal 8lave8, it fir8t 8end8 out an addre88 byte which identifie8 the target 8lave. n addre88 byte will
generate an interrupt in all 8lave8 8o that they can examine the received byte and check whether it
matche8 their addre88.

Of cour8e, only one of them will match the addre88 and immediately clear the SM2 bit of the SCON
regi8ter and prepare to receive the data byte to come. Other 8lave8 not being addre88ed leave their SM2
bit 8et ignoring the coming data byte8.

8051 MCROCONTROLLER NTERR&PTS
There are five interrupt 8ource8 for the 8051, which mean8 that they can recognize 5 different event8 that
can interrupt regular program execution. Each interrupt can be enabled or di8abled by 8etting bit8 of the
E regi8ter. Likewi8e, the whole interrupt 8y8tem can be di8abled by clearing the E bit of the 8ame
regi8ter. Refer to figure below.
Now, it i8 nece88ary to explain a few detail8 referring to external interrupt8- NT0 and NT1. f the T0 and
T1 bit8 of the TCON regi8ter are 8et, an interrupt will be generated on high to low tran8ition, i.e. on the
falling pul8e edge (only in that moment). f the8e bit8 are cleared, an interrupt will be continuou8ly
executed a8 far a8 the pin8 are held low.
IE Reglster
(Interrupt
Enuble)

O E - global interrupt enabledi8able:
o 0 - di8able8 all interrupt reque8t8.
o 1 - enable8 all individual interrupt reque8t8.
O ES - enable8 or di8able8 8erial interrupt:
o 0 - &RT 8y8tem cannot generate an interrupt.
o 1 - &RT 8y8tem enable8 an interrupt.
O ET1 - bit enable8 or di8able8 Timer 1 interrupt:
o 0 - Timer 1 cannot generate an interrupt.
o 1 - Timer 1 enable8 an interrupt.
O EX1 - bit enable8 or di8able8 external 1 interrupt:
o 0 - change of the pin NT0 logic 8tate cannot generate an interrupt.
o 1 - enable8 an external interrupt on the pin NT0 8tate change.
O ET - bit enable8 or di8able8 timer 0 interrupt:
o 0 - Timer 0 cannot generate an interrupt.
o 1 - enable8 timer 0 interrupt.
O EX - bit enable8 or di8able8 external 0 interrupt:
o 0 - change of the NT1 pin logic 8tate cannot generate an interrupt.
o 1 - enable8 an external interrupt on the pin NT1 8tate change.


NTERR&PT PRORTES
t i8 not po88ible to for8een when an interrupt reque8t will arrive. f 8everal interrupt8 are enabled, it may
happen that while one of them i8 in progre88, another one i8 reque8ted. n order that the microcontroller
know8 whether to continue operation or meet a new interrupt reque8t, there i8 a priority li8t in8tructing it
what to do.
The priority li8t offer8 3 level8 of interrupt priority:
1. Re8et! The ap8olute ma8ter. When a re8et reque8t arrive8, everything i8 8topped and the
microcontroller re8tart8.
2. nterrupt priority 1 can be di8abled by Re8et only.
3. nterrupt priority 0 can be di8abled by both Re8et and interrupt priority 1.
The P Regi8ter (nterrupt Priority Regi8ter) 8pecifie8 which one of exi8ting interrupt 8ource8 have higher
and which one ha8 lower priority. nterrupt priority i8 u8ually 8pecified at the beginning of the program.
ccording to that, there are 8everal po88ibilitie8:
O f an interrupt of higher priority arrive8 while an interrupt i8 in progre88, it will be
immediately 8topped and the higher priority interrupt will be executed fir8t.
O f two interrupt reque8t8, at different priority level8, arrive at the 8ame time then the
higher priority interrupt i8 8erviced fir8t.
O f the both interrupt reque8t8, at the 8ame priority level, occur one after another, the one
which came later ha8 to wait until routine being in progre88 end8.
O f two interrupt reque8t8 of equal priority arrive at the 8ame time then the interrupt to be
8erviced i8 8elected according to the following priority li8t:
1. External interrupt NT0
2. Timer 0 interrupt
3. External nterrupt NT1
4. Timer 1 interrupt
5. Serial Communication nterrupt
P REGSTER (NTERR&PT PRORTY)
The P regi8ter bit8 8pecify the priority level of each interrupt (high or low priority).

O PS - Serial Port nterrupt priority bit
o Priority 0
o Priority 1
O PT1 - Timer 1 interrupt priority
o Priority 0
o Priority 1
O PX1 - External nterrupt NT1 priority
o Priority 0
o Priority 1
O PT - Timer 0 nterrupt Priority
o Priority 0
o Priority 1
O PX - External nterrupt NT0 Priority
o Priority 0
o Priority 1
HNDLNG NTERR&PT
When an interrupt reque8t arrive8 the following occur8:
1. n8truction in progre88 i8 ended.
2. The addre88 of the next in8truction to execute i8 pu8hed on the 8tack.
3. Depending on which interrupt i8 reque8ted, one of 5 vector8 (addre88e8) i8 written to the
program counter in accordance to the table below:
4.
I NTERRUPT SOURCE VECTOR DDRESS)
E0 3 h
TF0 B h
TF1 1B h
R T 23 h
All addresses are in hexadecimal format
5. The8e addre88e8 8tore appropriate 8ubroutine8 proce88ing interrupt8. n8tead of them,
there are u8ually jump in8truction8 8pecifying location8 on which the8e 8ubroutine8 re8ide.
6. When an interrupt routine i8 executed, the addre88 of the next in8truction to execute i8
poped from the 8tack to the program counter and interrupted program re8ume8 operation
from where it left off.

From the moment an interrupt i8 enabled, the microcontroller i8 on alert all the time. When an interrupt
reque8t arrive8, the program execution i8 8topped, electronic8 recognize8 the 8ource and the program
"jump8 to the appropriate addre88 (8ee the table above). Thi8 addre88 u8ually 8tore8 a jump in8truction
8pecifying the 8tart of appropriate 8ubroutine. &pon it8 execution, the program re8ume8 operation from
where it left off.
RESET
Re8et occur8 when the RS pin i8 8upplied with a po8itive pul8e in duration of at lea8t 2 machine cycle8
(24 clock cycle8 of cry8tal o8cillator). fter that, the microcontroller generate8 an internal re8et 8ignal
which clear8 all SFR8, except SB&F regi8ter8, Stack Pointer and port8 (the 8tate of the fir8t two port8 i8
not defined, while FF value i8 written to the port8 configuring all their pin8 a8 input8). Depending on
8urrounding and purpo8e of device, the RS pin i8 u8ually connected to a power-on re8et pu8h button or
circuit or to both of them. Figure below illu8trate8 one of the 8imple8t circuit providing 8afe power-on re8et.

Ba8ically, everything i8 very 8imple: after turning the power on, electrical capacitor i8 being charged for
8everal milli8econd8 throgh a re8i8tor connected to the ground. The pin i8 driven high during thi8 proce88.
When the capacitor i8 charged, power 8upply voltage i8 already 8table and the pin remain8 connected to
the ground, thu8 providing normal operation of the microcontroller. Pre88ing the re8et button cau8e8 the
capacitor to be temporarily di8charged and the microcontroller i8 re8et. When relea8ed, the whole
proce88 i8 repeated.
THRO&GH THE PROGRM- STEP BY STEP...
Microcontroller8 normally operate at very high 8peed. The u8e of 12 Mhz quartz cry8tal enable8
1.000.000 in8truction8 to be executed per 8econd. Ba8ically, there i8 no need for higher operating rate. n
ca8e it i8 needed, it i8 ea8y to built in a cry8tal for high frequency. The problem ari8e8 when it i8
nece88ary to 8low down the operation of the microcontroller. For example during te8ting in real
environment when it i8 nece88ary to execute 8everal in8truction8 8tep by 8tep in order to check O pin8'
logic 8tate.
nterrupt 8y8tem of the 8051 microcontroller practically 8top8 operation of the microcontroller and enable8
in8truction8 to be executed one after another by pre88ing the button. Two interrupt feature8 enable that:
O nterrupt reque8t i8 ignored if an interrupt of the 8ame priority level i8 in progre88.
O &pon interrupt routine execution, a new interrupt i8 not executed until at lea8t one
in8truction from the main program i8 executed.
n order to u8e thi8 in practice, the following 8tep8 8hould be done:
1. External interrupt 8en8itive to the 8ignal level 8hould be enabled (for example NT0).
2. Three following in8truction8 8hould be in8erted into the program (at the 03hex. addre88):

What i8 going on? 8 8oon a8 the P3.2 pin i8 cleared (for example, by pre88ing the button), the
microcontroller will 8top program execution and jump to the 03hex addre88 will be executed. Thi8 addre88
8tore8 a 8hort interrupt routine con8i8ting of 3 in8truction8.
The fir8t in8truction i8 executed until the pu8h button i8 reali8ed (logic one (1) on the P3.2 pin). The
8econd in8truction i8 executed until the pu8h button i8 pre88ed again. mmediately after that, the RET
in8truction i8 executed and the proce88or re8ume8 operation of the main program. &pon execution of any
program in8truction, the interrupt NT0 i8 generated and the whole procedure i8 repeated (pu8h button i8
8till pre88ed). n other word8, one button pre88 - one in8truction.
8051 MCROCONTROLLER POWER CONS&MPTON CONTROL
Generally 8peaking, the microcontroller i8 inactive for the mo8t part and ju8t wait8 for 8ome external 8ignal
in order to take8 it8 role in a 8how. Thi8 can cau8e 8ome problem8 in ca8e batterie8 are u8ed for power
8upply. n extreme ca8e8, the only 8olution i8 to 8et the whole electronic8 in 8leep mode in order to
minimize con8umption. typical example i8 a TV remote controller: it can be out of u8e for month8 but
when u8ed again it take8 le88 than a 8econd to 8end a command to TV receiver. The T89S53 u8e8
approximately 25m for regular operation, which doe8n't make it a pover-8aving microcontroller. nyway,
it doe8n't have to be alway8 like that, it can ea8ily 8witch the operating mode in order to reduce it8 total
con8umption to approximately 40u. ctually, there are two power-8aving mode8 of
operation:Idle and Power Down.

DLE MODE
&pon the DL bit of the PCON regi8ter i8 8et, the microcontroller turn8 off the greate8t power con8umer-
CP& unit while peripheral unit8 8uch a8 8erial port, timer8 and interrupt 8y8tem continue operating
normally con8uming 6.5m. n dle mode, the 8tate of all regi8ter8 and O port8 remain8 unchanged.
n order to exit the dle mode and make the microcontroller operate normally, it i8 nece88ary to enable
and execute any interrupt or re8et. t will cau8e the DL bit to be automatically cleared and the program
re8ume8 operation from in8truction having 8et the DL bit. t i8 recommended that fir8t three in8truction8 to
execute now are NOP in8truction8. They don't perform any operation but provide 8ome time for the
microcontroller to 8tabilize and prevent8 unde8ired change8 on the O port8.
POWER DOWN MODE
By 8etting the PD bit of the PCON regi8ter from within the program, the microcontroller i8 8et to Power
down mode, thu8 turning off it8 internal o8cillator and reduce8 power con8umption enormou8ly. The
microcontroller can operate u8ing only 2V power 8upply in power- down mode, while a total power
con8umption i8 le88 than 40u. The only way to get the microcontroller back to normal mode i8 by re8et.
While the microcontroller i8 in Power Down mode, the 8tate of all SFR regi8ter8 and O port8 remain8
unchanged. By 8etting it back into the normal mode, the content8 of the SFR regi8ter i8 lo8t, but the
content of internal RM i8 8aved. Re8et 8ignal mu8t be long enough, approximately 10mS, to enable
8table operation of the quartz o8cillator.
PCON REGSTER

The purpo8e of the Regi8ter PCON bit8 i8:
O SMOD Baud rate i8 twice a8 much higher by 8etting thi8 bit.
O GF1 General-purpo8e bit (available for u8e).
O GF1 General-purpo8e bit (available for u8e).
O GF0 General-purpo8e bit (available for u8e).
O PD By 8etting thi8 bit the microcontroller enter8 the Power Down mode.
O DL By 8etting thi8 bit the microcontroller enter8 the Idle mode.