Constructs in VHDL

Concurrent Statements
• All concurrent statements in an architecture are executed
simultaneously.
• Concurrent statements are used to express parallel activity as is the case with
any digital circuit.

• Concurrent statements are executed with no predefined order by the simulator

. So the order in which the code is written does not have any effect on its
function.

• They can be used for behavioral and structural and data flow descriptions.
 Concurrent statements contd.
• Process is a concurrent statement in which sequential
statements are allowed.
• All processes in an architecture are executed simultaneously.

• Concurrent statements are executed by the simulator when one of the

signals in its sensitivity list changes . This is called occurrence of an
‘event’.
eg : c <= a or b;
is executed when either signal ‘a’ or signal ‘b’ changes.
process(clk , reset) ...
is executed when either ‘clk’ or ‘reset’ changes

• Signals are concurrent whereas variables are sequential objects.

 Conditional signal assignment
• The ‘when‘ statement
– This type of assignment has one target but
multiple condition expressions.
– This statement assigns value based on the priority
of the condition.
– syntax
sig_name <= exp1 when condition1 else
exp2 when condition2 else
exp3;
entity my_nand is
port (a, b : in std_logic;
c : out std_logic);
end my_nand;
architecture beh of my_nand is
begin
c <= „0‟ when a = „1‟ and b = „1‟ else
„1‟ ;
end beh;

entity tri_state is
port (a, en : in std_logic;
b : out std_logic);
end tri_state;
architecture beh of tri_state is
begin
b <= a when en = „1‟ else
„Z‟;
end beh;
 example

architecture try_A of try is

begin
Y <= i1 when s1 = „0‟ and s0 = „0‟ else
i2 when s1 = „0‟ and s0 = „1‟ else
i3 when s1 = „1‟ and s0 = „0‟ else
i4 when s1 = „1‟ and s0 = „1‟ else
„0‟ ;
end try_A;

Incomplete specification is not allowed

 example

architecture when_grant of bus_grant is

signal …
begin
data_bus <= a and b when e1 = „1‟
else
e or f when a = b else
g & h when e3 = „1‟ else
(others => „Z‟);
end when_grant;
 Selective signal assignment
The with statement

• This statement is similar to the case statement

• syntax
with expression select
target <= expression1 when choice1
expression2 when choice2
expressionN when choiceN;
• all possible choices must be enumerated
• when others choice takes care of all the
remaining alternatives.
 Difference between with and when
statements
• Each choice in the with statement should be unique

• Compared to the ‘when’ statement, in the ‘with’ statement, choice is limited

to the choices provided by the with ‘expression’, whereas for the ‘when’
statement each choice itself can be a separate expression.

• The when statement is prioritized (since each choice can be a different

expression, more than one condition can be true at the same time, thus
necessitating a priority based assignment) whereas the with statement does
not have any priority (since choices are mutually exclusive)
entity my_mux is
port (a, b, c, d : in std_logic;
sel0, sel1 : in std_logic;
e : out std_logic);
end my_mux;

architecture my_mux_A of my_mux is

signal sel: std_logic_vector(1 downto 0);
begin
sel <= sel1 & sel0;
with sel select
e <= a when “00”
b when “01”
c when “10”
d when others;
end my_mux_A;
 Component Instantiation
• A component represents an entity architecture pair.
• Component allows hierarchical design of complex circuits.

• A component instantiation statement defines a part lower in the hierarchy of

the design entity in which it appears. It associates ports of the component
with the signals of the entity. It assigns values to the generics of the
component.

• A component has to be declared in either a package or in the declaration

part of the architecture prior to its instantiation.
 Component Declaration and
• Syntax(Declaration) Instantiation
component component_name
[generic list]
[port list]
end component;

• Syntax(Instantiation)
label:component_name
[generic map]
port map;
entity my_and is
U1: my_and
port( a : in std_logic;
generic map (tpd => 5 ns)
b : in std_logic;
port map (x => a,
c : out std_logic);
y => b,
end my_and;
z => temp);
architecture my_and_A of my_and is
component and2
generic (tpd: time := 2 ns);
port (x : in std_logic;
y : in std_logic;
z : out std_logic); U2: my_and
end component; generic map (tpd => 2 ns)
signal temp : std_logic; port map (x => a,
begin y => b,
c <= temp; z => temp);
-- component instantiation here
end my_and_A;
architecture exor_A of exor is
component my_or u1 : my_or
port (a : in std_logic; port map (y2,
b : in std_logic; y3,
y : out std_logic y1);
); u2 : my_and
end component; port map (a_n,
component my_and b,
port (a : in std_logic; y2);
b : in std_logic; u3 : my_and
y : out std_logic port map (a,
); b_n,
end component; y3);
signal a_n, b_n : std_logic;
signal y1, y2, y3 : std_logic; a_n <= not a ;
begin b_n <= not b ;
. . . . .
end exor_A;
Component Instantiation contd.
Positional association
U1: my_and
generic map(5 ns)
port map(a, b, temp);

Named Association
U1:my_and
generic map (tpd => 5 ns)
port map (x => a,
y => b,
z => temp);

The formal and the actual can have the same name
 Component Instantiation contd.

• Named association is preferred because it makes the code more

readable and pins can be specified in any order whereas in positional
association order should be maintained as defined in the component
and all the pins need to be connected .

• Multiple instantiation of the same component should have different

labels.
 Process statement
• The process statement is a concurrent statement , which delineates a part
of an architecture where sequential statements are executed.
• Syntax
label: process [(sensitivity list )]
declarations
begin
sequential statements
end process;
Process statement
• All processes in an architecture are executed concurrently with all other
concurrent statements.

• Process is synchronized with the other concurrent statements using the

sensitivity list or a wait statement.

• Process should either have sensitivity list or an explicit wait statement.

Both should not be present in the same process statement.

• The order of execution of statements is the order in which the statements

appear in the process

• All the statements in the process are executed continuously in a loop .

 Process contd.

• The simulator runs a process when any one of the signals in the sensitivity
list changes. For a wait statement, the simulator executes the process after
the wait is over.

• The simulator takes 0 simulation time to execute all the statements in the
process. (provided there is no wait)
process
begin
if (reset = „1‟) then
A <= „0‟ ;
elsif (clk‟event and clk = „1‟) then
A <= „B‟;
end if;
wait on reset, clk;
end process;

process (clk,reset)
begin
if (reset = „1‟) then
A <= „0‟;
elsif (clk‟event and clk = „1‟) then
A <= „B‟;
end if;
end process;
 Sequential Statements
• Sequential statements are statements which are analyzed
serially one after the other. The final output depends on the
order of the statements, unlike concurrent statements where
the order is inconsequential.

• Sequential statements are allowed only inside process and subprograms

(function and procedure)

• Process and subprograms can have only sequential statements within

them.

• Only sequential statements can use variables.

• The Process statement is the primary concurrent VHDL statement used to

describe sequential behaviour.
Sequential Statements contd.

• Sequential statements can be used to generate

– Combinational logic
– Sequential logic
• Clocked process
It is easily possible to infer flip-flops using if
statements and ‘event attribute.
• Combinatorial process
generates purely combinatorial logic.
All the inputs must be present in the sensitivity
list. Otherwise the simulation and synthesis
results will not match.
The if statement

• Syntax
if condition1 then
statements
[elsif condition2 then Priority
statements]
[else
statements]
end if;
• An if statement selects one or none of a sequence of events to
execute . The choice depends on one or more conditions.
The if statement contd.

if sel = „1‟ then if (sel = “00”) then

c <= a; o <= a;
else elsif sel = “01” then
c <= b; x <= b;
end if; elsif (color = red) then
y <= c;
else
o <= d;
end if;

• If statements can be nested.

• If statement generates a priority structure

• If corresponds to when else concurrent statement.

 The case statement - syntax

case expression is
when choice 1 =>
statements
when choice 3 to 5 =>
statements
when choice 8 downto 6 =>
statements
when choice 9 | 13 | 17 =>
statements
when others =>
statements
end case;
 The case statement
• The case statement selects, for execution one of a number of alternative
sequences of statements .

• Corresponds to with select in concurrent statements .

• Case statement does not result in prioritized logic structure unlike the if
statement.
 The case statement contd.

process(sel, a, b, c, d)
process (count) begin
begin case sel is
case count is when “00” =>
when 0 => dout <= a;
dout <= “00”; when “01” =>
when 1 to 15 => dout <= b;
dout <= “01”; when “10” =>
when 16 to 255 => dout <= c;
dout <= “10”; when “11” =>
when others => dout <= d;
null; when others =>
end case; null;
end process; end case;
end process;
 Think Hardware! (Mutually exclusive
conditions)
myif_pro: process (s, c, d, e, f)
begin
if s = "00" then
pout <= c;
elsif s = "01" then
pout <= d;
elsif s = "10" then
pout <= e;
else
pout <= f;
end if;
end process myif_pro;

This priority is useful for timings.

 Think Hardware! Use a case for mutually
exclusive things
mycase_pro: process (s, c, d, e, f)
begin
case s is
when "00" =>
pout <= c; C
when "01" =>
pout <= d; D POUT
when "10" =>
E
pout <= e;
when others => F
pout <= f;
end if; S
end process mycase_pro;
There is no priority with case