International Journal of Recent Technology and Engineering (IJRTE)

ISSN: 2277-3878, Volume-8, Issue-2S3, July 2019

Design of Low Power and High Speed 4X4

Multiplier using Modified Column Bypassing
Scheme for DSP Applications
E.Srinivas, N.Sharath Babu, G.Sreenivasa Raju 

ABSTRACT--- In this paper a low power and high speed 4X4 The product P=Pn-1,Pn-2,Pn-3……….P0 [5]. Array
multiplier is designed using CMOS Technology. The important multiplier is close to regular architecture[3]. Multiplier
factors in VLSI Design are power, area, speed and design time. circuit based on add and shifts algorithms. In digital
Now-a-days, power and speed has become a crucial factor in
electronic world Bypassing multipliers very much needed to
Digital Signal Processor (DSP) Applications. However, different
optimization techniques are available in the digital electronic save the power consumption of architecture.
world. The proposed approach a Low power and high speed
Multiplier Design based on Modified Column bypassing III. BYPASS MULTIPIERS:
technique mainly used to reduce the switching power activity.
The main motivation behind the realization of the Bypass
While this technique offers great dynamic power savings, due to
their interconnection. In this work, a low power and high speed Multipliers reduced area and fast speed [6]. While coming in
multiplier with Hybridization scheme is presented. This scheme is to operation Types of Bypassing schemes are Row
combination of booth encoder algorithm and column bypass Bypassing schemes and Column bypassing schemes. Row
technique is called modified column bypassing scheme. The bypassing technique is based on number of zeros in
simulations are performed in 0.18µm CMOS Technology in the multiplier bits. In this multiplier operation, some rows of
Cadence Virtuoso tools with operating voltage ±1.8v.
adders in the basic multiplier array are disabling during
Keywords: Multiplier, CMOS, Column Bypassing, Digital
Signal Applications (DSP), Row Bypassing, Booth encoder
operation to save the power [8]. The internal structure of
the row bypassing adder cell is shown below Fig. 1. Row
I. INTRODUCTION Bypassing Multiplier shown in Fig. 2. In this architecture
contains 4-bit two numbers and 8 partial products. The
Multiplication is one of the basic building block in all inputs are A0,B0,A1,B1,A2,B2,A3,B3&A4,B4 and partial
digital processors ,digital filters ..,etc. the basic operation of products are P0,P1,P2,P3,P4,P5,P6 and P7.
two number multiplication is first number is multiplication
and second number is multiplicand; both can called factors
[1]. In VLSI Integrated Circuit Design have two approaches,
First is Analog IC Design and second one is Digital IC
Design but digital IC design somewhat more accuracy
compared to analog IC design. So most of the digital
integrated circuits are popular as compared to Analog design
[2]. Generally different types of multiplier architectures are
available in the electronic world. The types of multiplier Fig:1 Structure of Row bypassing
architectures are booth multiplier, Braun multiplier, Row
bypassing multiplier and column bypassing multiplier.,etc.
among all the multipliers column bypassing architecture are
designed in this paper.

II. MULTIPLIERS:
The multiplier architecture can be generally classified in
to the following categories: series, parallel and series-
parallel. The series multiplier uses a successive addition
algorithm. Parallel Array Multiplier Consider the
multiplication of two unsigned n-bit numbers, where A=An-
1,An-2,An-3……………………A0 is the multiplicand and
B=Bn-1,Bn-2,Bn-3…………………B0 is the multiplier.

Revised Manuscript Received on July 10, 2019.

E.Srinivas, Assoc.Professor ,Department of ECE, Anurag Group Of
Institutions, Hyderabad, Telangana, India [email protected] Fig: 2 Row bypassing Multiplier
N.Sharath Babu, Asst.Professor,Department of ECE, Anurag Group
Of Institutions, Hyderabad, Telangana, India [email protected]
G.Sreenivasa Raju Assoc.Professor,Department of ECE, Anurag
Group Of Institutions, Hyderabad, Telangana, India
([email protected])

Published By:
Retrieval Number: B11180782S319/19©BEIESP Blue Eyes Intelligence Engineering
DOI : 10.35940/ijrte.B1118.0782S319 643 & Sciences Publication
DESIGN OF LOW POWER AND HIGH SPEED 4X4 MULTIPLIER USING MODIFIED COLUMN BYPASSING
SCHEME FOR DSP APPLICATIONS
Fig. 3 shows the Column bypassing Multiplier Products analysis applied to reaming sums such as S5, S6 and S7 in
architecture. It contains input 4-bit Two numbers and output the multiplier architecture.
have 8 partial product such as P0,P1,P2,P3,P4,P5,P6 and
P7[9,10]. Hybrid bypassing multipliers can be verified by IV. SIMULATION RESULTS
the number of zeros in either the multiplicand or multiplier The proposed multiplier and conventional multiplier
to predict. Whether the operation completed in one cycle or comparison is made in terms of power consumption, power
two cycle. dissipation and delay. The designed circuits are drawn in
cadence virtuoso schematic diagram and simulation are done
in cadence analog Design Environment. The Results of
proposed multiplier are compared with conventional design.
This architecture useful to design multipliers such as 16-bit
and 8-bit multiplication. The comparison of power
consumption at different operating frequencies ranging from
1 MHz to 333.3 MHz is shown in Table 1.
Fig. 5 shows the schematic diagram of 2X1 Multiplexer.
The basic operations of 2X1 multiplexer have two inputs,
one selection line and one output. The schematic diagram
drawn in analog design environment schematic editor.

Fig: 3 Column bypassing Multiplier Products

A proposed architecture for implementing the 4-bit

multiplier using modified column bypassing multiplier with
is shown in Fig. 4. The modified column bypassing
multiplier proposed the hybridization of booth encoding
algorithm and

Fig.5 Schematic Diagram of 2x1 MUX

Fig: 4 a proposed circuit for implementing the 4-bit Fig .6 shows the 2x1 multiplexer output waveforms are
multiplier simulated in cadence tools. The output wave forms are two
input’s, four combinations, two selection lines and one
Fig 4 shows the proposed 4-bit multiplier architecture. output are presented. The combination that is two inputs are
The sum and carry out is bottom architecture. The Partial zero and selection line is zero, the output becomes zero. If
products are accumulated (i.e. multiply and accumulate). two inputs are one, the output is one. If input A becomes 1
Once the circuit first sum (S1) is the direct sum of two and B Becomes 0, the selection line is zero the output is 1
partial products, A1B0 and A0.B1. Second sum (S2) and the selection line is 1 the output is 0. Generally
contains three partial product are added with this two adders multiplexer is also called as data selector. Why because the
and carry out from first sum (S1) Column is required. Third data selecting based on the selection lines. Multiplexer
sum (S3) is a little bit complex. Why because two different blocks are used in many digital design circuits.
carryout from previous column. Here three cascaded adders,
two full adders and one Half adders required [11]. S4
requires three products and carry outs from S3. Similar

Published By:
Retrieval Number: B11180782S319/19©BEIESP Blue Eyes Intelligence Engineering
DOI : 10.35940/ijrte.B1118.0782S319 644 & Sciences Publication
 International Journal of Recent Technology and Engineering (IJRTE)
ISSN: 2277-3878, Volume-8, Issue-2S3, July 2019

Fig. 9 Shows the Schematic diagram of OR gate, The OR

Gate drawn in Analog design Environment
In cadence tools. OR Gate contains two inputs and one
output.

Fig 6. Output Put Waveform of 2x1 MUX

Fig. 7 Shows the Schematic Diagram of AND Gate,
The basic operation of AND carries multiplication and
one output.

Fig 9: Schematic diagram of OR gate

Fig. 10 Shows the Output waveform of OR Gate. This

Output window contains two input waveform and one
output waveform. If Inputs A and B are zero, the output is
zero. Otherwise the output becomes one.

Fig.7: Schematic Diagram of AND Gate

Fig. 8 Shows the Output Waveform of AND gate,
The gate contains two inputs and one output. For
Example if input A and B are becomes zero the output
becomes zero. If A and B becomes are one, the output
becomes one. If any one of the input is zero the output
becomes zero.

Fig 10: output waveform of OR Gate

Fig. 11 Shows the Schematic Diagram of XOR gate. The
basic operation of XOR Gate is any one input is high the
output is high. Schematic Diagram of XOR Gate is drawn
and simulated in cadence tool.

Fig 8: Output Wave form AND Gate

Published By:
Retrieval Number: B11180782S319/19©BEIESP Blue Eyes Intelligence Engineering
DOI : 10.35940/ijrte.B1118.0782S319 645 & Sciences Publication
DESIGN OF LOW POWER AND HIGH SPEED 4X4 MULTIPLIER USING MODIFIED COLUMN BYPASSING
SCHEME FOR DSP APPLICATIONS

Fig 14: Output Wave form of Proposed 4x4 Multiplier

Fig 15: Power Consumption of Proposed Multiplier

circuit. The proposed multiplier have power consumption is
3.4µwatts.

Fig 11: Schematic Diagram of XOR Gate

Pc=3.4µwatts
Fig. 12 shows the Output Waveform of XOR gate. The
output waveforms have two inputs and one output. Fig 15: Power Consumption of Proposed Multiplier
circuit

Table 1: shows the Comparison of Multiplier.

In Conventional Design, the power dissipation is
11.34nwatts, the power consumption is 94µwatts and delay
is 23ns. While proposed design the power dissipation is
2.4nwatts ,power consumption is 3.5µwatts and delay is
10ns. Finally prosed design have superior results compared
to Conventional design.

Table 1: Comparison Table of Multiplier Circuit

Parameters Conventional Proposed
design design
Fig 12: Output Waveform of XOR Gate
Power Supply 1.8v 1.8v
Fig. 13 Shows the Schematic Diagram of Proposed 4X4 Power Dissipation 11.34nwatts 2.4nwatts
Multiplier. The Schematic diagram drawn in analog
schematic editor in cadence tools Power Consumption 94µwatts 3.5µwatts

Delay 23ns 10ns

V. CONCLUSION
A low power, high speed 4x4 multiplier using a modified
column bypassing Architecture is designed. This
architecture achieved better results like reduces the power
consumption and propagation delay. The Simulation results
show that proposed multiplier facilitates reduction of power
and area occupancy compared to conventional design. This
method is valid for both signed and unsigned operands.
Fig 13: Proposed Schematic Diagram of4x4 Multiplier

Fig. 14 Shows the Proposed output waveform of 4X4

Multiplier. The output window contains the waveform s of
4X4 multiplier.

Published By:
Retrieval Number: B11180782S319/19©BEIESP Blue Eyes Intelligence Engineering
DOI : 10.35940/ijrte.B1118.0782S319 646 & Sciences Publication
 International Journal of Recent Technology and Engineering (IJRTE)
ISSN: 2277-3878, Volume-8, Issue-2S3, July 2019

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Published By:
Retrieval Number: B11180782S319/19©BEIESP Blue Eyes Intelligence Engineering
DOI : 10.35940/ijrte.B1118.0782S319 647 & Sciences Publication