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Assignment 1

The document contains an assignment for a Computer Organization and Architecture course. It includes 8 questions related to digital computer systems and their hardware design. The questions cover topics like designing a 4-bit parallel adder/subtractor, implementing a common bus system using registers and multiplexers, formulating a control word for an ALU, implementing register transfers using multiplexers, evaluating an arithmetic expression using assembly instructions, performing multiplication using Booth's algorithm, and designing a 4-bit arithmetic circuit.

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PULKIT KUMAR 21SCSE1420057
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24 views

Assignment 1

The document contains an assignment for a Computer Organization and Architecture course. It includes 8 questions related to digital computer systems and their hardware design. The questions cover topics like designing a 4-bit parallel adder/subtractor, implementing a common bus system using registers and multiplexers, formulating a control word for an ALU, implementing register transfers using multiplexers, evaluating an arithmetic expression using assembly instructions, performing multiplication using Booth's algorithm, and designing a 4-bit arithmetic circuit.

Uploaded by

PULKIT KUMAR 21SCSE1420057
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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SCHOOL OF COMPUTING SCIENCE AND ENGINEERING

ASSIGNMENT
Course Name: Computer Organization and Architecture Course Code: E2UC505T

Submission Deadline: Jan. 21, 2024

Q.1 Draw the hardware design to show that how a 4-bit parallel adder can operate in both as adder and subtractor.

Q.2 Design a common bus system for a digital computer system with four 4-bit registers. Instead of utilizing
multiplexers, use three-state buffers and a decoder in the design of this bus.

Q.3 A bus organized CPU based on general register organization has 16 registers with 32 bits in each, an ALU,
and a destination decoder.

a. How many multiplexers are there in the A bus, and what is the size of each multiplexer.
b. How many selection inputs are needed for MUX A and MUX B?
c. How many inputs and outputs are there in the decoder?
d. How many inputs and outputs are in the ALU for data, including input and output carries?
e. Formulate a control word for the system assuming that the ALU has 65 operations.

Q.4 Using multiplexer, design a common bus system for a digital computer system with four 4-bit registers.

Q.5 The outputs of four registers, R0, R1, R2 and R3, are connected through 4X1 multiplexers to the inputs of a
fifth register, R5. Size of each register is of 8 bit. The specified transfers are determined by four timing variables
P0 through P3 as given below.

P0: R5<---R0

P1: R5<---R1

P2: R5<---R2

P3: R5<---R3

The timing variables are mutually exclusive, signifying that only one variable equals 1 at any given time, with the
other three set to 0. Illustrate a block diagram that displays the hardware implementation of the register transfers.
Include the essential connections from the four timing variables to the selection inputs of the multiplexers and to
the load input of the register R5.

Q.6 Write the program to evaluate the following arithmetic statement using zero, one, two, or three address
instructions.

X = (A +B) * (C + D)

Q7. Calculate values of following using Booth's Algorithm.

(a) (5) X (7) (b) (5) X (-7)

Q8. Design a 4-bit arithmetic circuit that can perform addition, subtraction, increment and decrement micro-
operations and explain its working.

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