Architecture
Architecture
Explain the purpose of the MAR (Memory Address Register) and why its needed?
Explain the purpose of the MDR (Memory Data Register) and why its needed?
Explain the purpose of the Program Counter and why it's needed?
Explain the purpose of the ALU (Arithmetic Logic Unit)and why it's needed?
Explain the purpose of the CU (Control Unit) and why it's needed?
Explain the core function of the CPU as fetch and execute instructions stored in memory
Using http://peterhigginson.co.uk/LMC/
And the following code
inp
sta 8
inp
add 8
out
Explain what is happening during the fetch decode execute cycle.
1.1 -Systems Architecture Workbook
Explain how common characteristics of CPUs affect their performance:
clock speed, cache size, number of cores
Give examples of embedded systems along with what inputs, processing and outputs
they have
QUESTION 1
Ann wants to purchase a new computer and is looking at two models. The specification
of the CPU in each computer is shown below.
When running a 3D flight simulator, Computer 1 is likely to run faster than Computer 2.
Using the information above, identify one reason for this.
[1]
Explain one reason why the cache size affects the performance of the CPU.
[2]
Identify four events that take place during the fetch-execute cycle.
1.1 -Systems Architecture Workbook
[4]
Gareth has a satellite navigation system (Sat Nav) which contains an embedded
system. Define what is meant by an ‘embedded system’.
[1]
Identify three devices, other than a Satellite Navigation system, that contain
embedded systems.
[3]
QUESTION 3
Here are some statements about the CPU of a computer. Tick one box in each row to
show whether each of the following statements is true or false.
Statement True False
[5]
QUESTION 4
Dipesh is thinking of buying a tablet computer to replace his old desktop computer.
Describe how the CPU and RAM work together to enable the tablet computer to
operate.
[3]
The tablet computer also uses cache memory. Describe the purpose of cache memory.
[2]
QUESTION 5
1.1 -Systems Architecture Workbook
Quinn’s current computer specification is shown below.
[2]
Question 12: The part of a processor in which instructions are executed is known as? (1-4) ✔
Core
Centre
Execution
Instruction Centre
Question 13: What acts as an intermediary between the processor and the Main Memory? (6-9) ✔
Bus
User
Cache
Clock
Question 17 If the processing speed goes up from 2GHZ to 4GHZ and the number of cores goes ✔
1.1 -Systems Architecture Workbook
from 1 to 2 – what is the exact effect on the performance of the computer? (5-6)
Doubled
Quadrupled
Eight Times faster
Sixteen times faster
Question 18 If the processing speed goes up from 2GHZ to 4GHZ and the number of cores goes
from 1 to 4 – what is the exact effect on the performance of the computer? (5-6) ✔
Doubled
Quadrupled
Eight Times faster
Sixteen times faster
Question 19 If the processing speed goes up from 1GHZ to 4GHZ and the number of cores goes
from 1 to 2 – what is the exact effect on the performance of the computer? (5-6) ✔
Doubled
Quadrupled
Eight Times faster
Sixteen times faster
Question 20 If the processing speed goes up from 1GHZ to 4GHZ and the number of cores goes
from 1 to 8 – what is the exact effect on the performance of the computer? (5-6) ✔
Eight Times faster
Sixteen times faster
Thirty Two times faster
Sixty Four times faster
Question 21: What component holds the address of the next instruction (7-9) ✔
Memory Address Register
Memory Data Register
Program Counter
Accumulator
Question 23: This holds the instruction/data temporarily after it is brought to the processor from the ✔
1.1 -Systems Architecture Workbook
main memory (7-9)
Question 24: This holds the number of the current instruction being worked on (7-9) ✔
Memory Address Register
Memory Data Register
Program Counter
Accumulator
Question 25: This would perform an operation including the word “And” (5-7) ✔
Arithmetic Logic Unit
Accumulator
Cache
Control Unit
Question 26: This would send a signal such as “Memory Read” (5-7) ✔
Arithmetic Logic Unit
Accumulator
Cache
Control Unit
Question 28: This would reduce the number of memory/processor transfers (5-7) ✔
Arithmetic Logic Unit
Accumulator
Cache
Control Unit
Question 31: This doesn’t happen during the Fetch part of the cycle: (7-9) ✔
Address Bus is used
Program Counter increments by one
Arithmetic operations are performed
Main Memory is addressed
Question 32: This doesn’t happen during the Decode / Execute part of the cycle: (7-9) ✔
Current Instruction is held in the CIR
Results are held in the Accumulator
Status Register updated
Instructions are transferred from Main Memory
Question 34: Carries address of the next instruction that will be fetched (4-6) ✔
Address Bus
Data Bus
Control Bus
System Bus