IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

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Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits

Yu Wang, Member, IEEE, Ku He, Rong Luo, Member, IEEE, Hui Wang, and Huazhong Yang, Senior Member, IEEE
AbstractSleep transistor (ST) insertion is a valuable leakage reduction technique in circuit standby mode. Fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improve circuit noise margins. In this paper, we introduce a novel two-phase FGSTI technique which consists of ST placement and ST sizing. These two phases are formally modeled using mixed integer linear programming (MILP) models. When the circuit timing relaxation is not large enough to assign ST everywhere, leakage feedback (LF) gates, which are used to avoid oating states, induce large area and dynamic power overhead. An extended multi-object ST placement model is further proposed to reduce the leakage current and the LF gate number simultaneously. Finally, heuristic algorithms are developed to speed up the ST placement phase. Our experimental results on the ISCAS85 benchmarks reveal that: 1) the two-phase FGSTI technique achieves better results than the simultaneous ST placement and sizing method; 2) when the circuit timing relaxation varies from 0% to 5%, the multi-object ST placement model can achieve on average 4 -9 LF gate number reduction, while the leakage difference is only about 8% of original circuit leakage; 3) our heuristic algorithm is 1000 faster than the MILP method within an acceptable loss of accuracy. Index TermsFine-grain sleep transistor insertion, leakage feedback gate, leakage reduction, mixed integer linear programming (MILP).

[1], while the behavior of the short circuit power dissipation remains at around 10% of the total power dissipation [2]. As technology scales, leakage power is becoming a major portion of the total power consumption, for example, leakage power is reported to make up about 40% of total power at the 90-nm technology node [3]. Large leakage current will degrade noise immunity in dynamic circuits, increase the standby power dissipation to unacceptable levels, and lead to excessive heating; all of these may cause circuits fail to function properly [4]. Inevitably, many techniques have been proposed to reduce the increasing leakage power. Besides architecture level techniques [4], leakage control techniques can be broadly categorized into two main categories: process level and circuit level techniques [5]. At the process level, leakage reduction can be achieved by controlling the dimensions (length, oxide thickness, junction depth, etc.) and doping prole in transistors. Circuit level techniques include transistor stacking [6], input vector control [7], body biasing [8], multi- assignment [9][11], dynamic scaling (DVTS) [12], variable supply voltage [13], cell resizing [14], and leep transistor insertion. Among these circuit level techniques, sleep transistor insertion is the most effective one when the circuit is standby [15]. A. Multi-Threshold CMOS Techniques Sleep transistor (ST) insertion technique is essentially placing an ST between the gates and the power/ground (P/G) net. In burst mode circuits, where the system spends the majority of the time in an idle standby state, ST insertion is proven to be a very effective technique for leakage current reduction during the standby mode [15][24]. STs can be inserted into the circuit by two different manners: global and local [22]. Thus, we classify ST insertion techniques into block-based ST insertion [as shown in Fig. 1(a)] and ne-grain ST insertion (FGSTI) [as shown in Fig. 1(b)] according to different ST insertion manners. 1) Block-Based ST Insertion (BBSTI): The most popular ST insertion technique is gating the power supply of sizable blocks using large STs [15]. This is concluded as BBSTI technique. In a BBSTI technique, all the gates in one block have a xed timing relaxation, so it is also called xed slowdown method. The previous works on BBSTI techniques [16][20] presented some methods on clustering gates into blocks in order to optimize the leakage current and ST sizes. All these methods focus on how to reduce the ST area penalty along with a remarkable leakage saving. J. Kao et al. [16] presented the rst method to automatically size ST of a large block based on mutual exclusive discharge patterns of internal blocks. M. Anis et al. [17], [18] developed a cluster-based design structure to avoid putting a larger ST in the center of a large block: the whole circuit is divided into small

I. INTRODUCTION

OWER consumption is becoming a rst-order design criterion. The total power dissipation consists of dynamic power, short circuit power, and leakage power, thus, can be expressed as

where is the operation frequency, is the supply voltage, and is total gate number. , , , and are the transition probability, load capacitance, leakage current, and short circuit charge of the th gate, respectively. Leakage power dissipation has become comparable to switching power dissipation
Manuscript received September 6, 2006; revised July 10, 2007. Published August 20, 2008 (projected). This work was supported in part by National Natural Science Foundation of China under Contract 90207002 and Contract 60506010 and by the National 863 Project of China under Contract 2006AA01Z224. This is a revised and expanded version based on two papers accepted by ISLPED 2006 and APCCAS 2006. The authors are with the Circuits and Systems Division, Electronics Engineering Department, Tsinghua University, Beijing, 100084, China (e-mail: [email protected]). Digital Object Identier 10.1109/TVLSI.2008.2000523

1063-8210/$25.00 2008 IEEE

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make a detailed comparison between local and global ST insertion. Recently, V. khandelwal et al. [23] presented a selectively ST insertion methodology with better utilization of circuit slack. They used A one-shot algorithm to determine where to put ST in the FGSTI design considering leakage feedback gates, but they did not address how to perform the FGSTI technique when the circuit slowdown is 0%. Also, the one-shot algorithm may easily leads to a local optimal result. Our previous work [24] introduced a mixed integer linear programming (MILP) model for the FGSTI technique to determine ST placement and sizing simultaneously without considering LF gate. The MILP model leads to an accurate result, but its computation time is considerably long. B. Our Contributions In this paper, we proposed a two-phase FGSTI technique that has the following contributions. 1) Simple leakage current and delay models of a single gate are presented. To the best of our knowledge, our leakage current model analysis is the rst to provide the designer the negligible dependence of ST size on the amount of leakage saving, and makes the two-phase FGSTI reasonable. 2) The two phases of our FGSTI technique: a) ST placement and b) ST sizing, are modeled using MILP and LP models, respectively. Fewer variables and constraints with less approximation are used in the models, so that our two-phase FGSTI technique is more accurate and faster comparing with our previous simultaneous ST placement and sizing method using MILP [24]. The ST placement phase can achieve an impressive leakage saving when the conventional xed slowdown method can not be performed. Furthermore, if the circuit timing relaxation is large enough to use conventional xed slowdown method, our ST sizing still leads to a much smaller total ST size. 3) LF gate and normal ST gate are compared to prove that a carefully sized LF gate can substitute for a normal ST gate without affecting the circuit performance. An extended multi-object ST placement model is presented to provide the designer the relationship between LF gate number and the leakage current reduction rate. Our experimental results show that, when the circuit slowdown is 0%, comparing with the method only considering the leakage current reduction, on average 4 LF gate number reduction can be achieved; meanwhile the leakage current difference between our method and the method only considering leakage current reduction is only about 7.9% of the original circuit leakage. 4) Since the computation time for solving MILP model is not stable and may be considerably long, fast heuristic algorithms are developed for ST placement phase with simultaneous LF gate reduction. Our simple algorithms are investigated from intuition thinking to detailed implementation to show their effectiveness. On average 1000 speed up can be achieved using our heuristic algorithm compared with an MILP solver, while the loss of accuracy is acceptable. This paper is organized as follows. In Section II, our leakage current and delay models are rst presented and then analyzed to prove the rationality of our two-phase FGSTI technique; LF

Fig. 1. FGSTI versus BBSTI.

blocks with several gates in one block; they presented several fast heuristic techniques for efcient gate clustering and optimized the ST size for each block according to the current of the block. C. Long et al. [19], [20] proposed a distributed sleep transistor network (DSTN) approach in which all the STs are connected to further reduce the area penalty and improve the circuit performance. BBSTI techniques greatly reduce the area penalty, but in the P/G network they induce large ground bounce which has adverse effects on circuit speed and noise immunity [23]. Additional delay, about 5% circuit propagation time, must be suffered from because of ST insertion. Furthermore, for each block, ST size is decided by the worst case current which is quite difcult to determine without comprehensive simulation [17]. So it is harder to guarantee circuit functionality for large blocks with only one ST [22]. 2) Fine-Grain ST Insertion (FGSTI): In recent years, the FGSTI technique [21][24], which can be also called the gate level ST insertion, shows some advantages over the BBSTI technique. It is easier to guarantee circuit functionality in the FGSTI technique because ST sizes are not determined by the worst case current of large circuit blocks. The FGSTI technique leads to a smaller simultaneous switching current when the circuit mode changes between standby and active, thus improves circuit noise margins. Furthermore, better circuit slack utilization is achieved because the slowdown of each gate is not xed, and this leads to further leakage and area reduction [23]. V. khandelwal et al. [23] pointed out that the FGSTI technique corresponded to an area penalty of roughly only 5% using standard cell placement. When the circuit slowdown is not enough to assign STs everywhere in the FGSTI technique, a large amount of leakage feedback (LF) gates may be used to avoid oating states [21]. As it will shown in our results, the LF gate number may exceed as much as 80% of the gates with ST for certain circuits when LF gate is not considered in the FGSTI technique; the additional inverters in the LF gates will induce large area and dynamic power penalty. B. H. Calhoun et al. [22] proposed a ne-grain ST insertion design methodology and several design rules. The authors also

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WANG et al.: TWO-PHASE FINE-GRAIN SLEEP TRANSISTOR INSERTION TECHNIQUE IN LEAKAGE CRITICAL CIRCUITS

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TABLE I LEAKAGE CURRENT IN NOR2XL AND NAND4XL (fA). (180-nm TECHNOLOGY)

gate and normal ST gate are compared in Section II-D. The two-phase FGSTI technique formulated using MILP model is proposed in Section III. Section IV introduces our heuristic algorithms for ST placement phase. The implementation and experimental results are presented and analyzed in Section V. In Section VI, we conclude this paper. II. PRELIMINARIES In this section, leakage current and delay models used in our two-phase FGSTI technique are rst proposed. The models are examined to prove that an FGSTI design can be performed in two phases. Finally, LF gate and normal ST gate are compared to prove that an LF gate can substitute for a normal ST gate without affecting the circuit performance. ST with variable size decided by the process technology are used in our two-phase FGSTI design. In this paper, a combinational circuit is modeled by a directed . A vertex represents acyclic graph (DAG) a CMOS gate from the given library, while an edge , represents a connection from vertex to vertex . is used to measure the size of a ST, because is a constant that equals the minimum transistor channel length. A. Leakage Model For the gates without ST, a leakage lookup table is created by simulating all the gates in the standard cell library under all can be possible input patterns. Thus the leakage current expressed as (1)

52% as shown in Table I. The error of linear approximation may be neglected in the FGSTI technique due to law of large numbers [25] with the growing circuit size. It will be disclosed in Section II-C that the inuence of this linear model error on the FGSTI technique will be diminished by the large difference between leakage current of a gate with or without ST. B. Delay Model The gate delay is inuenced by the ST insertion [15]. The of gate without ST is given by load dependent delay (3) , , , and are the load capacitance at the gate where output, the low threshold voltage, the velocity saturation index, and the proportionality constant, respectively. The propagation of gate with ST can be expressed as delay (4) is the where vious equations of the ST. is derived from the pre-

(5) is the current owing through ST in gate during the active mode, which can be expressed as given by [23]

where and are the leakage current and the probability of gate under input pattern . A linear model is proposed to represent leakage current based on HSPICE simulation results (2)

(6) Thus, the voltage drop be expressed as in gate due to ST insertion can

(7) Refer to (3) and (4), be given out as in gate due to ST insertion can also

is a constant and decided by the gate type. We aswhere sume all the input patterns have the same probability and estifor all the standard cells in the library. Conmate every sidering two standard cells: NOR2XL and NAND4XL in the TSMC 0.18- m standard cell library, the largest error is about

(8)

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LEAKAGE CURRENT COMPARISON OF STANDARD CELLS (fA).(V

= 1.8 V, V

TABLE II

= 500 mV FOR ST, V

= 300 mV FOR LOGIC CELLS)

C. Rationality of Our Two-Phase FGSTI From Table I, a linear leakage current model may have an error larger than 50% compared with the HSPICE simulation results. Referring to [23], the leakage current for a gate with ST is also modeled as a linear function from [26]

(9) is the -mobility, is the oxide capacitance, is the high threshold voltage, is the thermal is the subthreshold swing parameter. Notice that voltage, their model is also linear by assuming all parameters except are constants which are decided by process information and gate structure. Such a linear model will also endorse comparable error as our leakage current model. From Table I, the leakage current of a gate without ST is much larger than that of a gate with ST, so that the error of the linear model can be neglected in the FGSTI procedure. In Table II, we compare the leakage current of cells in the TSMC 0.18- m standard cell library under two different ST conditions: with ST or without ST. Because the leakage current of a gate with ST of a ST becomes larger with a larger ST, in Table II, is set to 16, which is the maximum ratio of ST in our FGSTI technique, in order to get the largest leakage current. As shown in Table II, the leakage current difference under different ST conditions is at least 238 , because of the large difference between the threshold voltage of ST and logic cells. Referring to (5) and (7), the delay difference is less than 20% of the original gate delay between delays of a gate with and without ST. However, the delay difference of a gate with different ST of a ST to 1 sizes is much larger; for example, setting will lead to about 140% additional delay comparing with the original gate without ST. Also, we can see from Table I, the leakage current difference of a gate with different ST size is less than 1% of the original gate leakage. Hence, the leakage current variation range due to the change of ST size can be neglected, because it is much smaller comparing with the leakage saving of changing a gates ST condition. Therefore, ST placement is not affected by ST sizing owing to the large gap between their effects on leakage saving. With technology scaling, the leakage current difference may be smaller under different ST conditions, but it will still be very ST and the stacking effect. large due to the use of high We can draw a conclusion that the leakage reduction depends on where to insert ST and the leakage difference of each gate where

Fig. 2. Leakage feedback gate [21].

under different ST conditions; while the area penalty is decided by the ST sizing procedure. We further assume that ST placement and sizing are independent in an FGSTI design. Therefore, a two-phase FGSTI technique is developed: rst, ST placement is performed to decide which gate will be assigned with ST in order to achieve most of the leakage saving; and ST sizing is used to reduce the area overhead along with further leakage current reduction. D. Leakage Feedback Gate During the ST placement phase, when the circuit slowdown is not large enough to assign ST to every gate, the FGSTI technique can cause a gate with ST to drive a gate without ST. This will lead to oating state at the output of the gate with ST and may cause large power dissipation due to the short circuit current in the gate without ST. In this subsection, the circuit scheme of LF gate is rst reviewed; and then a comparison is made between an LF gate and a normal ST gate to prove that a specilized LF gate can substitute for a normal ST gate. 1) Circuit Scheme: As mentioned in [23], the LF gate structure [21] shown in Fig. 2 should be used in order to avoid the oating states. The important characteristic of an LF gate is that depending on the state of the latest output, one but not both or ), is turned on by the feedback inverter, helper STs ( thus, the output state of the LF gate are set to 1 or 0. 2) Comparison With Normal ST Gate: During the standby STs and are turned off, only one mode, both high of the helper STs will be kept on to drive the output signal to the appropriate rail. On the other hand, when the circuit is active, STs and are turned on. One and only both high one of the helper STs will be turned on to accelerate the circuit

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First, we construct the object function which is the total leakage current as follows:

(10) where is a binary variable to represent gate s ST conmeans gate has ST inserted and dition, means gate is without ST. As ST size is not considered, we to obtain the minimum choose the largest ST size delay overhead. The leakage current of gate with ST is given by (11) The timing constraints of can be expressed as (12) (13) (14) and refer to the primary input and primary output where represents the arrival time of gate , gates of the circuit; is the overall circuit delay; represents the gate delay, which can be expressed as referring to (5) and (7)
Fig. 3. Delay comparison: an LF gate and a normal gate with ST.

speed, because the feedback inverter is sensitive to the change of the output signal. The signal propagation delay of an inverter with ST and an LF gate for an inverter are compared under same load capacitance and shown in Fig. 3. The sizes of helper STs are the same as those of the original sleep transistors. As we can see, the rise and fall slope of an LF gate is steeper than that of a normal ST gate. Therefore, we conclude that every gate with ST can be replaced with a carefully sized LF gate without affecting the circuit delay constraints. An LF gate will certainly bring two extra helper STs and a feedback inverter, hence it leads to area and dynamic power overhead. Since all the extra transistors can be high threshold transistors, the leakage overhead can be neglected. III. TWO-PHASE FGSTI TECHNIQUE In this section, our two-phase FGSTI technique is modeled using linear programming methods. First, we show how to place the ST as many as possible in order to reduce the total leakage; an extended MILP model considering LF gate is also proposed. Then an optimal sizing method is proposed to reduce the area overhead based on the ST placement information from the rst phase. At the end of this section, we briey review the simultaneous placement and sizing method [24] using MILP for comparison. A. Phase I: ST Placement 1) MILP Model: We propose a novel ST placement method that tries to maximize the leakage saving in the circuits through MILP model.

(15) is a constant, which is extracted from the techwhere , is also a nology library. As constant for each gate. assignment with ST placement phase is similar to dual xed high and low values, thereby it can also be solved by sensitive-based heuristic algorithms which are previously used assignment [9][11]. to deal with dual 2) MILP Model Considering LF Gate: As we mentioned before, when the circuit slowdown is not large enough to assign ST to each gate in the circuit, LF gates are used to avoid oating states. The LF gate number may exceed as much as 80% of the gates with ST when the effect of LF gate is not considered in FGSTI technique. The additional inverters in the LF gates will induce large area and dynamic power penalty. Thus, LF gate number is as important as the leakage reduction rate. In this subsection, an extended MILP model to simultaneously maximize the leakage saving in the circuits and minimize the LF gate number is proposed. First, the original object function for ST placement (10) is amended to consider the LF gate number

(16)

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Fig. 4. MILP model for multi-object ST placement.

Fig. 5. LP model for optimal ST sizing.

where is the total leakage current; is the LF gate is also a binary variable to repnumber in the circuit; means gate is resent gate s LF gate condition, means gate is not an LF gate; an LF gate and is a weight value that can be modied by the circuit designer. The performance and delay constraints are still the same with the MILP model without considering LF gate, because of the assumption in Section II-D, every gate with ST can be changed into a carefully sized LF gate without affecting the circuit delay constraints. and one A gate must be changed into LF gate if of its fan-out gate is a gate without ST. Thus the binary variable should satisfy the following constraint: (17) If is not zero, the LF gate is considered during the optimization; on the other hand, if is zero, the LF gate is not considered, can be deleted in the variable and constraints related to the model. To sum up, the general form of our MILP model for ST placement phase is shown in Fig. 4. B. Phase II: Optimal ST Sizing After ST condition for each gate is decided, the optimal ST sizing is derived using a linear programming model. The object function for optimal ST sizing is given as follows: (18) where is a binary value decided in the rst phase: ST is a continuous variable. Moreover, placement phase; from (7) and (8) can be derived as the expression for follows:

The timing constraints can also be expressed as (12)(14). of gate with ST can be rewrite The propagation delay using (5) and (7) as

(20) :[ , ], With a given boundary of : using we can easily derive the boundary of (20). Consequently, the general form of our LP model for ST sizing is shown in Fig. 5. C. Simultaneous ST Placement and Sizing In this subsection, the simultaneous ST placement and sizing method [24] is briey reviewed. The object function is very similar to ST placement as shown in (10)

(21) and are variables that decide where to put where ST and how to size ST, respectively. The timing constraints also for gate follow (12)(14). Referring to (15), gate delay can be derived as

(22) As we can see from (21) and (22), this problem is actually a nonlinear programming model. In [24], Taylor series expansion

(19)

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and piece wise linear approximation technique are used to get an MILP model. Some dummy variables are needed for linear approximation and corresponding linearization constraints are added in the MILP model for each dummy variable. Unfortunately, the model size becomes extremely large with the increasing gate number in the circuit. IV. HEURISTIC ALGORITHM FOR ST PLACEMENT In this section, a heuristic algorithm is introduced to solve the ST placement phase explained in Section III-A. One of the major bottlenecks of using MILP method is the unpredictable computation time when the circuit slowdown is not large enough to assign ST to every gate. Although the MILP model leads to optimal result, it can not be used in a real design cycle because of the unaffordable runtime cost for reiterations. A fast and accurate heuristic algorithm is needed to speed up the ST placement phase with a near optimal result. The LF gate number depends mainly on the ST placement information and the topology of the circuit; while the leakage reduction rate depends on ST gate number under the circuit performance constraints. It is time consuming to consider both ST gate number and LF gate number simultaneously during ST placement phase. In our heuristic algorithm, the DAG of the circuit is pruned to reduce the problem size in the rst step; then, in the second step, a greedy algorithm is used to assign ST as many as possible without affecting the performance constraints; nally, in the third step, the LF gate number is reduced according to different weight value: in (16). A. Step I: DAG Pruning The MILP model size for ST placement is decided by the gate number and the interconnect number in the circuit, that is, the vertex number and the edge number in the DAG. Hence, the DAG is rst pruned in our heuristic algorithm to reduce the problem size. This problem is actually how to nd the gates which must be assigned with ST in the circuit, so that the corresponding vertexes can be deleted from the DAG. Denition 1 (Signal Path): Signal path in a DAG from a vertex to a vertex is a sequence of vertexes, such that , and for . Denition 2 (Critical Path Delay): If ST is assigned to each gate, critical path delay of vertex , , in a DAG , is the longest path delay of all the signal paths which contain vertex . If ST is assigned to each gate, the leakage current of the circuit will exceed the reis minimized, and the overall delay . However, there may be some signal paths in quested delay the circuit still satisfy the performance constraints. Some gates in such signal paths can be deleted without affecting the timing constraints. That is to say, if in the circuit still do not when ST is assigned to each gate in the circuit. Gate exceed does not affect the circuit performance constraints whether gate is assigned with ST or not. can be derived directly according to Denition 2: 1) calculate delay of all the signal paths which contain vertex

and 2) the largest delay of these signal paths is picked up to . However, this direct computation is impractical, be because it is very complicated to nd all the signal paths which contain vertex . Lemma 1 (Subpaths of Largest Delay Paths are Largest Delay , let be Paths): Given a DAG to vertex and, for any the largest delay path from vertex and such that , let be the subpath of from vertex to vertex ; then is the largest delay path from vertex to vertex . Proof: Path can be decomposed into three parts: , thus, the path delay of can be denoted as . Assuming from to with , there is a path then there is a path with total delay , so that contradicts the assumption that is a largest delay path from vertex to vertex . Referring to Lemma 1, the critical path delay of gate : , essentially, consists of three parts

(23) is the maximum delay of the all where possible paths from primary inputs to ; is the maximum delay of all the possible paths from to priis mary outputs. As we all know, the arrival time of : dened as the worst case delay from primary inputs to vertex :

otherwise

(24)

is the delay of vertex shown in (15). where is chosen in path set Furthermore, in a DAG, once a path , we can obtain a corresponding path in from vertex to a reverse order by simply reversing the vertex sequence order. belong to path set from to vertex , and , . can be expressed as Therefore, (25) where is the arrival time of ; is the delay of gate with ST; is the reverse arrival time of vertex , and of a DAG in a reverse direction. The can be derived as arrival time and the reverse arrival time can be simply derived by Breadth-rst search (BFS) [27]. with timing informaTheorem 1: Given a DAG tion, if , vertex can be deleted in the DAG, which means that will not affect the performance constraints. Proof: Assuming will affect the performance constraints, contain that means the delay of at least one signal path gate is larger than (26)

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Fig. 6. DAG pruning algorithm.

Referring to (25)

(27) Thus, (26) and (27) are contradiction according the deduction above, this fact demonstrates the theorem. Apparently, the vertex set can be divided into two parts: and . if . Therefore, the original is pruned to in which DAG the ST condition of each vertex needs to be decided. The DAG Pruning Algorithms is shown in Fig. 6. B. Step II: ST Assignment After DAG pruning, we should nd a way to assign ST in as many as possible while minimizing the LF gate number. Every time is switched from 0 to 1 or from 0 to 1, the potential LF gate number should be recalculated, which will greatly slow down the optimization procedure. Thus, it is rather time consuming to optimize the LF gate number during ST assignment. One intuitional solution to tackle this difculty is to separate the optimization of ST gate number and LF gate number. The ST assignment procedure is carried out rst to as. sign as many ST as possible to The ST assignment problem is how to minimize the leakage while satisfying current through assigning ST to gates in the performance constraints. During our ST assignment algos for gates in are rst set to 1. The longest rithm, all delay path is then picked out; for some typical gates in this path are set back to zero in order to reduce the path delay. satisfy the This step iterates until all the signal paths in the performance constraints. A near optimal ST assignment solution can be derived from our algorithm. 0 mode Intuitionally, the LF gate is caused by the 1 (which means a gate without ST is driven by a gate with ST, ). If the set of gates 1 and 0 are corresponding value for with and the set of gates with only have one single boundary, the LF gate number will be denitely small. For example, on a certain path, the continuous pattern (four boundaries, 2 LF gates) or (two boundaries, 1 LF gate) cause (single more LF gates than the pattern boundary, without LF gate). Furthermore, there are two different conditions for single boundary. For example, there may be two patterns: and continuous ; both of them have only one boundary, however, the LF gate number is not the same. The former one will lead to no LF gate while the other one will cause one LF is placed gate. It can be inferred that, if a gate with
Fig. 7. ST assignment algorithm.

on the input node when there is only one boundary, there is no close to LF; it enlightens us to place the gate with each other and close to the input vertex to reduce the potential LF gates during the ST assignment step. In ST assignment, Forward Selection method is used to select gates from a longest signal path: assign gate with close to input vertex. Fig. 7 shows the ST assignment algorithm, the Forward Selection part can be easily changed into other selection method, such as: random selection (randomly select gates from the signal path). distribution graph can give us an intuitional The evaluation about the percentage of gates that can be optimized distribuin a given circuit. For example, in Fig. 8, tion graph for C432 shows that a high percentage of gates are , it can be inferred that the total gates with with large ST in the nal optimal result will be small; on the contrary, distribution graph for C880 shows that a small per, so that the total number centage of gates are with large of gates with ST in the nal optimal result will be large. These deductions are well supported by the simulation results shown in Section V. C. Step III: LF Reduction After we have the ST assignment information, an LF reduction algorithm is performed following the different weight value: in (16). First, we run a breadth-rst search in DAG , for each vertex with , if there is a fan-out from , is set to 1 and gate gate of vertex with is add into queue . We examine each LF gate in to nd out whether it is worth to change this LF gate back into a gate without ST. The weight value can be considered as a kind of leakage current overhead. Thus, (16) is rewritten as

(28) If one LF gate is changed back into gate without ST, the LF gate distribution in the area looking back from gate to should be re-examined. There may be some gates with ST should be changed back into gate without ST to avoid additional LF gates in this fan-shaped part of DAG which connected with

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Fig. 9. LF reduction algorithm.

Fig. 8.

(v ) distribution in C432 and C880.

standard cell library. A leakage current look up table of all the standard cells without ST is generated using HSPICE. in (2) for all the standard cells is In addition, every estimated using the HSPICE simulation results under different . The values of various transistor parameters have been 1.8 V, taken from the TSMC 0.18- m process library. 500 mV, 300 mV, and 200 A are set for all the gates in the circuit. The timing constraints are set up with a static timing analysis (STA) tool [10], and the MILP and LP models for ST placement phase and ST sizing phase are automatically generated. An LP solver named lp_solve1 is used to solve the models. The heuristic algorithm for ST placement phase is implemented using MATLAB. The simulations are conducted on a 1.83 GHZ CPU, 1.5 G memory computer. , corresponding to a least delay We assume variance of 6% if ST is assigned to all the gates in the circuit. We perform our two-phase FGSTI technique by rst using the for all the gates in the cirMILP model to get value of cuit and then solving the LP model to get the optimal based on the results of . The MILP model to simultaneously determine ST placement and sizing are also solved using the same LP solver under the same set of parameters in order to compare the results with our two-phase FGSTI technique. At last our heuristic algorithms for ST placement phase are performed to show the runtime merit over MILP method with an acceptable loss of accuracy. B. MILP Model for ST Placement Phase

gate . This operation leads to additional leakage current. Meanwhile, some of these gates with ST are LF gates; the change of LF gates back into gates without ST will also lead to leakage current saving. Therefore, we dene another weight value for each LF gate as (29) where is the vertex set in which should be changed back belongs into gate without ST due to the change of gate ; to , and all gates in are LF gates. Notice that, gate belongs to both and . and are derived by examining each gate during breadth-rst search from back . The LF Reduction Algorithm is shown in Fig. 9. to V. IMPLEMENTATION AND EXPERIMENTAL RESULTS A. Implementation All ISCAS85 benchmark circuit netlists are synthesized using Synopsys Design Compiler and a TSMC 0.18- m

1) ST Placement Without Considering LF Gate: For 0%, 3%, 5% circuit slowdown, a valid solution can not be derived from conventional xed slowdown method. Thus, the leakage current saving for 0%, 3%, 5% circuit slowdown are compared between our two-phase FGSTI technique and MILP method [24]. As shown in Table III, our two-phase FGSTI technique can achieve 78.91% leakage saving even if the circuit slowdown is not inuenced. When the circuit slow down is 3%, 5%, the leakage saving of our two-phase FGSTI technique is 92.55%, 97.97%, respectively. Because of less approximation in MILP model of ST placement phase, more leakage saving is achieved comparing with the simultaneous ST placement and sizing method [24]. The leakage saving is about on average 2% more than the MILP method. In Table IV, we show that our two-phase FGSTI technique for some circuits can achieve impressive runtime savings compared with the simultaneous ST placement and sizing method [24]. The runtime saving is largely caused by two reasons: one is the two-phase procedure of FGSTI technique and the other is less
1[Online].

Available: http://groups.yahoo.com/group/lp_solve/

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TABLE III LEAKAGE CURRENT COMPARISON BETWEEN TWO-PHASE FGSTI AND MILP METHOD [24] (pA)

TABLE IV RUNTIME COMPARISON BETWEEN TWO-PHASE FGSTI AND MILP METHOD [24] (TIME IN SECONDS)

TABLE V COMPARISON BETWEEN MULTI-OBJECTIVE ST PLACEMENT (M-STP) AND ST PLACEMENT WITHOUT CONSIDERING THE LF GATE (STP-WO)

variables and constraints used in MILP model for ST placement. For example, in circuit C432, there are only 271 constraints and 338 variables in our MILP model for ST placement; however, in [24], the MILP model has 2975 constraints and 1183 variables. Although MILP problems need a long time to solve, some of the benchmark, especially the small ones, at least 10 runtime saving can be achieved using our two-phase FGSTI method. We only list the results of four benchmarks, because other benchmarks take hours to get the optimal results. The stopping time criteria is set to four hours for larger circuits. 2) ST Placement Considering LF Gate: As we mentioned corresponds to a delay variance of 6% if before, ST is assigned to all the gates in the circuit [24]. Thus, when the circuit slowdown varies in the range of 6% circuit original delay, ST cannot be assigned to every gate in the circuit. The LF gate should be used when a gate with ST is driving a gate without ST. The results of our multi-object ST placement (M-STP) and the ST placement without considering the LF gate (STP-WO) are compared in Table V. The weight value is assumed to be 100.

In Table V, if the LF gate is not considered during ST placement, on average 37.1% of the gates with ST should be changed into leakage feed back structure if there is no circuit slowdown. When circuit slowdown is 3% and 5%, on average 19.8% and 9.9% of the gate with ST should be changed into LF gate, respectively. When the circuit slowdown is 0%, some of the benchmarks, such as C499, C1355, need to change 80.4% and 66.4% of normal ST gates into LF gates. This will lead to a large area increasing due to large number of high feedback inverters and help STs. As the LF gate is considered during the multi-object ST placement, the LF gate number is about 9.3%, 3.3%, and 1.1% of the total gates with ST when the circuit slowdown is 0%, 3%, and 5%, respectively. Meanwhile, the difference of leakage reduction rate is only 7.9%, 4.3%, and 2.8%. For the two typical benchmarks mentioned previously: C499 and C1355, the LF gate becomes 35.2% and 16.1% of the gates with ST, respectively, when the circuit slowdown is 0%. Furthermore, the weight value can be used to control the tradeoff between leakage reduction rate and the LF gate number.

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TABLE VI DIFFERENT WEIGHT VALUE FOR C880 (pA)

TABLE VII RESULTS OF LEAKAGE AND LF GATE USING HEURISTIC ALGORITHM DURING ST PLACEMENT PHASE

Four different weight values: 10, 50, 100, 200 are used in our MILP model for C880. Table VI shows the leakage current and LF number under different weight value. As in Table VI, when the circuit slowdown is 0%, a larger weight value should be chosen to reduce the LF gate number; when the circuit slowdown is becoming larger, the original LF gate number without any optimization reduces to a low level, thus a smaller weight value can be used to get a larger leakage reduction rate with an acceptable LF gate number. The runtime for solving the previous MILP model of ST placement is not stable, it will be time consuming for many circuits; hence heuristic algorithms are needed to get near optimal results with a very fast speed. However, the heuristic may lead to local optimal and can not guarantee the optimality of the result; thus, the results of MILP models can be used as a reference. C. Heuristic Algorithm for ST Placement Phase Our three-step heuristic algorithm is developed to accelerate the computation speed within acceptable loss of accuracy. As shown in Table VII, after Step I, DAG pruning, when the circuit slowdown is 0%, 3%, and 5%, about 60.1%, 65.45%, and 72.3% of total gates are deleted from the original circuits, thus, problem size is greatly reduced. in Table VII represents the gate . The second step ST Assignment can be considnumber in ered as the MILP method without considering LF gate and is explained in Section III-A1. Our second step can achieve similar leakage reduction rate compared with the results of two-step MILP method shown in Table V. For C499 and C1355, our algorithm leads to even smaller leakage, especially when the circuit slowdown is 0%; meanwhile the average difference of leakage reduction rate for other circuits is about 4% of original leakage current. The MILP models for C499 and C1355 may not converge well using the MILP solver. Furthermore, because potential LF reduction is considered by using Forward Selection during ST Assignment Algorithm, the LF gate number is much less than the MILP method in Table V. When the circuit slowdown is 0%, 3%,

and 5%, the LF gate is only 11.6%, 6.7%, and 2.4% of total gate with ST. In Step III, the weight value is also assumed to be 100. The LF gate number is reduced to below 3% of the total gate with ST while the difference of leakage reduction rate is only 13.2%, 8.3%, and 3.5% when the circuit slowdown is 0%, 3%, and 5%, respectively. As shown in Table VIII, the computation time of our heuristic algorithm is linear with the circuit size. As the MILP method is very time-consuming, our heuristic algorithm appears controllable and promising for a larger circuit design. Finally, as discussed in Section IV-B, the leakage reduction distribution, which rate of each circuit relies on its gives us an intuitional evaluation about the percentage of gates that can be optimized. For C432, because of a high percentage of , only 50% leakage current can be gates are with large reduced when the circuit slowdown is 0%; on the other hand, C880 shows that a small percentage of gates are with large , so that the leakage reduction rate can achieve 92% which is very high when the circuit slowdown is also 0%. Theredistribution shows the potential of leakage refore, the duction rate in a certain circuit to the designers. D. Linear Programming Model for Optimal ST Sizing When the circuit slowdown is less than 6%, ST sizing phase is performed using the ST information of each gate decided in the ST placement phase. The optimal ST sizing method is used to get all the leakage current values in Tables IIIVII. When the circuit slowdown is larger than 6%, ST can be assigned to all the gates in the circuits, the two-phase procedure of FGSTI technique is reduced into one phase: ST sizing. The LP model for ST sizing can be solved to get the same result as optimal sizing method in [25]. We compare the area penalty with the xed slowdown method and the MILP method in Table IX. With 7% circuit slowdown, our ST sizing LP model causes 75.48% ST area saving compared to xed slowdown method and the result

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TABLE VIII RUNTIME OF HEURISTIC ALGORITHM FOR ST PLACEMENT PHASE (TIME IN SECONDS)

TABLE IX ST SIZING RESULTS COMPARED WITH MILP AND FIXED SLOWDOWN METHOD

is almost the same with MILP method. In Table IX, ST area is , since calculated using (18), just summing up all the the transistor channel length of ST is a constant. VI. CONCLUSION In this paper, we present a novel two-phase FGSTI technique to reduce the leakage current. Simple leakage current and delay models for our two-phase FGSTI technique are proposed and analyzed to prove the rationality of our method. ST placement and sizing are modeled using MILP and LP models respectively. The LF gate number is reduced during the ST placement phase. Both LP-solver and heuristic algorithms are used to solve the MILP model. Our experimental results show that our two-phase FGSTI technique leads to 2% more leakage saving and at least 10 runtime saving compared with simultaneous ST placement and sizing method using MILP. The LF gate number can be reduced and controlled using our multi-object model when the circuit slowdown is below 6%. Our heuristic algorithm is much faster and more stable than the MILP method. When the circuit slowdown is larger than 6%, the two-phase FGSTI can achieve 75.48% ST area saving comparing with xed slowdown method. In conclusion, two-phase FGSTI technique is reasonable from

our results. For the future work, the detailed comparison between the FGSTI and BBSTI techniques should be carefully examined in the physical level, such as place and routing penalty. REFERENCES
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Ku He received the B.S. degree in electronic engineering and the M.E. degree in electronic engineering from Tsinghua University, Beijing, China, in 2004 and 2007, respectively. He is currently pursuing the Ph.D. degree in computer engineering from the University of Texas, Austin. His research interests include statistical and robust circuit optimization.

Rong Luo (M05) received the double B.S. degree in engineering physical and electronic engineering and the Ph.D. degree from Tsinghua University, Beijing, China, in 1992 and 1997, respectively. Currently, she is an Associate Professor with the Department of Electronic Engineering, Tsinghua University. Her current research work is mainly on SoC design technology, VLSI design, and embedded system design technology.

Hui Wang received the B.S. degree in radio electronics from Tsinghua University, Beijing, China, in 1970. She has been with Tsinghua University since 1970, where she served as Vice Director of the Department of Electronics Engineering, from 1996 to 1999, Deputy Dean of Academic Affairs Ofce, from 1999 to 2005, and has been the Vice Dean of School of Information Science and Technology, since 2005. She was a visiting Scholar at Stanford University, Stanford, CA, from 1991 to 1992. Dr. Wang was a recipient of awards including the Science and Technology Progress Award (I) from Chinese Ministry of Electronics, the National Science and Technology Progress Award (III) from National Science and Technology Communication and Teaching Achievement Award (I) from Chinese Ministry of Education. She participated in many projects from the Natural Science Foundation of China (NSFC), 863 program and some key programs of fundamental research. received some national awards,

Yu Wang (M07) received the B.S. and Ph.D. degrees with honors in electronics engineering from Tsinghua University, Beijing, China, in 2002 and 2007, respectively. He is currently with the Electrical Engineering Department, Tsinghua University. His research mainly focuses on electronic design automation area, including fast circuit analysis, low power circuit design methodology, reliability-aware circuit design methodology, application specic FPGA design, and MPSOC design methodology. He has authored or coauthored over 10 journal and conference papers in this area and holds 1 China patent.

Huazhong Yang (M97SM00) received the B.S. degree in microelectronics and the M.S. and Ph.D. degrees in circuits and systems from Tsinghua University, Beijing, China, in 1989, 1993, and 1998, respectively. Since 1993, he has been with the Department of Electronic Engineering, Tsinghua University, where he has been a Full Professor since 1998. His research interests include CMOS radio-frequency integrated circuits, VLSI system structure for digital communications and media processing, low-voltage and lowpower integrated circuits, and computer-aided design methodologies for system integration. He has authored or coauthored 6 books and more than 180 journal and conference papers in this area and holds 9 China patents. He is also a coeditor of the research monograph High-speed Optical Transceivers-Integrated Circuits Designs and Optical Devices Techniques (World Scientic, 2006). Dr. Yang was a recipient of the fund for Distinguished Young Scholars from NSFC in 2000, the outstanding researcher award of the National Keystone Basic Research Program of China in 2004, and the Special Government Allowance from the State Council of China in 2006.served as a TPC member of the AsiaPacic Conference on Circuits and Systems, the International Conference on Communications, Circuits and Systems, and the Asia and South Pacic Design Automation Conference. He is an Associate Editor of the International Journal of Electronics.

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