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3rd Semester DLD LAB 3

The document is a lab report that describes designing adders and subtractors using logic gates. It discusses half adders, full adders, half subtractors and full subtractors. It then details tasks to design and simulate a 4-bit adder, 8-bit adder, and 16-bit adder/subtractor using logic gates in Proteus Design Suite software. The report concludes that the circuits demonstrate how to physically add binary numbers using logic gates and integrated circuits.

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210276
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29 views

3rd Semester DLD LAB 3

The document is a lab report that describes designing adders and subtractors using logic gates. It discusses half adders, full adders, half subtractors and full subtractors. It then details tasks to design and simulate a 4-bit adder, 8-bit adder, and 16-bit adder/subtractor using logic gates in Proteus Design Suite software. The report concludes that the circuits demonstrate how to physically add binary numbers using logic gates and integrated circuits.

Uploaded by

210276
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of Electrical and Computer Engineering

Air University Islamabad


3rd Semester
Digital Logic Design
Lab Report#2
Realization Of Logic Gates As NAND Gate
Osama Anees Mirza Muhammad Muneeb Khan Muhammad Ali Raza
210286 210276 210309
25 September 2022

1
Contents
1 Objectives 3

2 Apparatus 3

3 Theory 3

4 Task 4
4.1 Procedure: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.2 4 bit Adder: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.3 Table: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5 Logic Gate Implementation of 8 bit 5

6 Conclusion 7

2
1 Objectives
• To experimentally verify the operation of basic adders & subtractors using logic gates
• To design various configurations of adders using logic gates.

2 Apparatus
• Proteus Design Suite
• Breadboard
• Connecting wires
• ICs as required

3 Theory
In binary number system we cannot add or subtract numbers as we do in base 10 numbers. We have
different physical methods to do so.
1. Half-Adder: A half-adder is a combinational logic circuit that adds the values of the two
data bits A and B. Two output bits, the sum bit (S), and the carry bit(C), are produced as a
result of addition. The following Boolean operations describe the half-adder:
Sum = A ⊕ B
Carry = A · B

2. Full-Adder: The half-adder ignores the carry bit from the preceding step. The carry-in bit
is the carry bit from the preceding step. A full-adder is a combinational logic circuit that
combines two data bits, A and B, and a carry-in bit, Cin. The following Boolean functions
define the full-adder:
Sum = (x ⊕ y) ⊕ Cin
Carry = xy + Cin(x ⊕ y)

3. Half Subtractor: A difference bit D and a borrow out bit B-out are produced when a single-
bit binary value B is subtracted from another binary value A (i.c. A-B). Half subtraction is
the name of both the operation and the circuit used to carry it out. The following Boolean
operations describe the half Subtractor:
Sum = A ⊕ B
Carry = A′ B

4. Full Subtractor: Subtracting two binary values of a single bit. B. Cin creates a difference bit
D and a borrow out Br bit from a single-bit value A. It is referred to as complete subtraction.
The following Boolean operations describe the full-subtracter:
Dif f erence = (x ⊕ y) ⊕ Cin
Br = A′ B + A′ (Cin) + B(Cin)

3
4 Task
Design 8-bit and 16-bit parallel adder & subtractor and verify results on proteus.

4.1 Procedure:
• Use the knowledge from the previous tasks which were making simple 4 bit adders through
Logic gates.
• This time use an ICs instead of separate Logic Gates.
• Simulate the circuit in Proteus Design Suite.

• Verify the results by converting the numbers in to base 10 form.

4.2 4 bit Adder:

Figure 1: Proteus Simulation Of 4 bit adder

4
4.3 Table:

5 Logic Gate Implementation of 8 bit

Figure 2: Proteus Simulation Of 4 bit adder

5
6
6 Conclusion
We learned how to physically ,through circuits, add binary numbers and read the output. We can
add 4 bit numbers and get an answer of maximum 15.

These circuits can be implemented through logic gates as well as an IC which we used to generate
4 bit adder. Our group made 8 bit adder using Logic gates. This gave us a basic explanation of how
modern day circuits work.

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