Semiconductor Memory

Introduction
 There are two types of memories that are used in digital
systems:
 Random-access memory (RAM): perform both the write and
read operations.
 Read-only memory (ROM): perform only the read operation.

 The read-only memory is a programmable logic device.

Other such units are the programmable logic array (PLA),
the programmable array logic (PAL), and the field-
programmable gate array (FPGA).

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 Random-Access Memory (RAM)
 A memory unit stores binary information in groups of bits
called words.
1 byte = 8 bits
1 word = 2 bytes (or more)

 The communication between a memory and its environment is

achieved through data input and output lines, address selection
lines, and control lines that specify the direction of transfer.

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  Each word in memory is
assigned an identification
number, called an address,
starting from 0 up to 2k-1,
where k is the number of
address lines.

 The number of words in a

memory with one of the letters
K=210, M=220, or G=230.
64K = 216 2M = 221 4G = 232.

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  Transferring a new word to be stored into memory:
 Apply the binary address of the desired word to the address
lines.
 Apply the data bits that must be stored in memory to the data
input lines.
 Activate the write input.

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  Transferring a stored word out of memory:
 Apply the binary address of the desired word to the address lines.
 Activate the read input.
 Commercial memory sometimes provide the two control
inputs for reading and writing in a somewhat different
configuration.

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 Types of memories
 In a random-access memory, the access time is always the same
regardless of the particular location of the word.
 In a sequential-access memory, the time it takes to access a word
depends on the position of the word with respect to the reading
head position; therefore, the access time is variable.

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 Static RAM (SRAM)
 SRAM consists essentially of internal latches that store the binary
information.
 The stored information remains valid as long as power is applied
to the unit.
 SRAM is easier to use and has shorter read and write cycles.
 Low density, low capacity, high cost, high speed, high power
consumption.

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 Dynamic RAM (DRAM)
 DRAM stores the binary information in the form of electric
charges on capacitors.
 The capacitors are provided inside the chip by MOS transistors.
 The capacitors tends to discharge with time and must be
periodically recharged by refreshing the dynamic memory.
 DRAM offers reduced power consumption and larger storage
capacity in a single memory chip.
 High density, high capacity, low cost, low speed, low power
consumption.

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 Types of memories
 Memory units that lose stored information when power is turned
off are said to be volatile.
 Both static and dynamic, are of this category since the binary
cells need external power to maintain the stored information.
 Nonvolatile memory, such as magnetic disk, ROM, retains its
stored information after removal of power.

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 Memory decoding
 The equivalent logic of a binary cell that stores one bit of
information is shown below.
Read/Write = 0, select = 1, input data to S-R latch
Read/Write = 1, select = 1, output data from S-R latch

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 4x4 RAM
 There is a need for decoding circuits to select the memory word
specified by the input address.
 During the read operation, the four bits of the selected word go
through OR gates to the output terminals.
 During the write operation, the data available in the input lines are
transferred into the four binary cells of the selected word.
 A memory with 2 k words of n bits per word requires k address lines
that go into kx2k decoder.

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 4x4 RAM

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 Coincident decoding
 A decoder with k inputs and 2k
outputs requires 2k AND gates
with k inputs per gate.
 Two decoding in a two-
dimensional selection scheme
can reduce the number of
inputs per gate.
 1K-word memory, instead of
using a single 10x1024 decoder,
we use two 5x32 decoders.

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 Address multiplexing
 DRAMs typically have four times the density of SRAM.
 The cost per bit of DRAM storage is three to four times less than
SRAM. Another factor is lower power requirement.
 Address multiplexing will reduce the number of pins in the IC
package.
 In a two-dimensional array, the address is applied in two parts at
different times, with the row address first and the column address
second. Since the same set of pins is used for both parts of the
address, so can decrease the size of package significantly.

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 Address multiplexing for 64K DRAM
 After a time equivalent to the
settling time of the row
selection, RAS goes back to
the 1 level.
 Registers are used to store the
addresses of the row and
column.
 CAS must go back to the 1
level before initializing
another memory operation.

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 Read-Only Memory (ROM)
 A block diagram of a ROM is shown below. It consists of k address
inputs and n data outputs.
 The number of words in a ROM is determined from the fact that k
address input lines are needed to specify 2k words.

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 Construction of ROM
 Each output of the decoder represents a memory address.
 Each OR gate must be considered as having 32 inputs.
 A 2k x n ROM will have an internal k x 2k decoder and n OR gates.

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 Truth table of ROM
 A programmable connection between two lines is logically
equivalent to a switch that can be altered to either be close or
open.
 Intersection between two lines is sometimes called a cross-point.

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 Programming the ROM
 In Table, 0: no connection; 1: connection
Address 3 = 10110010 is permanent storage using fuse link

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 Combinational circuit implementation
 The internal operation of a ROM can be interpreted in two ways:
First, a memory unit that contains a fixed pattern of stored words.
Second, implements a combinational circuit.
 Previous figure may be considered as a combinational circuit with
eight outputs, each being a function of the five input variables.

A7(I4, I3, I2, I1, I0) =

Sum of minterms

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 Example
 Design a combinational circuit using a ROM. The circuit accepts a
3-bit number and generates an output binary number equal to the
square of the input number.
Derive truth table first

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 Example

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 Types of ROMs
 The required paths in a ROM may be programmed in four
different ways.
1. Mask programming: fabrication process
2. Read-only memory or PROM: blown fuse/fuse intact
3. Erasable PROM or EPROM: placed under a special ultraviolet
light for a given period of time will erase the pattern in
ROM.
4. Electrically-erasable PROM(EEPROM): erased with an
electrical signal instead of ultraviolet light.

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 Combinational PLDs
 A combinational PLD is an integrated circuit with
programmable gates divided into an AND array and an OR
array to provide an ANDOR sum of product mplementation.
 PROM: fixed AND array constructed as a decoder and
programmable OR array.
 PAL: programmable AND array and fixed OR array.
 PLA: both the AND and OR arrays can be programmed.

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 Combinational PLDs

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 •
Programmable Logic Array (PLA)
 The decoder in PROM example can be replaced by an array
of AND gates that can be programmed to generate any
product term of the input variables.
 The product terms are then connected to OR gates to
provide the sum of products for the required Boolean
functions.
 The output is inverted when the XOR input is connected to
1 (since x 1 = x’). The output doesn’t change and connect
to 0 (since x 0 = x).

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 •
Programmable Logic Array (PLA)
 F1 = AB’+AC+A’BC’
F2 = (AC+BC)’

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 •
PLA Programming Table
 First: list the product terms numerically
 Second: specifiy the required paths between inputs
and AND gates
 Third: specify the paths between the AND and OR gates
 For each output variable, we may have a T(ture) or
C(complement) for programming the XOR gate

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 •
Programmable Array Logic (PAL)
 The PAL is a programmable logic device with a fixed OR
array and a programmable AND array.

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 Programmable Array Logic (PAL)
 When designing with a PAL, the Boolean functions must be
simplified to fit into each section.
 Unlike the PLA, a product term cannot be shared among two
or more OR gates. Therefore, each function can be simplified
by itself without regard to common product terms.
 The output terminals are sometimes driven by three-state
buffers or inverters.

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 PAL Example
 w(A, B, C, D) = ∑(2, 12, 13)
x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = ∑(1, 2, 8, 12, 13)

 Simplifying the four functions as following Boolean

functions:
w = ABC’ + A’B’CD’
x = A + BCD
y = A’B + CD + B’D’
z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ +
A’B’C’D

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 PAL Table
 z has four product terms, and we can replace by w with two
product terms, this will reduce the number of terms for z
from four to three.

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 PAL Implementation

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 Fuse map for example

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 Reference
 , “Digital Circuits,” NPTEL:

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