YASWANTH B

1/20/24

I2C COMMUNICATION PROTOCOL

Overview
I2C is a two-wire serial communication protocol using a serial data line (SDA) and a serial clock line
(SCL). The protocol supports multiple target devices on a communication bus and can also support
multiple controllers that send and receive commands and data. Communication is sent in byte packets
with a unique address for each target device.

Block Diagram

SDA (Serial Data)

MASTER SLAVE
SCL (Serial Clock)

I2C Speed Modes

I2C has several speed modes starting with the standard mode (Sm), which is a serial protocol that
operates up to 100 kilobits per second (kbps). This mode is followed by the Fast-mode (Fm) which tops
out at 400 kilobits per second. Fast mode can be used by the controller if the bus capacitance and drive
capability allow for faster speed. Both of these protocols are widely supported. The Fast-mode Plus
(Fm+) mode allows for communication as high as 1 megabit per second (Mbps). To achieve this speed,
drivers in the devices require extra strength to comply with faster rise and fall times. These three modes
are relatively similar, using a communication structure that is the same. However, all have different
timing specifications for each of the modes and hardware implementation of the I2C in the devices is
different to accommodate the different speeds. I2C also has two other modes for higher data rates. High-
speed mode (Hs-mode) has a data rate of 3.4 megabits per second. In this mode, the controller device
must first use a controller code to allow for high-speed data transfer. This enables high-speed mode in
the target device. This mode can also require an active pullup to drive the communication lines at a
higher data rate. Ultra-Fast mode (UFm) is the fastest mode of operation and transfers data up to 5Mbps.
This mode is write-only and omits some I2C features in the communication protocol

1|Page
 YASWANTH B
1/20/24

I2C Protocol
I2C START and STOP I2C communication is initiated from the controller device with an I2C START
condition. If the bus is open, an I2C controller claims the bus for communication by sending an I2C
START. To do this, the controller device first pulls the SDA low and then pulls the SCL low. This
sequence indicates that the controller device is claiming the I2C bus for communication, forcing other
controller devices on the bus to hold their communication. When the controller device has completed
communication, the SCL releases high and then the SDA releases high. This indicates an I2C STOP
condition. This releases the bus to allow other controllers to communicate or to allow for the same
controller to communicate with another device.

I2C Communication Frames

The I2C protocol is broken up into frames. Communication begins with the controller device sending
an address frame after a START. The address frame is followed by one or more data frames each
consisting of one byte. Each frame also has an acknowledge bit to alert the controller that the target
device or the controller device has received communication.

At the beginning of the address frame, the controller device initiates a START condition. The controller
device first pulls SDA low and then pulls SCL low for the START. This allows the controller device to
claim the bus without contention from other controller devices on the bus. Each I2C target device has
an associated I2C address. When beginning communications with a particular target device the
controller uses the target device address to send or receive data in the following I2C frames. The I2C
address consists of 7 bits and devices on the I2C bus, each having a unique address on the bus. A 7-bit
address implies 27 (or 128) unique addresses. However, there are several reserved I2C addresses which
limits the number of possible devices. Reserved addresses. The address is sent with the SDA as the data
and the SCL as the serial clock. With this information, you can read through the I2C communication of

2|Page
 YASWANTH B
1/20/24

a device and understand what is being sent back and forth between the controller device and the target
device. The 8th bit of this frame following the address, is the read-write (R/W) bit. If this bit is 1, the
controller is asking to read data from the target device. If this bit is 0, the controller asks to write data
to the target device. After any communication byte, an extra 9th bit is used to verify the communication
was successful. At the end of the address byte communication, the target device pulls down the SDA
during the SCL pulse to indicate to the controller that the address was received. This is known as an
acknowledge (ACK) bit. If this bit is high, then no target device received the address and the
communication was unsuccessful. If the bit is high, this is known as a NACK and there was no ACK.
The address frame is followed by one or more data frames. These frames are sent one byte at a time.
After each data byte is transferred, there is another ACK. If the data byte is a write to the device, then
the target device pulls the SDA low to ACK the transfer. If the data byte is a read from the device, the
controller pulls the SDA low to acknowledge the data has been received. The ACK is a useful debugging
tool. The absence of this bit can indicate that the target peripheral did not receive the proper I2C address
for communication, or that the controller peripheral did not receive the expected data. After the
communication is completed, the controller issues an I2C STOP condition. SCL is first released and
then SDA is released. The controller uses the STOP to indicate that the communication is completed
and the I2C bus is released. This is the basic protocol for any I2C communication between the controller
device and the target device. Communication can consist of more than one byte of data. In some cases
where a target device has multiple data and configuration registers, a read from a device can begin with
a write to the device to indicate which register is to be read. The following sections show examples of
how to read from and write to different data converter devices.

Example of START and STOP Condition

Example of Single Byte Data Transfer

3|Page
 YASWANTH B
1/20/24

Writing to a Slave on The I2C Bus

To write on the I2C bus, the master will send a start condition on the bus with the slave's address, as
well as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge
bit, the master will then send the register address of the register it wishes to write to. The slave will
acknowledge again, letting the master know it is ready. After this, the master will start sending the
register data to the slave, until the master has sent all the data it needs to (sometimes this is only a single
byte), and the master will terminate the transmission with a STOP condition.

Example I 2C Write to Slave Device's Register

Reading From a Slave on The I2C Bus

Reading from a slave is very similar to writing but with some extra steps. To read from a slave, the
master must first instruct the slave which registers it wishes to read from. This is done by the master
starting off the transmission similarly as the write, by sending the address with the R/W bit equal to 0
(signifying a write), followed by the register address it wishes to read from. Once the slave
acknowledges this register address, the master will send a START condition again, followed by the
slave address with the R/W bit set to 1 (signifying a read). This time, the slave will acknowledge the
read request, and the master releases the SDA bus, but will continue supplying the clock to the slave.
During this part of the transaction, the master will become the master receiver, and the slave will
become the slave transmitter. The master will continue sending out the clock pulses but will release
the SDA line so that the slave can transmit data. At the end of every byte of data, the master will send
an ACK to the slave, letting the slave know that it is ready for more data. Once the master has
received the number of bytes it is expecting, it will send a NACK, signalling to the slave to halt
communications and release the bus. The master will follow this up with a STOP condition.

Example I2C Read from Slave Device's Register

4|Page