TS5A23157-Q1

SCDS252B – JULY 2007 – REVISED JUNE 2021

TS5A23157-Q1 Dual 15-Ω SPDT Analog Switch

1 Features 3 Description
• Qualified for automotive applications The TS5A23157-Q1 is a dual, single-pole, double-
• AEC-Q100 qualified with the following results: throw (SPDT) analog switch designed to operate from
– Device temperature grade 1: –40°C to 125°C 1.65 V to 5.5 V. This device can handle both digital
– Device HBM ESD classification level H2 and analog signals. The device can transmit signals
– Device CDM ESD classification level C4B up to 5.5 V (peak) in either direction.
• Functional safety-capable For the most current package and ordering
– Documentation available to aid functional safety information, see the Package Option Addendum at
system design the end of this document, or see the TI Web site at
• Customer-specific configuration control can be www.ti.com.
supported along with major-change approval
• Specified break-before-make switching Table 3-1. Device Information(1)
• Low ON-state resistance (15 Ω) PART NUMBER PACKAGE BODY SIZE (NOM)
• Control inputs are 5-V tolerant TS5A23157-Q1 VSSOP (10) 3.00 mm × 3.00 mm
• Low charge injection
(1) For all available packages, see the package option
• Excellent ON-resistance matching addendum at the end of the data sheet.
• Low total harmonic distortion
• 1.8-V to 5.5-V single-supply operation
IN1 1 10 COM1
2 Applications NO1 2 9 NC1
• Sample-and-hold circuits GND 3 8 V+
• Battery-powered equipment NO2 4 7 NC2
• Audio and video signal routing
• Communication circuits IN2 5 6 COM2

TS5A23157-Q1 Functional Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 11 Application and Implementation................................ 18
2 Applications..................................................................... 1 11.1 Application Information............................................18
3 Description.......................................................................1 11.2 Typical Application.................................................. 18
4 Revision History.............................................................. 2 11.3 Design Requirements..............................................18
5 Pin Configurations and Functions.................................3 11.4 Detailed Design Procedure..................................... 19
6 Specifications.................................................................. 4 11.5 Application Performance Plots................................ 19
6.1 Absolute Maximum Ratings........................................ 4 12 Power Supply Recommendations..............................19
6.2 Electrical Characteristics for 5-V Supply.....................5 13 Layout...........................................................................20
6.3 Electrical Characteristics for 3.3-V Supply..................7 13.1 Layout Guidelines................................................... 20
6.4 Electrical Characteristics for 2.5-V Supply..................8 13.2 Layout Example...................................................... 21
6.5 Electrical Characteristics for 1.8-V Supply..................9 14 Device and Documentation Support..........................22
6.6 Typical Characteristics.............................................. 10 14.1 Receiving Notification of Documentation Updates..22
7 Parameter Description.................................................. 11 14.2 Support Resources................................................. 22
8 Parameter Measurement Information.......................... 12 14.3 Trademarks............................................................. 22
9 Function and Summary of Characteristics................. 16 14.4 Electrostatic Discharge Caution..............................22
10 Detailed Description....................................................17 14.5 Glossary..................................................................22
10.1 Overview................................................................. 17 15 Mechanical, Packaging, and Orderable
10.2 Functional Block Diagram....................................... 17 Information.................................................................... 22
10.3 Feature Description.................................................17 15.1 Ordering Information............................................... 22
10.4 Device Functional Modes........................................17

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (February 2013) to Revision B (June 2021) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added functional safety-capable information to the Features section................................................................ 1

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5 Pin Configurations and Functions

IN1 1 10 COM1

NO1 2 9 NC1

GND 3 8 V+

NO2 4 7 NC2

IN2 5 6 COM2

Not to scale

Figure 5-1. DGS VSSOP (16) Top View

Table 5-1. Pin Functions

PIN
Type DESCRIPTION
NAME NO.
COM1 10 I/O Common
COM2 6 I/O Common
GND 3 P Ground
IN1 1 I Digital control to connect COM to NO or NC
IN2 5 I Digital control to connect COM to NO or NC
NC1 9 I/O Normally closed
NC2 7 I/O Normally closed
NO1 2 I/O Normally open
NO2 4 I/O Normally open
V+ 8 P Power supply

1. I = input, O = output, I/O = input and output, P = power.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V+ Supply voltage range(1) –0.5 6.5 V
VNC
VNO Analog voltage range(1) (2) (3) –0.5 V+ + 0.5 V
VCOM
II/OK Analog port diode current VNC, VNO, VCOM < 0 or VNC, VNO, VCOM > V+ ±50 mA
INC
INO On-state switch current VNC, VNO, VCOM = 0 to V+ ±50 mA
ICOM
VIN Digital input voltage range(1) (2) –0.5 6.5 V
IIK Digital input clamp current VIN < 0 –50 mA
Continuous current through V+ or GND ±100 mA
θJA Package thermal impedance(4) 165.36 °C/W
Tstg Storage temperature range –65 150 °C
Human-body model H2 2 kV
ESD Electrostatic discharge rating
Charged-device model C4B 750 V

(1) All voltages are with respect to ground, unless otherwise specified.
(2) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

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6.2 Electrical Characteristics for 5-V Supply

V+ = 4.5 V to 5.5 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS TA V+ MIN TYP(1) MAX UNIT
Analog Switch
VCOM,
Analog signal range 0 V+ V
VNO, VNC
0 ≤ VNO or VNC ≤ V+, Switch ON,
ON-state resistance ron Full 4.5 V 15 Ω
ICOM = –30 mA, See Figure 8-1
ON-state resistance
VNO or VNC = 3.15 V, Switch ON,
match between Δron 25°C 4.5 V 0.15 Ω
ICOM = –30 mA, See Figure 8-1
channels
ON-state resistance 0 ≤ VNO or VNC ≤ V+, Switch ON,
ron(flat) 25°C 4.5 V 4 Ω
flatness ICOM = –30 mA, See Figure 8-1

NC, NO INC(OFF), VNC or VNO = 0 to V+, Switch OFF, 25°C –1 0.05 1

5.5 V μA
OFF leakage current INO(OFF) VCOM = 0 to V+, See Figure 8-2 Full –1 1

NC, NO INC(ON), VNC or VNO = 0 to V+, Switch ON, 25°C –0.1 0.1
5.5 V μA
ON leakage current INO(ON) VCOM = Open, See Figure 8-2 Full –1 1

COM VNC or VNO = Open, Switch ON, 25°C –0.1 0.1

ICOM(ON) 5.5 V μA
ON leakage current VCOM = 0 to V+, See Figure 8-2 Full –1 1
Digital Inputs (IN1, IN2)(2)
Input logic high VIH Full V+ × 0.7 V
Input logic low VIL Full V+ × 0.3 V

Input leakage 25°C –1 0.05 1

IIH, IIL VIN = 5.5 V or 0 5.5 V μA
current Full –1 1

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6.2 Electrical Characteristics for 5-V Supply (continued)

V+ = 4.5 V to 5.5 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS TA V+ MIN TYP(1) MAX UNIT
Dynamic
VNC = GND and VNO = V+, RL = 500 Ω, 4.5 V
Turnon time tON or CL = 50 pF, Full to 1.2 8.7 ns
VNC = V+ and VNO = GND, See Figure 8-4 5.5 V
VNC = GND and VNO = V+, RL = 500 Ω, 4.5 V
Turnoff time tOFF or CL = 50 pF, Full to 0.5 6.8 ns
VNC = V+ and VNO = GND, See Figure 8-4 5.5 V
4.5 V
Break-before-make VNC = VNO = V+/2, CL = 35 pF,
tBBM 25°C to 0.5 ns
time RL = 50 Ω, See Figure 8-5
5.5 V
VNC = VNO = V+/2,
Charge injection QC See Figure 8-9 25°C 5V 7 pC
RL = 50 Ω,
NC, NO CNC(OFF), Switch OFF,
VNC or VNO = V+ or GND, 25°C 5V 5.5 pF
OFF capacitance CNO(OFF) See Figure 8-3
NC, NO CNC(ON), Switch ON,
VNC or VNO = V+ or GND, 25°C 5V 17.5 pF
ON capacitance CNO(ON) See Figure 8-3
COM Switch ON,
CCOM(ON) VCOM = V+ or GND, 25°C 5V 17.5 pF
ON capacitance See Figure 8-3
Digital input
CIN VIN = V+ or GND, See Figure 8-3 25°C 5V 2.8 pF
capacitance
Switch ON,
Bandwidth BW RL = 50 Ω, 25°C 4.5 V 220 MHz
See Figure 8-6
RL = 50 Ω, Switch OFF,
OFF isolation OISO 25°C 4.5 V –65 dB
f = 10 MHz, See Figure 8-7
RL = 50 Ω, Switch ON,
Crosstalk XTALK 25°C 4.5 V –66 dB
f = 10 MHz, See Figure 8-8
f = 600 Hz to
Total harmonic RL = 600 Ω,
THD 20 kHz, 25°C 4.5 V 0.01 %
distortion CL = 50 pF,
See Figure 8-10
Supply

Positive supply Switch ON or 25°C 1

I+ VIN = V+ or GND, 5.5 V μA
current OFF Full 10
Change in
ΔI+ VIN = V+ – 0.6 V Full 5.5 V 500 μA
supply current

(1) TA = 25°C
(2) Hold all unused digital inputs of the device at V+ or GND to ensure proper device operation. See the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.

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6.3 Electrical Characteristics for 3.3-V Supply

V+ = 3 V to 3.6 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS TA V+ MIN TYP(1) MAX UNIT
Analog Switch
VCOM,
Analog signal range 0 V+ V
VNO, VNC
0 ≤ VNO or VNC ≤ V+, Switch ON,
ON-state resistance ron Full 3V 23 Ω
ICOM = –24 mA, See Figure 8-1
ON-state resistance
VNO or VNC = 2.1 V, Switch ON,
match between Δron 25°C 3V 0.2 Ω
ICOM = –24 mA, See Figure 8-1
channels
ON-state resistance 0 ≤ VNO or VNC ≤ V+, Switch ON,
ron(flat) 25°C 3V 9 Ω
flatness ICOM = –24 mA, See Figure 8-1

NC, NO INC(OFF), VNC or VNO = 0 to V+, Switch OFF, 25°C –1 0.05 1

3.6 V μA
OFF leakage current INO(OFF) VCOM = 0 to V+, See Figure 8-2 Full –1 1

NC, NO INC(ON), VNC or VNO = 0 to V+, Switch ON, 25°C –0.1 0.1
3.6 V μA
ON leakage current INO(ON) VCOM = Open, See Figure 8-2 Full –1 1

COM VNC or VNO = Open, Switch ON, 25°C –0.1 0.1

ICOM(ON) 3.6 V μA
ON leakage current VCOM = 0 to V+, See Figure 8-2 Full –1 1
Digital Inputs (IN1, IN2)(2)
Input logic high VIH Full V+ × 0.7 V
Input logic low VIL Full V+ × 0.3 V

Input leakage 25°C –1 0.05 1

IIH, IIL VIN = 5.5 V or 0 3.6 V μA
current Full –1 1
Dynamic
VNC = GND and VNO = V+, RL = 500 Ω,
3 V to
Turnon time tON or CL = 50 pF, Full 2.0 10.6 ns
3.6 V
VNC = V+ and VNO = GND, See Figure 8-4
VNC = GND and VNO = V+, RL = 500 Ω,
3 V to
Turnoff time tOFF or CL = 50 pF, Full 1.0 8.3 ns
3.6 V
VNC = V+ and VNO = GND, See Figure 8-4
Break-before-make VNC = VNO = V+/2, CL = 35 pF, 3 V to
tBBM 25°C 0.5 ns
time RL = 50 Ω, See Figure 8-5 3.6 V
RL = 50 Ω,
Charge injection QC See Figure 8-9 25°C 3.3 V 3 pC
CL = 0.1 nF,
RL = 50 Ω,
Bandwidth BW See Figure 8-6 25°C 3V 220 MHz
Switch ON,
RL = 50 Ω, Switch OFF,
OFF isolation OISO 25°C 3V –65 dB
f = 10 MHz, See Figure 8-7
RL = 50 Ω, Switch ON,
Crosstalk XTALK 25°C 3V –66 dB
f = 10 MHz, See Figure 8-8
f = 600 Hz to
Total harmonic RL = 600 Ω,
THD 20 kHz, 25°C 3V 0.015 %
distortion CL = 50 pF,
See Figure 8-10
Supply

Positive supply Switch ON or 25°C 1

I+ VIN = V+ or GND, 3.6 V μA
current OFF Full 10
Change in
ΔI+ VIN = V+ – 0.6 V Full 3.6 V 500 μA
supply current

(1) TA = 25°C
(2) Hold all unused digital inputs of the device at V+ or GND to ensure proper device operation. See the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.

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6.4 Electrical Characteristics for 2.5-V Supply

V+ = 2.3 V to 2.7 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS TA V+ MIN TYP(1) MAX UNIT
Analog Switch
VCOM,
Analog signal range 0 V+ V
VNO, VNC
0 ≤ VNO or VNC ≤ V+, Switch ON,
ON-state resistance ron Full 2.3 V 50 Ω
ICOM = –8 mA, See Figure 8-1
ON-state resistance
VNO or VNC = 1.6 V, Switch ON,
match Δron 25°C 2.3 V 0.5 Ω
ICOM = –8 mA, See Figure 8-1
between channels
ON-state resistance 0 ≤ VNO or VNC ≤ V+, Switch ON,
ron(flat) 25°C 2.3 V 27 Ω
flatness ICOM = –8 mA, See Figure 8-1

NC, NO INC(OFF), VNC or VNO = 0 to V+, Switch OFF, 25°C –1 0.05 1

2.7 V μA
OFF leakage current INO(OFF) VCOM = 0 to V+, See Figure 8-2 Full –1 1

NC, NO INC(ON), VNC or VNO = 0 to V+, Switch ON, 25°C –0.1 0.1
2.7 V μA
ON leakage current INO(ON) VCOM = Open, See Figure 8-2 Full –1 1

COM VNC or VNO = Open, Switch ON, 25°C –0.1 0.1

ICOM(ON) 2.7 V μA
ON leakage current VCOM = 0 to V+, See Figure 8-2 Full –1 1
Digital Inputs (IN1, IN2)(2)
Input logic high VIH Full V+ × 0.7 V
Input logic low VIL Full V+ × 0.3 V

Input leakage 25°C –1 0.05 1

IIH, IIL VIN = 5.5 V or 0 2.7 V μA
current Full –1 1
Dynamic
VNC = GND and VNO = V+, RL = 500 Ω, 2.3 V
Turnon time tON or CL = 50 pF, Full to 2.5 17 ns
VNC = V+ and VNO = GND, See Figure 8-4 2.7 V
VNC = GND and VNO = V+, RL = 500 Ω, 2.3 V
Turnoff time tOFF or CL = 50 pF, Full to 1.5 10.5 ns
VNC = V+ and VNO = GND, See Figure 8-4 2.7 V
2.3 V
Break-before-make VNC = VNO = V+/2, CL = 35 pF,
tBBM 25°C to 0.5 ns
time RL = 50 Ω, See Figure 8-5
2.7 V
Switch ON,
Bandwidth BW RL = 50 Ω, 25°C 2.3 V 220 MHz
See Figure 8-6
RL = 50 Ω, Switch OFF,
OFF isolation OISO 25°C 2.3 V –65 dB
f = 10 MHz, See Figure 8-7
RL = 50 Ω, Switch ON,
Crosstalk XTALK 25°C 2.3 V –66 dB
f = 10 MHz, See Figure 8-8
f = 600 Hz to
Total harmonic RL = 600 Ω,
THD 20 kHz, 25°C 2.3 V 0.025 %
distortion CL = 50 pF,
See Figure 8-10
Supply

Positive supply Switch ON or 25°C 1

I+ VIN = V+ or GND, 2.7 V μA
current OFF Full 10
Change in
ΔI+ VIN = V+ – 0.6 V Full 2.7 V 500 μA
supply current

(1) TA = 25°C
(2) Hold all unused digital inputs of the device at V+ or GND to ensure proper device operation. See the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.

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6.5 Electrical Characteristics for 1.8-V Supply

V+ = 1.65 V to 1.95 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS TA V+ MIN TYP(1) MAX UNIT
Analog Switch
VCOM,
Analog signal range 0 V+ V
VNO, VNC
0 ≤ VNO or VNC ≤ V+, Switch ON,
ON-state resistance ron Full 1.65 V 180 Ω
ICOM = –4 mA, See Figure 8-1
ON-state resistance
VNO or VNC = 1.15 V, Switch ON,
match between Δron 25°C 1.65 V 1 Ω
ICOM = –4 mA, See Figure 8-1
channels
ON-state resistance 0 ≤ VNO or VNC ≤ V+, Switch ON,
ron(flat) 25°C 1.65 V 110 Ω
flatness ICOM = –4 mA, See Figure 8-1

NC, NO INC(OFF), VNC or VNO = 0 to V+, Switch OFF, 25°C –1 0.05 1

1.95 V μA
OFF leakage current INO(OFF) VCOM = 0 to V+, See Figure 8-2 Full –1 1

NC, NO INC(ON), VNC or VNO = 0 to V+, Switch ON, 25°C –0.1 0.1
1.95 V μA
ON leakage current INO(ON) VCOM = Open, See Figure 8-2 Full –1 1

COM VNC or VNO = Open, Switch ON, 25°C –0.1 0.1

ICOM(ON) 1.95 V μA
ON leakage current VCOM = 0 to V+, See Figure 8-2 Full –1 1
Digital Inputs (IN1, IN2)(2)
Input logic high VIH Full V+ × 0.75 V
Input logic low VIL Full V+ × 0.25 V

Input leakage 25°C –1 0.05 1

IIH, IIL VIN = 5.5 V or 0 1.95 V μA
current Full –1 1
Dynamic
VNC = GND and VNO = V+, RL = 500 Ω, 1.65 V
Turnon time tON or CL = 50 pF, Full to 5.5 27 ns
VNC = V+ and VNO = GND, See Figure 8-4 1.95 V
VNC = GND and VNO = V+, RL = 500 Ω, 1.65 V
Turnoff time tOFF or CL = 50 pF, Full to 2 16 ns
VNC = V+ and VNO = GND, See Figure 8-4 1.95 V
1.65 V
Break-before-make VNC = VNO = V+/2, CL = 35 pF,
tBBM 25°C to 0.5 ns
time RL = 50 Ω, See Figure 8-5
1.95 V
Switch ON,
Bandwidth BW RL = 50 Ω, 25°C 1.8 V 220 MHz
See Figure 8-6
RL = 50 Ω, Switch OFF,
OFF isolation OISO 25°C 1.8 V –60 dB
f = 10 MHz, See Figure 8-7
RL = 50 Ω, Switch ON,
Crosstalk XTALK 25°C 1.8 V –66 dB
f = 10 MHz, See Figure 8-8
f = 600 Hz to
Total harmonic RL = 600 Ω,
THD 20 kHz, 25°C 1.8 V 0.015 %
distortion CL = 50 pF,
See Figure 8-10
Supply

Positive supply Switch ON or 25°C 1

I+ VIN = V+ or GND, 1.95 V μA
current OFF Full 10
Change in
ΔI+ VIN = V+ – 0.6 V Full 1.95 V 500 μA
supply current

(1) TA = 25°C
(2) Hold all unused digital inputs of the device at V+ or GND to ensure proper device operation. See the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.

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6.6 Typical Characteristics

140 12
TA = 255C TA = 25°C
120 10
V+ = 1.65 V
100 8

tON/tOFF − ns
80
ron − Ω

6
tON
60
4
V+ = 2.3 V tOFF
40
2
20 V+ = 3 V
V+ = 4.5 V
0
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0 1 2 3 4 5 V+ − Supply Voltage − V
VCOM − V
Figure 6-2. tON and tOFF versus V+
Figure 6-1. ron versus VCOM

5 10
tON
0
4 −10
Bandwidth
−20
tON/tOFF − ns

3 tOFF Loss − dB −30

−40
−50
2 Off-Isolation
−60
−70 TA = 25°C
1
−80
−90 Crosstalk
0
−60 −40 −20 0 20 40 60 80 100 −100
0.1 1 10 100 1000
TA − Temperature − 5C Frequency − MHz
Figure 6-3. tON and tOFF versus Temperature (V+ = 5 V) Figure 6-4. Frequency Response (V+ = 3 V)

0.0020
0.0018
0.0016
THD + Noise − %

0.0014
0.0012
0.0010
0.0008
0.0006
0.0004
0.0002 TA = 25°C
0.0000
100 1000 10000
Frequency −Hz
Figure 6-5. Total Harmonic Distortion (THD) versus Frequency (V+ = 3 V)

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7 Parameter Description
SYMBOL DESCRIPTION
VCOM Voltage at COM
VNC Voltage at NC
VNO Voltage at NO
ron Resistance between COM and NC or COM and NO ports when the channel is ON
Δron Difference of ron between channels
ron(flat) Difference between the maximum and minimum value of ron in a channel over the specified range of conditions
Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the OFF state under
INC(OFF)
worst-case input and output conditions
Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the OFF state under
INO(OFF)
worst-case input and output conditions
Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the ON state and the output
INC(ON)
(COM) being open
Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the ON state and the output
INO(ON)
(COM) being open
Leakage current measured at the COM port, with the corresponding channel (NO to COM or NC to COM) in the ON state
ICOM(ON)
and the output (NC or NO) being open
VIH Minimum input voltage for logic high for the control input (IN)
VIL Minimum input voltage for logic low for the control input (IN)
VIN Voltage at IN
IIH, IIL Leakage current measured at IN
Turnon time for the switch. Measure this parameter under the specified range of conditions and by the propagation delay
tON
between the digital control (IN) signal and analog output (COM/NC/NO) signal when the switch is turning ON.
Turnoff time for the switch. Measure this parameter under the specified range of conditions and by the propagation delay
tOFF
between the digital control (IN) signal and analog output (COM/NC/NO) signal when the switch is turning OFF.
Break-before-make time. Measure this parameter under the specified range of conditions and by the propagation delay
tBBM
between the output of two adjacent analog channels (NC and NO) when the control signal changes state.
Charge injection is a measurement of unwanted signal coupling from the control (IN) input to the analog (NC, NO, or
QC COM) output. This measure is in coulombs (C) and is the total charge induced due to switching of the control input.
Charge injection, QC = CL× ΔVO, CL is the load capacitance and ΔVO is the change in analog output voltage.
CNC(OFF) Capacitance at the NC port when the corresponding channel (NC to COM) is OFF
CNO(OFF) Capacitance at the NO port when the corresponding channel (NC to COM) is OFF
CNC(ON) Capacitance at the NC port when the corresponding channel (NC to COM) is ON
CNO(ON) Capacitance at the NO port when the corresponding channel (NC to COM) is ON
CCOM(ON) Capacitance at the COM port when the corresponding channel (COM to NC or COM to NO) is ON
CIN Capacitance of IN
OFF isolation of the switch is a measurement of OFF-state switch impedance. This measure is in dB at a specific
OISO frequency, with the corresponding channel (NC to COM or NO to COM) in the OFF state. OFF isolation, OISO = 20 LOG
(VNC/VCOM) dB, VCOM is the input and VNC is the output.
Crosstalk is a measurement of unwanted signal coupling from an ON channel to an OFF channel (NC to NO or NO to
XTALK NC). This measure is at a specific frequency and in dB. Crosstalk, XTALK = 20 log (VNC1/VNO1), VNO1 is the input and VNC1
is the output.
Bandwidth of the switch. This is the frequency where the gain of an ON channel is –3 dB below the dc gain. Gain is
BW
measured from the equation, 20 log (VNC/VCOM) dB, where VNC is the output and VCOM is the input.
I+ Static power-supply current with the control (IN) pin at V+ or GND
ΔI+ This is the increase in I+ for each control (IN) input that is at the specified voltage, rather than at V+ or GND.

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8 Parameter Measurement Information

V+

VNC
NC VCOM
NO Channel ON
VNO COM
VCOM * VNOńNC
r on + W
ICOM
IN ICOM
VIN VIN = VIH or VIL

GND

Figure 8-1. ON-State Resistance (Ron)

V+
OFF-State Leakage Current
Channel OFF
VIN = VIH or VIL
VNC
NC VCOM VNC or VNO = 0 to V+
or
VNO NO VCOM = 0 to V+
COM

ON-State Leakage Current

IN
VIN Channel ON
VIN = VIH or VIL
GND VNC or VNO = 0 to V+, VCOM = Open
or
VNC or VNO = Open, VCOM = 0 to V+

Figure 8-2. ON- and OFF-State Leakage Current (ICOM(ON), INC(OFF), INO(OFF), INC(ON), INO(ON))

V+

VCOM

Capacitance VBIAS = V+ or GND

Meter VNC
VIN = VIH or VIL
VNO
Capacitance is measured at NC,
VBIAS IN NO, COM, and IN inputs during
VIN
ON and OFF conditions.

GND

Figure 8-3. Capacitance (CIN, CCOM(ON), CNC(OFF), CNO(OFF), CNC(ON), CNO(ON))

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V+
TEST RL CL VNC VNO
GND V+
tON 500 Ω 50 pF
VNC or VNO V+ GND
VCOM
NC or NO GND V+
tOFF 500 Ω 50 pF
V+ GND
NC or NO COM
RL CL
Logic
IN VIN 50% 50%
VIN Input

Logic tON tOFF

GND
Input
Switch 90% 90%
VCOM
Output

Figure 8-4. Turn-On Time (tON) and Turn-Off Time (tOFF)

V+ tr < 5 ns
tf < 5 ns

VI Logic
VCOM VIN 50%
Input
NC or NO
0
NC or NO
COM
RL CL Switch
Output VCOM
VIN IN 90% 90%

Logic VI = V+/2
GND tBBM
Input
RL = 50 Ω
CL = 35 pF

Figure 8-5. Break-Before-Make Time (tBBM)

V+
Network Analyzer

50 W VNC Channel ON: NC to COM

NC
COM VCOM VCOM
Source Gain + 20 log dB
NO VNC
Signal

VIN IN Network Analyzer Setup

50 W

GND Source Power = 0 dBM

DC Bias = 350 mV

Figure 8-6. Frequency Response (BW)

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V+
Network Analyzer

50 W VNC Channel OFF: NC to COM

NC
COM VCOM VCOM
OFF Isolation + 20 log dB
Source VNC
50 W NO
Signal

GND Network Analyzer Setup

50 W
Source Power = 0 dBM
DC Bias = 350 mV

Figure 8-7. OFF Isolation (OISO)

V+
Network Analyzer
Channel ON: NC to COM
50 W VNC NC Channel OFF: NO to COM
VCOM VNO
Source Crosstalk + 20 log dB
NO VNC
Signal
VNO 50 W
GND Network Analyzer Setup
50 W
Source Power = 0 dBM
DC Bias = 350 mV

Figure 8-8. Crosstalk (XTALK)

V+ VINH
Logic
VIN
Input OFF ON OFF
RGEN VINL
VOUT
NC or NO
+ VOUT ∆VOUT
VGEN NC or NO COM
RL CL
VGEN = 0
VIN IN RGEN = 0
RL = 1 MΩ
Logic CL = 35 pF
Input GND
QC = CL × ∆VOUT
VIN = VIH or VIL

Figure 8-9. Charge Injection (QC)

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V+/2 Channel ON: COM to NC

V+ VSOURCE = 0.5 V P-P

fSOURCE = 600 Hz to 20 kHz
RL
10 mF RL = 600 Ω
NC CL = 50 pF
Analyzer 10 mF
VO
CL NO
COM
RL VSOURCE
GND

Figure 8-10. Total Harmonic Distortion (THD)

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9 Function and Summary of Characteristics

Input In NC to COM | COM to NC NO to COM | COM to NO
L ON OFF
H OFF ON

Table 9-1. Summary of Characteristics

2:1 Multiplexer and
Configuration Demultiplexer
(2 × SPDT)
Number of channels 2
ron 15 Ω
Δron 0.15 Ω
ron(flat) 4Ω
tON 8.7 ns
tOFF 6.8 ns
tBBM 0.5 ns
Charge injection 7 pC
Bandwidth 220 MHz
OFF isolation –65 dB at 10 MHz
Crosstalk –66 dB at 10 MHz
Total harmonic distortion 0.01%
ICOM(off)/INC(OFF) ±1 μA
Package option 10-pin DGS

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10 Detailed Description
10.1 Overview
The TS5A23157-Q1 is a 2 channel 2:1 switch (SPDT). It has a wide operating supply of 1.8 V to 5.5 V that
allows for use in a wide array of applications from sample and hold circuits to communication protocol switching
such as I2C or UART. The device supports bidirectional analog and digital signals on the source (NCx and NOx)
and drain (COMx) pins.
10.2 Functional Block Diagram

Figure 10-1. TS5A23157-Q1 Functional Block Diagram

10.3 Feature Description

Bidirectional Operation
The TS5A23157-Q1 conducts equally well from source (NCx and NOx) to drain (COMx) or from drain (COMx) to
source (NCx and NOx). Each channel has similar characteristics in both directions and supports both analog and
digital signals.
10.4 Device Functional Modes
The digital control pins (IN1 and IN2) are the logic pins that control their respective common connections (COM1
and COM2) with both the normally closed pathways (NC1 and NC2) and the normally open pathways (NO1 and
NO2). When either or both digital control pins (IN1 and IN2) are pulled low their respecitive common (COM1 and
COM2) and normally closed (NC1 and NC2) pins are connected. When either or both digital control pins (IN1
and IN2) are pulled high their respective common (COM1 and COM2) and normally open (NO1 and NO2) pins
are connected.
The TS5A23157-Q1 can be operated without any external components except for the supply decoupling
capacitors. Unused logic control pins (INx) should be tied to GND or VDD in order to ensure the device does not
consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path
inputs (NCx, NOx, and COMx) should be connected to GND.

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11 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

11.1 Application Information

Common applications that require the features of the TS5A23157-Q1 include multiplexing various protocols from
a processor MCU such as I2C, UART, or standard GPIO signals. With the TS5A23157-Q1's wide operating
supply range different variations of signal levels with GPIO, UART, and I2C can all be passed and the supply
voltage can vary with the needs of the system designer. A typical UART application is shown in the Typical
Application Section.

11.2 Typical Application

Figure 11-1. TS5A23157-Q1 Used in UART Application

11.3 Design Requirements

For the typical application shown above - please use the following parameters shown below.
Table 11-1. Design Parameters
PARAMETER VALUE
Supply Voltage 3.3 V
Input / Output Voltage 0 V – 3.3 V
Logic Input High 2.31 V – 3.3 V
Logic Input Low 0 V – 0.99 V

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11.4 Detailed Design Procedure

The TS5A23157-Q1 can be operated without any external components except for the supply decoupling
capacitors. To ensure known logic states at start up - use pull-down resistors, between 10 KΩ and 100 KΩ, on
each control input (INx). All inputs signals passing through the switch must fall within the recommend operating
conditions of the TS5A23157-Q1 including signal range and continuous current. For this design example, with a
supply of 3.3 V, the signals can range from 0 V to 3.3 V when the device is powered. Due to the voltage range
and bandwidth of the switch, it can support many applications such as I2C, UART, and GPIO switching.
11.5 Application Performance Plots
Three important parameters when using the TS5A23157-Q1 in any communication protocol / GPIO switching
application are the bandwidth of the switch as well as off isolation and cross talk. The below figure shows the
typical bandwidth, off isolation, and cross talk versus frequency. When implenmenting this use case of the switch
it is crucial to understand the AC error that other signals may create when using this device.
10
0
−10
Bandwidth
−20
−30
Loss − dB

−40
−50
Off-Isolation
−60
−70 TA = 25°C
−80
−90 Crosstalk
−100
0.1 1 10 100 1000
Frequency − MHz

Figure 11-2. AC Parmeters for TS5A23157-Q1 (V+ = 3V)

12 Power Supply Recommendations

The TS5A23157-Q1 operates across a wide supply range of 1.8 V to 5.5 V. Do not exceed the absolute
maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD
supply to other components. Good power-supply decoupling is important to achieve optimum performance.
For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from
VDD to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using
low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.

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13 Layout

13.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.The figure below shows progressively better techniques of rounding corners. Only the last example
(BEST) maintains constant trace width and minimizes reflections.

Figure 13-1. Trace Guidelines for TS5A23157-Q1

Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, throughhole
pins are not recommended at high frequencies. Do not route high speed signal traces under or near crystals,
oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices or ICs that use or
duplicate clock signals. Avoid stubs on the high-speed signals traces because they cause signal reflections.
Route all high-speed signal traces over continuous GND planes, with no interruptions. Avoid crossing over
anti-etch, commonly found with plane splits. When working with high frequencies, a printed circuit board with at
least four layers is recommended; two signal layers separated by a ground and power layer as shown below.

Figure 13-2. Layer Stack Example for TS5A23157-Q1 device.

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13.2 Layout Example

• Decouple the VDD pin with a 0.1 μF capacitor, placed as close to the pin as possible.
• Make sure that the capacitor voltage rating is sufficient for the VDD supply.
• High-speed switches require proper layout and design procedures for optimum performance.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

Figure 13-3. Layout Example of TS5A23157-Q1

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14 Device and Documentation Support

14.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
14.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
14.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

14.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
15.1 Ordering Information
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 105°C VSSOP 10 – (DGS) Tape and reel TS5A23157TDGSRQ1 JBR
–40°C to 125°C VSSOP 10 – (DGS) Tape and reel TS5A23157QDGSRQ1 SJC

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 PACKAGE OPTION ADDENDUM

www.ti.com 22-Apr-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TS5A23157QDGSRQ1 ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 SJC

TS5A23157TDGSRQ1 ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 JBR

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 22-Apr-2021

OTHER QUALIFIED VERSIONS OF TS5A23157-Q1 :

• Catalog : TS5A23157

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Apr-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS5A23157QDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TS5A23157TDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Apr-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TS5A23157QDGSRQ1 VSSOP DGS 10 2500 346.0 346.0 29.0
TS5A23157TDGSRQ1 VSSOP DGS 10 2500 346.0 346.0 29.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID 0.1 C
AREA

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
SEE DETAIL A 0.13

0.25
GAGE PLANE

0.7 0.15
0 -8 0.05
0.4

DETAIL A
TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10

SYMM

8X (0.5) 5 6

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10

SYMM
8X (0.5)

5 6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221984/A 05/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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