Enhancing Performance with

Pipelining
Chapter Four
of
The Book of David A. Patterson
 Pipelined Datapath
✔ The 5 steps in instruction execution are:
1. Instruction Fetch & PC Increment (IF)
2. Instruction Decode and Register Read (ID)
3. Execution or calculate address (EX)
4. Memory access (MEM)
5. Write result into register (WB)
✔ Review: single-cycle processor
1. all 5 steps done in a single clock cycle
2. dedicated hardware required for each step
 Review - Single-Cycle Datapath
“Steps”
ADD

4 ADD

PC <<2
Instruction I
ADDR RD
32 16 32
5 5 5
Instruction
Memory RN RN WN
1 2 RD Zero
Register File1 ALU
WD
RD M
2 U ADDR
X
Data
Memory RD M
E U
16 X 32 X
T WD
N
D

IF ID EX MEM WB
Instruction Fetch Instruction Decode Execute/ Address Calc. Memory Access Write Back
 Pipelined Datapath
Pipeline registers wide enough to hold data coming in

AD
D

4 AD
64 bits 128 bits D

PC <<2 97 bits 64 bits

Instruction I
ADDR RD
32 16 32
5 5 5
Instruction
Memory RN RN WN
1 2 RD Zero
Register File1 AL
WD U
RD M
2 U ADDR
X
Data
Memory RD M
E U
16 X 32 X
T WD
N
D

IF/ID ID/EX EX/MEM MEM/WB

Only data flowing right to left may cause hazard…, why?
 Pipelined Datapath
✔ No pipeline register at the end of write back stage. In this
stage we write a register in the register file and any later
instruction can get this data by reading this register. So no
need for redundant register.
✔ Each component of the data path is associated with a single
stage.
✔ Each register contains a portion of the instruction needed
for that stage and latter stages.
Pipeline Flow (lw example)
Pipeline Flow (lw example)
Pipeline Flow (lw example)
Pipeline Flow (lw example)
Pipeline Flow (lw example)
 Bug in the Datapath

IF/ID ID/EX EX/MEM MEM/W

AD B
D

4 AD
D

PC <<2
Instruction I
ADDR RD
32 16 32
5 5 5
Instruction
Memory RN RN WN
1 2 RD
Register File1 AL
WD U
RD M
2 U ADDR
X
Data
Memory RD M
E U
1 X 3 X
6 T 2 WD
N
D

Write register number comes from another later instruction!

 Corrected Datapath
IF/ID ID/EX EX/MEM MEM/W
B
ADD
ADD
4 64 bits 133 bits
102 bits 69 bits
<<2
PC
ADDR RD 5
RN1 RD1
32
ALU Zer
Instruction RN2
5 o
Memory Register
5
WN File RD2
M
WD U ADDR
X
Data
E Memory RD M
U
16 X 32 X
T WD
N
5 D

Destination register number is also passed through ID/EX, EX/MEM

and MEM/WB registers, which are now wider by 5 bits
 Pipelined Example
• Consider the following instruction sequence:
lw $t0, 10($t1)
sw $t3, 20($t4)
add $t5, $t6, $t7
sub $t8, $t9, $t10
Single-Clock-Cycle Diagram:
LW Clock Cycle 1
 Single-Clock-Cycle Diagram:
Clock Cycle 2
SW LW
 Single-Clock-Cycle Diagram:
Clock Cycle 3
ADD SW LW
 Single-Clock-Cycle Diagram:
Clock Cycle 4
SUB ADD SW LW
Single-Clock-Cycle Diagram:
Clock Cycle 5
SUB ADD SW LW
Single-Clock-Cycle Diagram:
Clock Cycle 6
SUB ADD SW
Single-Clock-Cycle Diagram:
Clock Cycle 7
SUB ADD
Single-Clock-Cycle Diagram:
Clock Cycle 8
SUB
 Alternative View –
Multiple-Clock-Cycle Diagram
CC CC CC CC CC CC CC CC
1 2 3 4 5 6 7 8
Time axis
lw $t0, 10($t1) I RE AL D RE
M G U M G

sw $t3, 20($t4) I RE AL D RE
M G U M G

add $t5, $t6, $t7 I RE AL D RE

M G U M G

sub $t8, $t9, $t10 I RE AL D RE

M G U M G
Pipelined Datapath with Control
Signals
Control Signal for the Pipeline
Datapath
Control Signal for the Pipeline
Datapath
Control Signals Generation
Pipelined Datapath with control Signals
Connected
The Grand Example
lw $10, 20($1)
sub $11, $2, $3
and $12, $4, $5
or $13, $6, $7
add $14, $8, $9
The Grand Example
The Grand Example
The Grand Example
The Grand Example
The Grand Example
The Grand Example
The Grand Example
The Grand Example
The Grand Example