UNIT 1: Introduction to Verilog

SYLLABUS:
A Brief History of HDL, Structure of HDL Module, Comparison of VHDL
and Verilog
Introduction to Simulation and Synthesis Tools, Test Benches, Verilog
Modules, Delays, data flow style, behavioral style, structural style, mixed
design style, simulating design
Introduction to Language Elements: Keywords, Identifiers, White Space
Characters, Comments, Format, Integers, Reals and Strings, Logic Values,
Data Types-net types, undeclared nets, scalars and vector nets, Register
type, Parameters, Expressions, Operands, Operators, types of Expressions

 A Brief History of HDL

Verilog HDL was invented by Phil Moorby and Prabhu Goel around 1984. It served as a
proprietary hardware modeling language owned by Gateway Design Automation Inc. At
that time, the language was not standardized. It modified itself in almost all the revisions
that came out between 1984 to1990.
In 1990, Gateway Design Automation Inc. was acquired by Cadence Design System, which
is now one of the biggest suppliers of electronic design technologies and engineering
services in the electronic design automation (EDA) industry. Cadence recognized the value
of Verilog, and realized that if Verilog remained as a closed language, the pressure of
standardization would eventually drive people to shift to VHDL. So in 1991 the Open
Verilog International (OVI) (now known as Accellera) was organized by Candence and the
documentation of Verilog was transferred to public domain under the name of OVI. It was
later submitted to IEEE and became IEEE standard 1364-1995, commonly referred as
Verilog-95.
In 2001, extensions to Verilog-95 were submitted back to IEEE and became IEEE standard
1364-2001, known as Verilog-2001. The extensions covered some deficiencies that users
had found in the Verilog-95. One of the most significant upgrades was that signed variables
(in 2.s complement) became supported. Verilog-2001 is now the dominant edition of
Verilog supported by most design tools.
In 2005, Verilog-2005 (IEEE Standard 1364-2005) was published with minor corrections
and modifications. Also in 2005 System Verilog, a superset of Verilog-2005, with many

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new features and capabilities to aid design verification, was published. As of 2009, System
Verilog and Verilog language standards were merged into System Verilog 2009 (IEEE
Standard 1800-2009), which is one of the most popular languages for IC design and
verification today. Xilinx ® Vivado Design Suite, released in 2013, can support System
Verilog for FPGA design and verification.

Why Verilog?
 Why use an HDL?
Describe complex designs (millions of gates)

Input to synthesis tools (synthesizable subset)

Design exploration with simulation

 Why not use a general purpose language

Support for structure and instantiation (objects?)

Support for describing bit-level behavior

Support for timing

Support for concurrency

• Verilog vs. VHDL

Verilog is relatively simple and close to C

VHDL is complex and close to Ada

Verilog has 60% of the world digital design market (larger share in US)

• Verilog modeling range

From gates to processor level

We’ll focus on RTL (register transfer level)

 HARDWARE DESCRIPTION LANGUAGE

Hardware description language (HDL) is a specialized computer language used to program
electronic and digital logic circuits. The structure, operation and design of the circuits are
programmable using HDL. HDL includes a textual description consisting of operators,
expressions, statements, inputs and outputs. Instead of generating a computer executable
file, the HDL compilers provide a gate map. The gate map obtained is then downloaded to
the programming device to check the operations of the desired circuit. The language helps

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to describe any digital circuit in the form of structural, behavioral and gate level and it is
found to be an excellent programming language for FPGAs and CPLDs.

The three common HDLs are Verilog, VHDL, and System C. Of these, System C is the
newest. The HDLs will allow fast design and better verification. In most of the industries,
Verilog and VHDL are common. Verilog, one of the main Hardware Description Language
standardized as IEEE 1364 is used for designing all types of circuits. It consists of modules
and the language allows Behavioral, Dataflow and Structural Description. VHDL (Very
High Speed Integrated Circuit Hardware Description Language) is standardized by
IEEE1164. The design is composed of entities consisting of multiple architectures. System
C is a language that consist a set of C++ classes and macros. It allows electronic system
level and transaction modeling.

 Need for HDLs

The Moore’s Law in the year 1970 has brought a drastic change in the field of IC
technology. This change has made the developers to bring out complex digital and electronic
circuits. But the problem was the absence of a better programming language allowing
hardware and software co-design. Complex digital circuit designs require more time for
development, synthesis, simulation and debugging. The arrival of HDLs has helped to solve
this problem by allowing each module to be worked by a separate team.

All the goals like power, throughput, latency (delay), test coverage, functionality and area
consumption required for a design can be known by using HDL. As a result, the designer
can make the necessary engineering tradeoffs and can develop the design in a better and
efficient way. Simple syntax, expressions, statements, concurrent and sequential
programming is also necessary while describing the electronics circuits. All these features
can be obtained by using a hardware description language. Now while comparing HDL and
C languages, the major difference is that HDL provides the timing information of a design.

 HDL STRUCTURE & DESIGN

Generally, HDL structure consist a textual description involving many inputs, outputs,
signals operators, components, multiple architectures, and comments. Concurrent and
sequential way of programming style is possible in HDL. Each and every HDL uses a
different structure and design method. The examples shown below using Verilog will help
to get an overall idea about HDL structure and design.

Verilog

OR GATE EXAMPLE

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 Using Data Flow Modeling: Instead of using the assignment operator, it uses the
continuous assignment statement with the keyword ‘assign’. Verilog generally defines
each circuit using a module. The module will generally involve the name of the design,
its inputs and outputs and functionality.
 OR Gate - example ‘or gate’ is the module name. In Verilog we generally use wires and
registers to define the variables. Here the OR function is represented by using the
operator ‘|’.Generally, Verilog involves arithmetic, logical, relational, equality, bitwise,
reduction, shift, concatenation, replication and conditional operators.

 Using Structural Modeling: In this model, the component represents another design
module.

 Using Behavioral Modeling: In Verilog, this model is exactly similar to C. Here we

use always block were the statements are written. Reg is used to declare the variable.

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  COMPARISON OF VHDL AND VERILOG
What is Verilog?
Verilog is an HDL (Hardware Description Language). The latest stable version of Verilog
is IEEE 1364-2005. Verilog is a case sensitive language which only uses lowercase. It
supports simulation. In other words, it is possible to create a model of a function and
simulate it before building the real system. The base language of Verilog is C. Therefore, a
programmer who is familiar with C can learn Verilog quickly.
Module is the basic building block in Verilog. It provides information about input and
output ports and hides the internal implementation details. Every Verilog program starts
with the keyword “module” and ends with the keyword “endmodule”.
module <module_name> (input, output);
<program logic>

endmodule

What is VHDL?
VHDL is an HDL that helps to describe circuits in digital systems. A hardware module in
VHDL is called an entity. The syntax is as follows. The entity starts with “entity” and ends
with “end” keyword.
entity <entity_name> is

port declaration;

end entity_name;

Definition
Verilog is an HDL used to model electronic systems while VHDL is an HDL used
in electronic design automation to describe digital and mixed-signal systems such
as field programmable gate arrays and integrated circuits.
Base Language
The main difference between Verilog and VHDL is that Verilog is based on C
language while VHDL is based on Ada and Pascal languages.
Case Sensitive
Moreover, one other difference between Verilog and VHDL is that Verilog is case
-sensitive while VHDL is not case sensitive.

Introduced Time Period

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 Verilog is a newer language than VHDL as Verilog was introduced in 1984 while
VHDL was introduced in 1980.
Complexity
Complexity is another difference between Verilog and VHDL. VHDL is complex
than Verilog.
Conclusion
Verilog and VHDL are two hardware description languages (HDL) that help to
describe digital electronic systems. The main difference between Verilog and VHDL
is that Verilog is based on C language while VHDL is based on Ada and Pascal
languages.

T. Y. B. Sc. (SEM - V) EL 351: UNIT: 1- INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade

  INTRODUCTION TO SIMULATION AND SYNTHESIS TOOLS
Digital Circuit Design Using Xilinx ISE Tools

Xilinx Tools is a suite of software tools used for the design of digital circuits
implemented using Xilinx Field Programmable Gate Array (FPGA) or Complex
Programmable Logic Device (CPLD). The design procedure consists of
(a) Design entry
(b) Synthesis and implementation of the design
(c) Functional simulation
(d) Testing and verification.
Digital designs can be entered in various ways using the above CAD tools: using a
schematic entry tool, using a hardware description language (HDL) – Verilog or VHDL
or a combination of both. In this lab we will only use the design flow that involves the
use of Verilog HDL.
The CAD tools enable you to design combinational and sequential circuits starting with
Verilog HDL design specifications.
The steps of this design procedure are listed below:
1. Create Verilog design input file(s) using template driven editor.
2. Compile and implement the Verilog design file(s).
3. Create the test-vectors and simulate the design (functional simulation)
without using a PLD (FPGA or CPLD).
4. Assign input/output pins to implement the design on a target device.
5. Download bit-stream to an FPGA or CPLD device.
6. Test design on FPGA/CPLD device
A Verilog input file in the Xilinx software environment consists of the following
segments:
Header: module name, list of input and output ports.
Declarations: input and output ports, registers and wires.
Logic Descriptions: equations, state machines and logic functions.
End: endmodule
All designs for this lab must be specified in the above Verilog input format. Note that
the State diagram segment does not exist for combinational logic designs.

 TEST BENCH


A test bench can be defined as a set-up which enables testing of an application by

replicating the real world use of the same. In software testing a file of code run on the
machine to check the hardware design.

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 A test bench can be created using either of the following ways:
Text Editor- Recommended for verifying quite complex designs that allows using the
available features in HDL. Offers a lot of flexibility in managing code and helps to
produce precise and accurate results.

Xilinx Test bench Waveform Editor- Ideal for less complex simulation tasks,
recommended for use by comparatively new users.

VHDL: This language has its roots in Ada programming language. VHDL stands for
VHSIC (Very High Speed Integrated Circuit) Hardware Description Language used
primarily in electronic design automation. This is a strongly typed language.

Verilog: This is again an HDL that is used in digital electronic systems, analog circuits
and mixed signal circuits. Verilog is a loosely typed language but has efficient notation.

Device under Test (DUT): A device under test can be simply thought of as a replica of
the actual design or something that is a behavioral representation of a design.

 Components of Test Bench :

Input -This includes the requirements that are needed to perform work. Basically this is the
entrance criteria for the test bench.
Output -It consists of the exit criteria or we can say the deliver ables achieved at the end
of the test bench.
Procedures to – The processes that will transfer the inputs into outputs
Procedures to check -These are the processes that determine whether the output meet the
required standard.

 TYPES OF TEST BENCH:

Stimulus Only - Contains only the driver containing the stimulus driver and the Design
under test but does not contain any result verification.
Full Test bench -This test bench contains the stimulus driver, the correct results and
results for comparison.
Simulator specific - The name suggests that the test bench is written in a simulator specific
format.
Hybrid test bench -This is a blend of techniques from more than one test bench style.
Fast test bench -It is to optimize the speed of a test bench. This is written in a way so as
to provide the best speed from a simulation.

T. Y. B. Sc. (SEM - V) EL 351: UNIT: 1- INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade

  VERILOG MODULE
A module can be element or collection of lower level design blocks. A module is the
basicbuilding block in Verilog. In Verilog, module is declared by the keyword ‘module’.
A corresponding keyword ‘endmodule’ must appear at the end of the module definition.
Each module must have a ‘module name’, which is identifier for the module and a
‘module terminal list’, which describe the input & output terminals of the module.

Module Declaration

 The first line of a module declaration specifies the name and port list (arguments).
 The next few lines specify the input type and width of each port. The default port
width is 1 bit.
 Then the port variables must be declared wire, wand, . . . , reg. The default is wire.
Typically inputs are wire since their data is latched outside the module. Outputs
are type reg if their signals were stored inside an always or initial block

Syntax

module module_name (port_list);

input [msb:lsb] input_port_list;

output [msb:lsb] output_port_list;

inout [msb:lsb] inout_port_list;

... statements ...
endmodule

Example
module add_sub (add, in1, in2, oot);

input add; // defaults to wire

input [7:0] in1, in2;

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 wire in1, in2;

output [7:0] oot;

reg oot;
... statements ...

endmodule

 TIMING AND DELAYS

Functional verification of hardware is used to verify functionality of the designed circuit.
However, blocks in real hardware have delays associated with the logic elements and
paths in them. Therefore, we must also check whether the circuit meets the timing
requirements, given the delay specifications for the blocks. Checking timing
requirements has become increasingly important as circuits have become smaller and
faster. One of the ways to check timing is to do a timing simulation that accounts for the
delays associated with the block during the simulation.
We discuss how timing and delays are controlled and specified in Verilog modules.
Thus, by using timing simulation, the designer can verify both functionality and timing
of the circuit with Verilog.
Types of Delay Models
There are three types of delay models used in Verilog: distributed, lumped, and pin-
to-pin (path) delays.
1. Distributed Delay
Distributed delays are specified on a per element basis. Distributed delays can be
modeled by assigning delay values to individual gates or by using delay values in
individual assign statements. When inputs of any gate change, the output of the gate
changes after the delay value specified.

//Distributed delays in gate-level modules

module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Delay is distributed to each gate.
and #5 a1(e, a, b);
and #7 a2(f, c, d);
and #4 a3(out, e, f);
endmodule

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//Distributed delays in data flow definition of a module
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Distributed delay in each expression
assign #5 e = a & b;
assign #7 f = c & d;
assign #4 out = e &f;

2. Lumped Delay
Lumped delays are specified on a per module basis. They can be specified as a single
delay on the output gate of the module. The cumulative delay of all paths is lumped at one
location.
//Lumped Delay Model
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
and a1(e, a, b);
and a2(f, c, d);
and #11 a3(out, e, f);//delay only on the output gate
endmodule
Lumped delays models are easy to model compared with distributed delays.

3. Pin-to-Pin Delays
Another method of delay specification for a module is pin-to-pin timing. Delays are
assigned individually to paths from each input to each output. Thus, delays can be
separatelyspecified for each input/output path. Pin-to-pin delays are also known as path
delays.
Specify Blocks
A delay between a source (input or inout) pin and a destination (output or inout) pin of
a module is called a module path delay. Path delays are assigned in Verilog within the
keywords specify and endspecify. The statements within these keywords constitute a
specify block.
//Pin-to-pin delays
module M (out, a, b, c, d);
output out;
input a, b, c, d;

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 wire e, f;
//Specify block with path delay statements
specify
(a => out) = 9;
(b => out) = 9;
(c => out) = 11;
(d => out) = 11;
endspecify
//gate instantiations
and a1 (e, a, b);
and a2 (f, c, d);
and a3(out, e, f);
endmodule

The specify block is a separate block in the module and does not appear under any
otherblock, such as initial or always.

Edge-Sensitive Paths
An edge-sensitive path construct is used to model the timing of input to output delays, which
occurs only when a specified edge occurs at the source signal.
In this example, at the positive edge of clock, a module path extends from clock signal to
out signal using a rise delay of 10 and a fall delay of 8. The data path is from in to out, and
the in signal is not inverted as it propagates to the out signal.

(posedge clock => (out +: in)) = (10: 8);

Verilog Gate Delay

Verilog gate delays specify how values propagate through nets or gates. The gate delay
declaration specifies a time needed to propagate a signal change from the gate input to
its output.

Rise, fall, and Turn-Off Delays

The delays declaration can contain up to three values, such as rise, fall, and turn-off delays.
 The time taken for the output of a gate to change from some value to 1 is called a
rise delay.
 The time taken for the output of a gate to change form some value to 0 is called a
fall delay.
 The time taken for the output of a gate to change from some value to high
impedance is called turn-off delay.

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 If only one delay value is specified, then it is used for all signal changes. The default
delay is zero.
If two delays are specified, then the first delay specifies the rise delay, and the second delay
specifies the fall delay.
If three values are given, then the first value specifies the rise delay, the second specifies
the fall delay, and the third specifies the turn-off delay.

// Single delay specified - used for all three types of transition delays
or # (<delay>) o_1 (out, a, b);
// Two delays specified - used for Rise and fall transitions
or # (<rise>, <fall>) o_1 (out, a, b);
// Three delays specified - used for Rise, fall and Turn-off transitions
or # (<rise>, <fall>, <turn_off>) o_1 (out, a, b);

1. One Delay Format

module des (input a, b, output out1, out2);
// AND gate has 2 time unit gate delay
and # (2) o1 (out1, a, b);
// BUFIF0 gate has 3 time unit gate delay
bufif0 #(3) b1 (out2, a, b);
endmodule
Now, See that the output of AND gates change 2 time units after one of its inputs change.

2. Two Delay Format

module des (input a, b, output out1,out2);
and #(2, 3) o1 (out1, a, b);
bufif0 # (4, 5) b1 (out2, a, b);
endmodule

3. Three Delay Format

module des (input a, b, output out1, out2);

and #(2, 3, 4) o1 (out1, a, b);
bufif0 #(5, 6, 7) b1 (out2,a,b);
endmodule

Min, Typ, and Max Delays

Every digital gate and transistor cell has a minimum, typical, and maximum delay

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specified based on process node and is typically provided by libraries from fabrication
foundry.
For rise, fall, and turn-off delays, the three values min, typ, and max can be specified
and stand for minimum, typical and maximum delays.
This is another level of delay control in Verilog. Only one of the min, typ, and max
valuescan be used in the entire simulation run. It is specified at the start of the simulation
and depends on the simulator used. The typ is the default value.
 The min value is the minimum delay value that the gate is expected to have.
 The typ value is the typical delay value that the gate is expected to have.
 The max value is the maximum delay value that the gate is expected to have.

module des (input a, b, output out1, out2);

and #(2:3:4, 3:4:5) o1 (out1, a, b);
bufif0 # (5:6:7, 6:7:8, 7:8:9) b1 (out2, a, b);
endmodule

T. Y. B. Sc. (SEM - V) EL 351: UNIT: 1- INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade

  DATA FLOW MODELING
Dataflow modeling style is mainly used to describe combinational circuits. The basic
mechanism used is the continuous assignment. In a continuous assignment, a value is
assigned to a data type called net.
Dataflow modeling describes hardware in terms of the flow of data from input to output.
Syntax
assign [delay] LHS_net = RHS_expression;

Where LHS_net is a destination net of one or more bit, and RHS_expression is an

expressionconsisting of various operators. The statement is evaluated at any time any
of the source operand value changes and the result is assigned to the destination net after
the delay unit.

For example,
assign out1 = in1 & in2; // perform and function on in1 and in2 and assign the result to
out1assign out2 = ~ in1;
assign #2 z[0] = ~(ABAR & BBAR & EN); //perform the desired function and assign
theresult

For example, to describe an AND gate using dataflow, the code will look something like
this:

module and_gate(A, B, out);

input A, B;
output out;
assign out= A & B;
out= A. B
endmodule

 BEHAVIORAL MODELING
Behavioral modeling is used to describe complex circuits. It is primarily used to model
sequential circuits, but can also be used to model pure combinatorial circuits. The
mechanisms (statements) for modeling the behavior of a design are:
initial Statements
always Statements
A module may contain an arbitrary number of initial or always statements and may
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 containone or more procedural statements within them. They are executed concurrently
(i.e. to model parallelism such that the order in which statements appear in the model
does not matter) with respect to each other whereas the procedural statements are
executed sequentially (i.e. the order in which they appear does matter). Both initial and
always statements are executed at time=0 and then only always statements are executed
during therest of the time.
Syntax

initial [timing_control] procedural_statements;

always [timing_control] procedural_statements;

Where a procedural_statement is one

of:procedural assignment
conditional_statement
case_statement
loop_state
ment
wait_state
ment
The initial statement is non-synthesizable and is normally used in test benches. The
alwaysstatement is synthesizable, and the resulting circuit can be a combinational or
sequential circuit.
In order for the model to generate a combinatorial circuit, the always block
 should not be edge sensitive
 every branch of the conditional statement should define all output
 Every case of case statement should define all output and must have a default case.

 Example for Behavioral modeling:

module mux_2x1(a, b, sel,
out);input a, b, sel;
output out;
always @ (a or b or
sel)begin

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 if (sel ==
1) sel out
out =b; 0 a
1 b
else
out = a;
end
endmodule

 STRUCTURAL STYLE (GATE LEVEL)

 In Verilog, most of the digital designs are done at a higher level of abstraction
like RTL. However, it becomes natural to build smaller deterministic circuits at
a lower level by using combinational elements such as AND and OR.
 Modeling done at this level is called gate-level modeling as it involves gates and
hasa one to one relationship between a hardware schematic and the Verilog code.
 The multiple-input gates are and, nand, or, nor, xor, and xnor whose
number ofinputs are two or more, and has only one output.
 The multiple-output gates are buf and not whose output is one or more and has
onlyone input.
 The language also supports the modeling of tri- state gates, including bufif0,
bufif1,notif0, and notif1. These gates have one input, one control signal, and
one output.

Syntax
Following is the basic syntax for each type of gates with zero delays, such as:

and | nand | or | nor | xor | xnor [instance name] (out, in1, ..., inN); // [ ] is optional
and |is selection

buf | not [instance name] (out1, out2, ..., outN, input);

bufif0 | bufif1 | notif0 | notif1 [instance name] (outputA, inputB, controlC);

 One can also have multiple instances of the same type of gate in one
constructseparated by a comma:

and [inst1] (out11, in11, in12), [inst2] (out21, in21, in22, in23), [inst3] (out31, in31,
in32,in33);

The gate-level modeling is useful when a circuit is a simple combinational, such as a

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 multiplexer, adder, encoder and decoder.

 Half adder Using Structural Style (Gate Level Modelling)

module half_adder (sum, carry, in0, in1);

output sum, carry;

input in0, in1;

// 2-input XOR gate.

xor xor_1 (sum, in0, in1);

sum= in0 in1
// 2-input AND gate. carry= in0 . in1
and and_1 (carry, in0, in1);

endmodule

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
  INTRODUCTION TO LANGUAGE ELEMENTS:

 Identifiers and Keywords

Keywords are special identifiers reserved to define the language constructs. Keywords are
in lowercase.
Identifiers are names given to objects so that they can be referenced in the design.
Identifiers are made up of alphanumeric characters, the underscore (_), or the dollar sign
($). Identifiers are case sensitive. Identifiers start with an alphabetic character or an
underscore. They cannot start with a digit or a $ sign (The $ sign as the first character is
reserved for system tasks.
 reg value; // reg is a keyword; value is an identifier
 input clk; // input is a keyword, clk is an identifier

 White Space Characters:

Blank spaces (\b), tabs (\t) and newlines (\n) comprise the whitespace. Whitespace is
ignored by Verilog except when it separates tokens. Whitespace is not ignored in strings.
Blank space (\b)
Tab (\t)
Newline (\n)

 Comments
Comments can be inserted in the code for readability and documentation. There are two
ways to write comments. A one-line comment starts with "//". Verilog skips from that point
to the end of line. A multiple-line comment starts with "/*" and ends with "*/". Multiple-
line comments cannot be nested. However, one-line comments can be embedded in
multiple-line comments.
a = b && c; //This is a one-line comment
/* This is a multiple line comment
………………….
…………………..*/
/* This is /* an illegal */ comment */
/* This is //a legal comment */

 Format

Sized numbers
 General syntax: <size>’<base><number>

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 <size> number of bits (in decimal)
<number> is the number in radix <base>
<base> :
 d or D for decimal (radix 10)
 b or B for binary (radix 2)
 o or O for octal (radix 8)
 h or H for hexadecimal (radix 16)
Examples:
4’b1111
12’Habc
16’d255
 Negative numbers
Put the sign before the <size>
Examples:
-6’d3 // legal format
4’d-2 // illegal
Two’s complement is used to store the value

 Integer
An integer is a general purpose register data type used for manipulating quantities. Integers
are declared by the keyword integer. Although it is possible to use reg as a general-purpose
variable, it is more convenient to declare an integer variable for purposes such as counting.
The default width for an integer is the host-machine word size, which is implementation-
specific but is at least 32 bits. Registers declared as data type reg store values as unsigned
quantities, whereas integers store values as signed quantities.

integer counter; // general purpose variable used as a counter.

initial
counter = -1; // A negative one is stored in the counter
 Reals
Real number constants and real register data types are declared with the keyword real. They
can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6, which
is 3 x 106). Real numbers cannot have a range declaration, and their default value is 0.
When a real value is assigned to an integer, the real number is rounded off to the nearest
integer.

real delta; // Define a real variable called delta initial

begin
delta = 4e10; // delta is assigned in scientific notation

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 delta = 2.13; // delta is assigned a value 2.13
end
integer i; // Define an integer i initial
i = delta; // i gets the value 2 (rounded value of 2.13)

 Strings
A string is a sequence of characters that are enclosed by double quotes. The restriction on
a string is that it must be contained on a single line, that is, without a carriage return. It
cannot be on multiple lines. Strings are treated as a sequence of one-byte ASCII values.
"Hello Verilog World" // is a string
"a / b" // is a string

 Logic Values

The value set for Verilog is:

0 - represents number zero, logic zero, logical false.
1 - Represents number one, logic one, logical true.
x - Represents an unknown logic value.
z - Represents high impedance logic value most data types can store all four values.

 DATA TYPES:


 NETS TYPES –
Represent connections between hardware components.

a, b, c, & d are nets.

Nets are declared by keyword wire.

Nets represent connections between hardware components.
wire d; // declare output as net d.
wire b, c; // declare two wires in same statement
Nets: The logical value of a net is set by the output of its driver. If there is no driver, the net
value is z.
“Net” is not a keyword -- it is a class of data types.

Other specific types of wires include:

wand (wired-AND); // the value of a wand depend on logical AND of all the drivers
connected to it.

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 wor (wired-OR); // the value of a wor depend on logical OR of all the drivers connected
to it.

tri (three-state); // all drivers connected to a tri must be z, except one (which determines
the value of the tri).

Syntax
wire [msb:lsb] wire_variable_list;

wand [msb:lsb] wand_variable_list;

wor [msb:lsb] wor_variable_list;

tri [msb:lsb] tri_variable_list;

REGISTER- Registers provide data storage. In Verilog, register simply means a

variable that can hold a value. A Verilog register is not the same as a hardware register.
A register does not need a driver. They also do not need a clock like a hardware register
does. Registers are declared by the keyword reg. The default value for a reg data type
is x.
reg start; // declares register “start”
reg reset, clock; // declares registers reset & clock

VECTOR & SCALAR DATA TYPES-

Nets and reg data types can be declared as vectors (multiple-bit data) or as scalars (single-
bit data). If the width of a data variable is not declared, scalar is assumed.
Vector and scalar declarations-
Vectors can be specified by declaring the range of bit numbers with the variable name. The
form of the declaration is:
[<high#> : <low#>] <variable> ;
or [<low#>: <high#>] <variable> ;
Example
wire [7:0] BYTE; // declare 8-bit data.
reg [15:0] INFO; // declare 16-bit register.
reg [0:11] DATA; // declare 12-bit register
Note: The bit numbers can run in either direction but the left-hand number of the pair in
the brackets is always the most significant bit of the vector.

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 When a list of variables is given in a declaration, Verilog assumes that each variable is
sized according to the last size specification seen as that line is scanned. This allows a set
of same-sized vectors to be declared without explicitly specifying the size of each one.

Thus the declaration of 8-bit registers A, B & C can be written as:

reg [7:0] A, B, C;

PARAMETER

Parameters allow constants like word length to be defined symbolically in one place.
This makes it easy to change the word length later, by change only the parameter.

Syntax
parameter par_1 = value,

par_2 = value, ..... ;

parameter [range] parm_3 = value;

Example
parameter add = 2’b00, sub = 3’b111;

parameter n = 4;

parameter [3:0] st4 = 4’b1010;

...

 Expression
An expression calculates a value from a set of operators and operands.

An expression is a construct that combines operands with operators to produce a result

that is a function of the values of the operands and the semantic meaning of the operator.
Alternatively, an expression is any legal operand -- for example, a net bit-select.
Wherever a value is needed in a statement, an expression can be given. However, several
statement constructs limit an expression to a constant expression. A constant expression
consists of constant numbers and predefined parameter names only, but can use any of
the operators defined in "Operators".

For its use in expressions, data type integer shares the same traits as the data type reg.
Descriptions of register usage apply to integers as well.

Syntax:

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 operand | operator operand | operand operator operand

Description:

An expression produce a result from a set of operators and operands.

An operand can be one of the following:

number

net

register, integer

net bit-select

register bit-select

net part-select

register part-select

memory element

a call to a user-defined function that returns any of the above

Operators

The following table summarizes the supported operators:

Operator Type

{ } concatenation

+ - * / arithmetic

% modulus

> >= < <= relational

! logical negation

&& logical and

|| logical or

== logical equality

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 != logical inequality

=== case equality

!== case inequality

~ bit-wise negation

& bit-wise and

| bit-wise inclusive or

^ bit-wise exclusive or

^~ or ~^ bit-wise equivalence

& reduction and

~& reduction nand

| reduction or

~| reduction nor

^ reduction xor

~^ or ^~ reduction xnor

<< shift left

>> shift right

<<< arithmetic shift left

>>> arithmetic shift right

? : conditional

Example:

module half_adder (sum, carry, in0, in1);

output sum, carry;

input in0, in1;

assign sum = in0 ^ in1;

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 assign carry = in0 & in1;

endmodule

 OPERATORS:
Unary ….. a = ~b;

Binary……a = b && c;

Ternary …… a = b? c: d; // the only ternary operator

1. Arithmetic Operators
These perform arithmetic operations. The + and - can be used as either unary (-z) or
binary(x-y) operators.

Operators
+ (addition)

- (subtraction)

* (multiplication)

/ (division)

% (modulus)

2. Relational Operators
Relational operators compare two operands and return a single bit 1or 0. These
operators synthesize into comparators. Wire and reg variables are positive Thus (-
3’b001) = = 3’b111.However for integers -1< 6.

Operators
< (less than)

<= (less than or equal to)

> (greater than)

>= (greater than or equal to)

== (equal to)

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 != (not equal to)

3. Bit-wise Operators
Bit-wise operators do a bit-by-bit comparison between two operands.

Operators
~ (bitwise NOT)

& (bitwise AND)

| (bitwise OR)

^ (bitwise XOR)

~^ or ^~ (bitwise XNOR)

4. Logical Operators
Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only
forsingle bit operands. They can work on expressions, integers or groups of bits, and
treat all values that are nonzero as “1”. Logical operators are typically used in conditional
(if ... else)statements since they work with expressions.

Operators
! (Logical NOT)

&& (logical AND)

|| (logical OR)

5. Reduction Operators
Reduction operators operate on all the bits of an operand vector and return a single-bit
value.These are the unary (one argument) form of the bit-wise operators above.

Operators
& (reduction AND)
| (reduction OR)

~& (reduction NAND)

~| (reduction NOR)

^ (reduction XOR)

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
 ~^ or ^~ (reduction XNOR)

6. Shift Operators
Shift operators shift the first operand by the number of bits specified by the second
operand.Vacated positions are filled with zeros for both left and right shifts (There is
no sign extension).

Operators
<< (shift left)

>> (shift right)

7. Concatenation Operator
The concatenation operator combines two or more operands to form a larger vector.

Operators
{ } (concatenation)

8. Replication Operator
The replication operator makes multiple copies of an item.

Operators
{n{item}} (n fold replication of an item)

9. Conditional Operator: “?”

Conditional operator is like those in C/C++. They evaluate one of the two expressions
basedon a condition. It will synthesize to a multiplexer (MUX).

Operators
(cond) ? (result if cond true): (result if cond false)

Operator Precedence
Table shows the precedence of operators from highest to lowest. Operators on the same
level evaluate from left to right. It is strongly recommended to use parentheses to define
order of precedence and improve the readability of your code.

T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade
T. Y. BSc. (SEM - V) EL 351: Paper I: UNIT 1: INTRODUCTION TO VERILOG, Notes by Mrs. M. E. Niphade