Data Sheet

ADBMS1818
18-Cell Battery Monitor with Daisy Chain Interface

FEATURES TYPICAL APPLICATION CIRCUIT

► Measures up to 18 battery cells in series
► 3 mV maximum total measurement error
► Stackable architecture for high voltage systems
► Built-in isoSPI interface
► 1 Mb isolated serial communications
► Uses a single twisted pair, up to 100 meters
► Low EMI susceptibility and emissions Figure 1. Typical Application Circuit
► Bidirectional for broken wire protection
► 290 µs to measure all cells in a system
► Synchronized voltage and current measurement
► 16-bit Δ-Σ ADC with programmable third-order noise filter
► Passive cell balancing up to 200 mA (maximum) with program-
mable pulse‑width modulation
► 9 general-purpose digital I/O or analog inputs
► Temperature or other sensor inputs
► Configurable as an I2C or SPI master
► 6 µA sleep mode supply current
► 64-lead LQFP_EP package Figure 2. Cell 18 Measurement Error vs. Temperature

APPLICATIONS GENERAL DESCRIPTION

► Backup battery systems The ADBMS18181 is a multicell battery stack monitor that meas-
► Grid energy storage ures up to 18 series connected battery cells with a total measure-
► Residential energy storage ment error (TME) of less than 3.0 mV. The cell measurement range
► UPS of 0 V to 5 V makes the ADBMS1818 suitable for most battery
► High power portable equipment chemistries. All 18 cells can be measured in 290 µs, and lower data
acquisition rates can be selected for high noise reduction.
Multiple ADBMS1818 devices can be connected in series, permit-
ting simultaneous cell monitoring of long, high voltage battery
strings. Each ADBMS1818 has an isoSPI™ interface for high
speed, RF immune, long distance communications. Multiple devi-
ces are connected in a daisy chain with one host processor connec-
tion for all devices. This daisy chain can be operated bidirectionally,
ensuring communication integrity, even in the event of a fault along
the communication path.
The ADBMS1818 can be powered directly from the battery stack or
from an isolated supply. The ADBMS1818 includes passive balanc-
ing for each cell, with individual pulse-width modulation (PWM) duty
cycle control for each cell. Other features include an on-board 5 V
regulator, nine general-purpose I/O lines, and a sleep mode, where
current consumption is reduced to 6 µA.
All registered trademarks and trademarks are the property of their
respective owners.
1 Protected by U.S. patents, including 8,908,779; 9,182,428; and 9,270,133.

Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
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Data Sheet ADBMS1818
TABLE OF CONTENTS

Features................................................................ 1 S Pin Pulse-Width Modulation for Cell

Applications........................................................... 1 Balancing........................................................37
Typical Application Circuit......................................1 Discharge Timer Monitor.................................. 38
General Description...............................................1 I2C/SPI Master on ADBMS1818 Using
Specifications........................................................ 4 GPIOs.............................................................38
ADC DC Specifications...................................... 4 S Pin Pulsing Using the S Pin Control
Voltage Reference Specifications.......................5 Settings.......................................................... 42
General DC Specifications................................. 5 S Pin Muting..................................................... 44
ADC Timing Specifications.................................7 Serial Interface Overview................................. 44
SPI DC Specifications........................................ 7 4-Wire Serial Peripheral Interface (SPI)
IsoSPI DC Specifications................................... 8 Physical Layer................................................ 44
IsoSPI Idle/Wake-Up Specifications...................8 2-Wire Isolated Interface (isoSPI) Physical
IsoSPI Pulse Timing Specifications....................9 Layer.............................................................. 44
SPI Timing Requirements.................................. 9 Data Link Layer................................................ 54
isoSPI Timing Specifications............................ 10 Network Layer.................................................. 54
Absolute Maximum Ratings................................. 11 Memory Map........................................................62
Thermal Resistance..........................................11 Applications Information...................................... 68
Electrostatic Discharge (ESD) Ratings.............11 Providing DC Power......................................... 68
ESD Caution.....................................................11 Internal Protection and Filtering....................... 68
Pin Configuration and Function Descriptions...... 12 Cell Balancing.................................................. 72
Typical Performance Characteristics................... 14 Discharge Control During Cell
Functional Block Diagram....................................20 Measurements................................................74
Improvements from the LTC6811-1..................... 21 Digital Communications....................................75
Theory of Operation.............................................22 Enhanced Applications.....................................83
State Diagram.................................................. 22 Reading External Temperature Probes............ 85
ADBMS1818 Core State Descriptions..............22 Typical Application...............................................86
isoSPI State Descriptions.................................23 Related Devices.................................................. 87
Power Consumption......................................... 23 Outline Dimensions............................................. 88
ADC Operation................................................. 24 Ordering Guide.................................................89
Data Acquisition System Diagnostics...............30 Evaluation Boards............................................ 89
Watchdog and Discharge Timer....................... 36

REVISION HISTORY

12/2021—Rev. 0 to Rev. A
Added 64-Lead LQFP_EP (SW-64-2)..............................................................................................................1
Changes to V+ Supply Current (IVP) Parameter, Table 3................................................................................. 5
Change to Regulator Start-Up Time (tWAKE) Parameter, Table 4..................................................................... 7
Changes to Table 11.......................................................................................................................................11
Added Thermal Resistance Section and Table 12; Renumbered Sequentially..............................................11
Added Electrostatic Discharge (ESD) Ratings Section.................................................................................. 11
Added ESD Ratings for ADBMS1818 and Table 13.......................................................................................11
Changes to Figure 3...................................................................................................................................... 12
Change to Figure 53...................................................................................................................................... 22
Changes to Table 72...................................................................................................................................... 65
Changes to Figure 96.................................................................................................................................... 70
Updated Outline Dimensions......................................................................................................................... 88
Changes to Ordering Guide........................................................................................................................... 89
Added Evaluation Boards.............................................................................................................................. 89

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Data Sheet ADBMS1818
TABLE OF CONTENTS

1/2021—Revision 0: Initial Version

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Data Sheet ADBMS1818
SPECIFICATIONS

Specifications are at TA = 25°C, unless otherwise noted. The test conditions are V+ = 59.4 V and VREG = 5.0 V, unless otherwise noted. The
ISOMD pin is tied to the V– pin, unless otherwise noted.

ADC DC SPECIFICATIONS
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
Measurement Resolution 0.1 mV/Bit
ADC Offset Voltage1 0.1 mV
ADC Gain Error 1 0.01 %
TME in Normal Mode C(n) to C(n–1), GPIO(n) to V– = 0 ±0.2 mV
C(n) to C(n–1) = 2.0 ±2.6 mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, apply over the full specified temperature ±2.8 mV
range
C(n) to C(n–1) = 3.3 ±3.0 mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, apply over the full specified temperature ±4.0 mV
range
C(n) to C(n–1) = 4.2 ±3.8 mV
C(n) to C(n–1), GPIO(n) to V– = 4.2, apply over the full specified temperature ±4.8 mV
range
C(n) to C(n–1), GPIO(n) to V– = 5.0 ±1 mV
Sum of all cells, apply over the full specified temperature range ±0.05 ±0.35 %
Internal temperature, T = maximum specified temperature ±5 °C
VREG pin, apply over the full specified temperature range –1 –0.15 0 %
VREF2 pin, apply over the full specified temperature range –0.05 0.05 0.20 %
Digital supply voltage, VREGD, apply over the full specified temperature range –0.5 0.5 1.5 %
TME in Filtered Mode C(n) to C(n–1), GPIO(n) to V– = 0 ±0.1 mV
C(n) to C(n–1) = 2.0 ±1.6 mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, apply over the full specified temperature ±1.8 mV
range
C(n) to C(n–1) = 3.3 ±2.2 mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, apply over the full specified temperature ±3.0 mV
range
C(n) to C(n–1) = 4.2 ±2.8 mV
C(n) to C(n–1), GPIO(n) to V– = 4.2, apply over the full specified temperature ±3.8 mV
range
C(n) to C(n–1), GPIO(n) to V– = 5.0 ±1 mV
Sum of all cells, apply over the full specified temperature range ±0.05 ±0.35 %
Internal temperature, T = maximum specified temperature ±5 °C
VREG pin, apply over the full specified temperature range –1 –0.15 0 %
VREF2 pin, apply over the full specified temperature range –0.05 0.05 0.20 %
Digital supply voltage, VREGD, apply over the full specified temperature range –0.5 0.8 1.5 %
TME in Fast Mode C(n) to C(n–1), GPIO(n) to V– = 0 ±2 mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, apply over the full specified temperature ±6.5 mV
range
C(n) to C(n–1), GPIO(n) to V– = 3.3, apply over the full specified temperature ±8.5 mV
range
C(n) to C(n–1), GPIO(n) to V– = 4.2, apply over the full specified temperature ±12.5 mV
range
C(n) to C(n–1), GPIO(n) to V– = 5.0 ±10 mV
Sum of all cells, apply over the full specified temperature range ±0.15 ±0.5 %
Internal temperature, T = maximum specified temperature ±5 °C
VREG pin, apply over the full specified temperature range –1.5 –0.15 1 %

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Data Sheet ADBMS1818
SPECIFICATIONS

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
VREF2 pin, apply over the full specified temperature range –0.18 0.05 0.32 %
Digital supply voltage, VREGD, apply over the full specified temperature range –2.5 –0.4 2 %
Input Range C(n), n = 1 to 18, apply over the full specified temperature range C(n–1) C(n–1) V
+5
C0, apply over the full specified temperature range 0 1 V
GPIO(n), n = 1 to 9, apply over the full specified temperature range 0 5 V
Input Leakage Current (IL) When Inputs Are Not C(n), n = 0 to 18, apply over the full specified temperature range 10 ±250 nA
Being Measured
GPIO(n), n = 1 to 9, apply over the full specified temperature range 10 ±250 nA
Input Current When Inputs Are Being Measured C(n), n = 0 to 18 ±1 μA
(State: Core = Measure)
GPIO(n), n = 1 to 9 ±1 μA
Input Current During Open Wire Detection Apply over the full specified temperature range 70 100 130 μA
1 The ADC specifications are guaranteed by the TME specification.

VOLTAGE REFERENCE SPECIFICATIONS

Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
1st Reference Voltage (VREF1) VREF1 pin, no load, apply over the full specified temperature 3.0 3.15 3.3 V
range
1st Reference Voltage Temperature Coefficient VREF1 pin, no load 3 ppm/°C
(TC)
1st Reference Voltage Thermal Hysteresis VREF1 pin, no load 20 ppm
1st Reference Voltage Long Term Drift VREF1 pin, no load 20 ppm/√KHR
2nd Reference Voltage (VREF2) VREF2 pin, no load, apply over the full specified temperature 2.993 3 3.007 V
range
VREF2 pin, 5 kΩ load to V−, apply over the full specified 2.992 3 3.008 V
temperature range
2nd Reference Voltage TC VREF2 pin, no load 10 ppm/°C
2nd Reference Voltage Thermal Hysteresis VREF2 pin, no load 100 ppm
2nd Reference Voltage Long Term Drift VREF2 pin, no load 60 ppm/√KHR

GENERAL DC SPECIFICATIONS
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
V+ Supply Current (IVP) (See Figure 53) State: core = sleep, isoSPI = idle, VREG = 0 V 6.1 11 µA
State: core = sleep, isoSPI = idle, VREG = 0 V , apply over the 6.1 18 µA
full specified temperature range
State: core = sleep, isoSPI = idle, VREG = 5 V 3 5 µA
State: core = sleep, isoSPI = idle, VREG = 5 V , apply over the 3 9 µA
full specified temperature range
State: core = standby 9 14 22 µA
State: core = standby, apply over the full specified 6 14 28 µA
temperature range
State: core = REFUP 0.4 0.55 0.8 mA
State: core = REFUP, apply over the full specified 0.375 0.55 0.825 mA
temperature range
State: core = measure 0.65 0.95 1.35 mA

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Data Sheet ADBMS1818
SPECIFICATIONS

Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
State: core = measure, apply over the full specified 0.6 0.95 1.4 mA
temperature range
VREG Supply Current (IREG(CORE)) (See Figure 53) State: core = sleep, isoSPI = idle, VREG = 5 V 3.1 6 µA
State: core = sleep, isoSPI = idle, VREG = 5 V, apply over the 3.1 9 µA
full specified temperature range
State: core = standby 10 35 60 µA
State: core = standby, apply over the full specified 6 35 65 µA
temperature range
State: core = REFUP 0.4 0.9 1.4 mA
State: core = REFUP, apply over the full specified 0.3 0.9 1.5 mA
temperature range
State: core = measure 14 15 16 mA
State: core = measure, apply over the full specified 13.5 15 16.5 mA
temperature range
Additional VREG Supply Current If isoSPI Is in ISOMD = 0, RB1 + RB2 = 2 kΩ, ready, apply over the full 3.6 4.5 5.2 mA
Ready/Active States (IREG(isoSPI)) specified temperature range
Note: Active State Current Assumes tCLK = 1 µs1 ISOMD = 0, RB1 + RB2 = 2 kΩ, active, apply over the full 5.6 6.8 8.1 mA
specified temperature range
ISOMD = 1, RB1 + RB2 = 2 kΩ, ready, apply over the full 4.0 5.2 6.5 mA
specified temperature range
ISOMD = 1, RB1 + RB2 = 2 kΩ, active, apply over the full 7.0 8.5 10.5 mA
specified temperature range
ISOMD = 0, RB1 + RB2 = 20 kΩ, ready, apply over the full 1.0 1.8 2.4 mA
specified temperature range
ISOMD = 0, RB1 + RB2 = 20 kΩ, active, apply over the full 1.3 2.3 3.3 mA
specified temperature range
ISOMD = 1, RB1 + RB2 = 20 kΩ, ready, apply over the full 1.6 2.5 3.5 mA
specified temperature range
ISOMD = 1, RB1 + RB2 = 20 kΩ, active, apply over the full 1.8 3.1 4.8 mA
specified temperature range
V+ Supply Voltage TME specifications met, apply over the full specified 16 60 90 V
temperature range
V+ to C18 Voltage TME specifications met, apply over the full specified –0.3 V
temperature range
V+ to C12 Voltage TME specifications met, apply over the full specified 40 V
temperature range
C13 Voltage TME specifications met, apply over the full specified 2.5 V
temperature range
C7 Voltage TME specifications met, apply over the full specified 1 V
temperature range
VREG Supply Voltage (VREG) TME supply rejection < 1 mV/V, apply over the full specified 4.5 5 5.5 V
temperature range
DRIVE Output Voltage Sourcing 1 µA 5.4 5.7 5.9 V
Sourcing 1 µA, apply over the full specified temperature 5.2 5.7 6.1 V
range
Sourcing 500 µA, apply over the full specified temperature 5.1 5.7 6.1 V
range
Digital Supply Voltage (VREGD) Apply over the full specified temperature range 2.7 3 3.6 V
Discharge Switch On Resistance VCELL = 3.6 V, apply over the full specified temperature range 4 10 Ω
Thermal Shutdown Temperature 150 °C

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Data Sheet ADBMS1818
SPECIFICATIONS

Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
Watchdog Timer Pin Low (VOL(WDT)) WDT pin sinking 4 mA, apply over the full specified 0.4 V
temperature range
General-Purpose I/O Pin Low (VOL(GPIO)) GPIO pin sinking 4 mA (used as digital output), apply over 0.4 V
the full specified temperature range
1 The active state current is calculated from dc measurements. The active state current is the additional average supply current into VREG when there are continuous 1 MHz
communications on the isoSPI ports with 50% data 1s and 50% data 0s. Slower clock rates reduce the supply current.

ADC TIMING SPECIFICATIONS

Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
(tCYCLE) (See Figure 55, Figure 56, and Figure 58)
Measurement and Calibration Cycle Time When Measure 18 cells, apply over the full specified temperature 2027 2343 2488 µs
Starting from the REFUP State in Normal Mode range
Measure 3 cells, apply over the full specified temperature range 352 407 432 µs
Measure 18 cells and 2 GPIO inputs, apply over the full 2717 3140 3335 µs
specified temperature range
Measurement and Calibration Cycle Time When Measure 18 cells, apply over the full specified temperature 174.2 201.3 213.8 ms
Starting from the REFUP State in Filtered Mode range
Measure 3 cells, apply over the full specified temperature range 29.1 33.6 35.7 ms
Measure 18 cells and 2 GPIO inputs, apply over the full 232.3 268.5 285.1 ms
specified temperature range
Measurement and Calibration Cycle Time When Measure 18 cells, apply over the full specified temperature 970 1121 1191 µs
Starting from the REFUP State in Fast Mode range
Measure 3 cells, apply over the full specified temperature range 176 203 215 µs
Measure 18 cells and 2 GPIO inputs, apply over the full 1307 1511 1605 µs
specified temperature range
Skew Time (tSKEW1). The Time Difference Fast mode, apply over the full specified temperature range 168 194 206 µs
Between Cell 18 and GPIO1 Measurements, Normal mode, apply over the full specified temperature range 470 543 577 µs
Command = ADCVAX (See Figure 58)
Skew Time(tSKEW2). The Time Difference Between Fast mode, apply over the full specified temperature range 202 233 248 µs
Cell 18 and Cell 1 Measurements, Command = Normal mode, apply over the full specified temperature range 580 670 711 µs
ADCV (See Figure 55)
Regulator Start-Up Time (tWAKE) VREG generated from the DRIVE pin (see Figure 93), apply over 200 400 µs
the full specified temperature range
Watchdog or Discharge Timer (tSLEEP) (See Figure DTEN pin = 0 or DCTO, Bits[3:0] = 0000, apply over the full 1.8 2 2.2 sec
87) specified temperature range
DTEN pin = 1 and DCTO, Bits[3:0] ≠ 0000 0.5 120 min
Reference Wake-Up Time (tREFUP (See Figure tREFUP is independent of the number of channels measured and 2.7 3.5 4.4 ms
55)). Added to tCYCLE Time When Starting from the ADC mode, apply over the full specified temperature range
the Standby State. tREFUP = 0 When Starting from
Other States
ADC Clock Frequency (fS) 3.3 MHz

SPI DC SPECIFICATIONS
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
SPI Pin Digital Input Voltage High (VIH(SPI)) CSB, SCK, and SDI pins, apply over the full specified 2.3 V
temperature range

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Data Sheet ADBMS1818
SPECIFICATIONS

Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
SPI Pin Digital Input Voltage Low （VIL(SPI)) CSB, SCK, and SDI pins, apply over the full specified 0.8 V
temperature range
Configuration Pin Digital Input Voltage High ISOMD, DTEN, and GPIO1 to GPIO9 pins, apply over the full 2.7 V
(VIH(CFG)) specified temperature range
Configuration Pin Digital Input Voltage Low ISOMD, DTEN, and GPIO1 to GPIO9 pins, apply over the full 1.2 V
(VIL(CFG)) specified temperature range
Digital Input Current (ILEAK(DIG)) CSB, SCK, SDI, ISOMD, and DTEN pins, apply over the full ±1 μA
specified temperature range
Digital Output Low (VOL(SDO)) SDO pin sinking 1 mA, apply over the full specified temperature 0.3 V
range

ISOSPI DC SPECIFICATIONS
See Figure 78.
Table 6.
Parameter Test Conditions/Comments Min Typ Max Unit
Voltage on IBIAS Pin (VBIAS) Ready/active state, apply over the full specified temperature 1.9 2.0 2.1 V
range
Idle state 0 V
Isolated Interface Bias Current (IB) RBIAS = 2 kΩ to 20 kΩ, apply over the full specified temperature 0.1 1.0 mA
range
Isolated Interface Current Gain (AIB) Transmitter pulse amplitude (VA) = ≤ 1.6 V, IB = 1 mA, apply 18 20 22 mA/mA
over the full specified temperature range
IB = 0.1 mA, apply over the full specified temperature range 18 20 24.5 mA/mA
Transmitter Pulse Amplitude (VA) VA = IPx voltage (VIPx) – IMx voltage (VIMx), apply over the full 1.6 V
specified temperature range
Threshold-Setting Voltage on ICMP Pin (VICMP) Receiver comparator threshold voltage (VTCMP) = receiver 0.2 1.5 V
comparator threshold voltage gain (ATCMP) × VICMP, apply over
the full specified temperature range
Input Leakage Current on ICMP Pin (ILEAK (ICMP)) VICMP = 0 V to VREG, apply over the full specified temperature ±1 µA
range
Leakage Current on IPx and IMx Pins (ILEAK (IPx/ Idle state, VIPx or VIMx, 0 V to VREG, apply over the full specified ±1 µA
IMx)) temperature range
Receiver Comparator Threshold Voltage Gain Receiver common-mode bias (VCM) = VREG/2 to VREG – 0.2 V, 0.4 0.5 0.6 V/V
(ATCMP) VICMP = 0.2 V to 1.5 V, apply over the full specified temperature
range
Receiver Common-Mode Bias (VCM) IPx and IMx not driving (VREG – VICMP/3 – 167 mV) V
Receiver Input Resistance (RIN) Single-ended to the IPA, IMA, IPB, and IMB pins, apply over 26 35 45 kΩ
the full specified temperature range

ISOSPI IDLE/WAKE-UP SPECIFICATIONS

See Figure 87.
Table 7.
Parameter Test Conditions/Comments Min Typ Max Unit
Differential Wake-Up Voltage (VWAKE) Dwell time at VWAKE before wake detection (tDWELL) = 240 ns, 200 mV
apply over the full specified temperature range
tDWELL VWAKE = 200 mV, apply over the full specified temperature 240 ns
range
Start-Up Time After Wake Detection (tREADY) Apply over the full specified temperature range 10 µs
Idle Timeout Duration (tIDLE) Apply over the full specified temperature range 4.3 5.5 6.7 ms

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Data Sheet ADBMS1818
SPECIFICATIONS

ISOSPI PULSE TIMING SPECIFICATIONS

See Figure 83.
Table 8.
Parameter Test Conditions/Comments Min Typ Max Unit
Chip Select Half Pulse Width (t1/2PW(CS)) Transmitter, apply over the full specified temperature range 120 150 180 ns
Chip Select Signal Filter (tFILT(CS)) Receiver, apply over the full specified temperature range 70 90 110 ns
Chip Select Pulse Inversion Delay (tINV(CS)) Transmitter, apply over the full specified temperature range 120 155 190 ns
Chip Select Valid Pulse Window (tWNDW(CS)) Receiver, apply over the full specified temperature range 220 270 330 ns
Data Half Pulse Width (t1/2PW(D)) Transmitter, apply over the full specified temperature range 40 50 60 ns
Data Signal Filter (tFILT(D)) Receiver, apply over the full specified temperature range 10 25 35 ns
Data Pulse Inversion Delay (tINV(D)) Transmitter, apply over the full specified temperature range 40 55 65 ns
Data Valid Pulse Window (tWNDW(D)) Receiver, apply over the full specified temperature range 70 90 110 ns

SPI TIMING REQUIREMENTS

See Figure 77 and Figure 86.
Table 9.
Parameter Test Conditions/Comments Min Typ Max Units
SCK Period (tCLK)1 Apply over the full specified temperature range 1 µs
SDI Setup Time Before SCK Rising Edge (t1) Apply over the full specified temperature range 25 ns
SDI Hold Time After SCK Rising Edge (t2) d Apply over the full specified temperature range 25 ns
SCK Low (t3) tCLK = t3 + t4 ≥ 1 µs, apply over the full specified temperature 200 ns
range
SCK High (t4) tCLK = t3 + t4 ≥ 1 µs, apply over the full specified temperature 200 ns
range
CSB Rising Edge to CSB Falling Edge (t5) Apply over the full specified temperature range 0.65 µs
SCK Rising Edge to CSB Rising Edge (t6) 1 Apply over the full specified temperature range 0.8 µs
CSB Falling Edge to SCK Rising Edge (t7) 1 Apply over the full specified temperature range 1 µs
1 These timing specifications are dependent on the delay through the cable and include allowances for 50 ns of delay in each direction. 50 ns corresponds to 10 m of Category
5 (CAT-5) cable (which has a velocity of propagation of 66% the speed of light). Using longer cables requires derating these specs by the amount of additional delay.

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Data Sheet ADBMS1818
SPECIFICATIONS

ISOSPI TIMING SPECIFICATIONS

See Figure 86.
Table 10.
Parameter Test Conditions/Comments Min Typ Max Units
SCK Falling Edge to SDO Valid (t8)1 Apply over the full specified temperature range 60 ns
SCK Rising Edge to Short ±1 Transmit (t9) Apply over the full specified temperature range 50 ns
CSB Transition to Long ±1 Transmit (t10) Apply over the full specified temperature range 60 ns
CSB Rising Edge to SDO Rising (t11) 1 Apply over the full specified temperature range 200 ns
Data Return Delay (tRTN) Apply over the full specified temperature range 325 375 425 ns
Chip-Select Daisy-Chain Delay (tDSY(CS)) Apply over the full specified temperature range 120 180 ns
Data Daisy-Chain Delay (tDSY(D)) Apply over the full specified temperature range 200 250 300 ns
Data Daisy-Chain Lag (vs. Chip Select) (tLAG) = (tDSY(D) + t1/2PW(D)) – (tDSY(CS) + t1/2PW(CS)), apply over the full 0 35 70 ns
specified temperature range
Chip Select High to Low Pulse Governor (t5(GOV)) Apply over the full specified temperature range 0.6 0.82 µs
Data to Chip-Select Pulse Governor (t6(GOV)) Apply over the full specified temperature range 0.8 1.05 µs
isoSPI Port Reversal Blocking tBLOCK Window Apply over the full specified temperature range 2 10 µs
1 These specifications do not include rise or fall time of SDO. Although fall time (typically 5 ns due to the internal pull-down transistor) is not a concern, the rising edge transition
time (tRISE) is dependent on the pull-up resistance and load capacitance on the SDO pin. The time constant must be chosen such that SDO meets the setup time requirements
of the microcontroller unit (MCU).

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Data Sheet ADBMS1818
ABSOLUTE MAXIMUM RATINGS

Table 11. Stresses at or above those listed under Absolute Maximum Ratings
Parameter Rating may cause permanent damage to the product. This is a stress
Total Supply Voltage, V+ to V– 112.5 V rating only; functional operation of the product at these or any other
Supply Voltage (Relative to C12), V+ to C12 50 V conditions above those indicated in the operational section of this
Input Voltage (Relative to V–)
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
C0 –0.3 V to +6 V
C18 –0.3 V to MIN ( V+ + 5.5 V, 112.5 V) THERMAL RESISTANCE
C(n), S(n) –0.3 V to MIN (8 × n, 112.5 V)
Thermal performance is directly linked to printed circuit board
IPA, IMA, IPB, and IMB –0.3 V to VREG + 0.3 V, ≤ 6 V
(PCB) design and operating environment. Careful attention to PCB
DRIVE –0.3 V to +7 V
thermal design is required.
All Other Pins –0.3 V to +6 V
Voltage Between Inputs θJA is the natural convection junction to ambient thermal resistance
C(n) to C(n–1) and S(n) to C(n–1) –0.3 V to +8 V measured in a one-cubic foot sealed enclosure. θJC is the junction
C18 to C15, C15 to C12, C12 to C9, C9 –0.3 V to +21 V to case thermal resistance.
to C6, C6 to C3, and C3 to C0 Table 12. Thermal Resistance
Current In and Out of Pins
Package Type1 θJA2 θJC Unit
All Pins Except VREG, IPA, IMA, IPB, 10 mA
IMB, C(n), and S(n) 05-08-1982 17 2.5 °C/W
IPA, IMA, IPB, and IMB 30 mA SW-64-2 17 2.5 °C/W
Specified Junction Temperature Range –40°C to +85°C 1 The exposed pad must be connected to the V− plane for proper thermal
Junction Temperature (TJMAX) 150°C
management.
Storage Temperature Range –65°C to +150°C 2 Board layout impacts thermal characteristics such as θJA.

ELECTROSTATIC DISCHARGE (ESD) RATINGS

The following ESD information is provided for handling of ESD-sen-
sitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charged device model (FICDM) and charged device
model (CDM) per ANSI/ESDA/JEDEC JS-002.

ESD Ratings for ADBMS1818

Table 13. ADBMS1818, 64-Lead LQFP_EP
ESD Model Withstand Threshold (V) Class
HBM ±1000 1C
CDM ±750 C2b

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.

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Data Sheet ADBMS1818
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 14. Pin Function Descriptions

Pin No. Mnemonic Description
1 V+ Positive Supply Pin.
2, 4, 6, 8, 10, 12, C0 to C18 Cell Inputs.
14, 16, 18, 20, 22,
24, 26, 28, 30, 32,
34, 36, 38
3, 5, 7, 9, 11, 13, S1 to S18 Balance Inputs/Outputs. 18 internal N-channel metal-oxide semiconductor field effect transistors (MOSFETs) are connected between
15, 17, 19, 21, 23, S(n) and C(n–1) for discharging cells.
25, 27, 29, 31, 33,
35, 37
39 to 47 GPIO1 to GPIO9 General Purpose I/O. GPIO1 to GPIO9 can be used as digital inputs or digital outputs or as analog inputs with a measurement range
from V– to 5 V. GPIO3, GPIO4, and GPIO5 can be used as I2C or SPI ports.
48 VREG 5 V Regulator Input. Bypass with an external 1 μF capacitor.
49 DRIVE Connect the base of an NPN transistor to the DRIVE pin. Connect the collector to V+ and the emitter to VREG.
50 VREF2 Buffered 2nd Reference Voltage for Driving Multiple 10 kΩ Thermistors. Bypass with an external 1 μF capacitor.
51 VREF1 ADC Reference Voltage. Bypass with an external 1 μF capacitor. No dc loads allowed.
52 DTEN Discharge Timer Enable. Connect DTEN to VREG to enable the discharge timer.
53, 54, 61, 62 SDI, SDO, CSB, 4-Wire SPI. Active low chip select (CSB), serial clock (SCK), and serial data in (SDI) are digital inputs. Serial data out (SDO) is an
SCK open drain NMOS output pin. SDO requires a 5 kΩ pull-up resistor.
55 ISOMD Serial Interface Mode. Connecting ISOMD to VREG configures Pin 53, Pin 54, Pin 61, and Pin 62 of the ADBMS1818 for 2-wire isoSPI
mode. Connecting ISOMD to V– configures the ADBMS1818 for 4-wire SPI mode.
56 WDT Watchdog Timer Output Pin. This is an open drain negative metal-oxide semiconductor (NMOS) digital output. WDT can be left
disconnected or connected with a 1 M resistor to VREG. If the ADBMS1818 does not receive a valid command within 2 seconds, the
watchdog timer circuit resets the ADBMS1818 and the WDT pin goes high impedance.
57 IBIAS Isolated Interface Current Bias. Tie IBIAS to V– through a resistor divider to set the interface output current level. When the isoSPI
interface is enabled, the IBIAS pin voltage is 2 V. The IPA and IMA or IPB and IMB output current drive is set to 20 times the current,
IB, sourced from the IBIAS pin.

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Data Sheet ADBMS1818
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 14. Pin Function Descriptions

Pin No. Mnemonic Description
58 ICMP Isolated Interface Comparator Voltage Threshold Set. Tie ICMP to the resistor divider between IBIAS and V– to set the voltage
threshold of the isoSPI receiver comparators. The comparator thresholds are set to half the voltage on the ICMP pin.
59, 60 V– Negative Supply Pins. The V– pins must be shorted together, external to the IC.
61, 62 IMA, IPA Isolated 2-Wire Serial Interface Port A. IMA (negative) and IPA (positive) are a differential input/output pair.
63, 64 IMB, IPB Isolated 2-Wire Serial Interface Port B. IMB (negative) and IPB (positive) are a differential input/output pair.
65 EPAD (V–) Exposed Pad (V–). The exposed pad must be soldered to the PCB.
Table 15. Serial Port Pins
Port ISOMD = VREG ISOMD = V–
Port B IPB IPB
(Pin 57, Pin 58, Pin 63, and Pin 64) IMB IMB
ICMP ICMP
IBIAS IBIAS
Port A NC SDO
(Pin 53, Pin 54, Pin 61, and Pin 62) NC SDI
IPA SCK
IMA CSB

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Data Sheet ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

Figure 4. Measurement Noise vs. Input, Normal Mode Figure 8. Noise Filter Response

Figure 5. Measurement Noise vs. Input, Filtered Mode Figure 9. Measurement Error vs. VREG

Figure 6. Measurement Noise vs. Input, Fast Mode Figure 10. Measurement Error vs. V+

Figure 7. Measurement Error Due to IR Reflow Figure 11. Top Cell Measurement Error vs. V+

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Data Sheet ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 16. VREF1 and VREF2 Power-Up

Figure 12. Measurement Error vs. Common-Mode Voltage

Figure 17. VREG and VDRIVE Power-Up

Figure 13. Measurement Error Due to a VREG AC Disturbance

Figure 18. Typical Wake-Up Pulse Amplitude, VWAKE vs. Wake-Up Dwell Time,
tDWELL
Figure 14. Measurement Error Due to a V+ AC Disturbance (PSRR is Power
Supply Rejection Ratio)

Figure 19. Measurement Error vs. Temperature

Figure 15. Measurement Error Common-Mode Rejection Ratio (CMRR) vs.

Frequency

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Data Sheet ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 20. Measurement Error vs. Input, Normal Mode Figure 24. GPIO Measurement Error vs. Input RC Values

Figure 21. Measurement Error vs. Input, Filtered Mode Figure 25. Measurement Time vs. Temperature

Figure 22. Measurement Error vs. Input, Fast Mode Figure 26. Sleep Supply Current vs. V+

Figure 23. Cell Measurement Error vs. Input RC Values Figure 27. Standby Supply Current vs. V+

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Data Sheet ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 28. REFUP Supply Current vs. V+ Figure 32. VREF2 and VREG Line Regulation

Figure 29. Measure Supply Current vs. V+ Figure 33. VREF2 and V+ Line Regulation

Figure 30. VREF1 vs. Temperature Figure 34. VREF2 Load Regulation (IOUT is Output Current)

Figure 31. VREF2 vs. Temperature Figure 35. VREF2 Change Due to IR Reflow

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Data Sheet ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 36. VDRIVE vs. Temperature Figure 40. Increase in Die Temperature vs. Internal Discharge Current

Figure 37. VDRIVE and V+ Line Regulation Figure 41. Internal Die Temperature Measurement Error vs. Temperature

Figure 38. VDRIVE Load Regulation Figure 42. isoSPI Current (Ready) vs. Temperature

Figure 39. Discharge Switch On Resistance vs. Cell Voltage Figure 43. isoSPI Current (Active) vs. isoSPI Clock Frequency

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Data Sheet ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 44. IBIAS Pin Voltage vs. Temperature Figure 48. isoSPI Driver Common-Mode Voltage (Port A and Port B) vs. Pulse
Amplitude

Figure 45. IBIAS Pin Voltage Load Regulation

Figure 49. isoSPI Comparator Threshold Gain (Port A and Port B) vs.
Receiver Common Mode

Figure 46. isoSPI Driver Current Gain (Port A and Port B) vs. IBIAS Current

Figure 50. isoSPI Comparator Threshold Gain (Port A and Port B) vs. ICMP
Voltage

Figure 47. isoSPI Driver Current Gain (Port A and Port B) vs. Temperature

Figure 51. isoSPI Comparator Threshold Gain (Port A and Port B) vs.
Temperature

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Data Sheet ADBMS1818
FUNCTIONAL BLOCK DIAGRAM

Figure 52. Functional Block Diagram

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Data Sheet ADBMS1818
IMPROVEMENTS FROM THE LTC6811-1

The ADBMS1818 is an evolution of the LTC6811-1 design. Table 16 summarizes the feature changes and additions in the ADBMS1818.

Table 16.
Additional ADBMS1818 Features Benefits Relevant Data Sheet Section(s)
The ADBMS1818 has 3 ADCs operating simultaneously 3 cells can be measured during each conversion cycle. ADC Operation
vs. 2 ADCs on the LTC6811-1.
In addition to the 3 ADC Digital filters, there is a 4th filter Checks that all digital filters are free of faults. ADC Conversion with Digital Redundancy for a
that is used for redundancy. description and PS, Bits[1:0] in Table 27
Measure Cell 7 with ADC1 and ADC2 simultaneously Checks that ADC2 is as accurate as ADC1 and also Overlap Cell Measurement (ADOL Command)
and then measure Cell 13 with ADC2 and ADC3 checks that ADC3 is as accurate as ADC2.
simultaneously using the ADOL command.
A monitoring feature can be enabled during the discharge Improved cell balancing. Discharge Timer Monitor
timer. Cell balancing can be automatically terminated
when cell voltages reach a programmable undervoltage
threshold.
The internal discharge MOSFETs can provide 200 mA Faster cell balancing, especially for low cell voltages. Cell Balancing with Internal MOSFETs
of balancing current (80 mA if the die temperature is
over 85°C). The balancing current is independent of cell
voltage.
The C0 pin voltage is allowed to range between 0 V and 1 C0 does not have to connect directly to V–. ADC DC Specifications
V without affecting the TME.
The mute and unmute commands allow the host to turn off Greater control of timing between S pins. Turning off and S Pin Muting
and turn on the discharge pins (S pins) without overwriting cell measurements.
register values.
Auxiliary measurements have an open-wire diagnostic Improved fault detection. Auxiliary Open Wire Check (AXOW Command)
feature
Four additional GPIO pins have been added for a total of Increased number of temperature or other sensors that Auxiliary (GPIO) Measurements (ADAX Command) and
nine. can be measured. Auxiliary Open Wire Check (AXOW Command)
A daisy chain of ADBMS1818s can operate in both Redundant communication path. Reversible isoSPI
directions (both ports can be a master or slave).

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Data Sheet ADBMS1818
THEORY OF OPERATION

STATE DIAGRAM ADBMS1818 returns to the sleep state. If the discharge timer is
disabled, only the watchdog timer is relevant.
The operation of the ADBMS1818 is divided into two separate
sections: the core circuit and the isoSPI circuit. Both sections have REFUP State
an independent set of operating states, as well as a shutdown
timeout. To reach this state, the REFON bit in Configuration Register Group
A must be set to 1 (using the WRCFGA command, see Table
ADBMS1818 CORE STATE DESCRIPTIONS 52). The ADCs are off. The reference is powered up so that the
ADBMS1818 can initiate ADC conversions more quickly than from
Sleep State the standby state.
The reference and ADCs are powered down. The watchdog timer When a valid ADC command is received, the IC goes to the
(see the Watchdog and Discharge Timer section) has timed out. measure state to begin the conversion. Otherwise, the ADBMS1818
The discharge timer is either disabled or timed out. The supply returns to the standby state when the REFON bit is set to 0, either
currents are reduced to minimum levels. The isoSPI ports are in the manually (using WRCFGA command) or automatically when the
idle state. The DRIVE pin is 0 V. watchdog timer expires (the ADBMS1818 then moves straight into
If a wake-up signal is received (see the Waking Up the Serial the sleep state if both timers are expired).
Interface section), the ADBMS1818 enters the standby state.
Measure State
Standby State The ADBMS1818 performs ADC conversions in the measure state.
The reference and the ADCs are off. The watchdog timer and/or The reference and ADCs are powered up.
the discharge timer is running. The DRIVE pin powers the VREG After ADC conversions complete, the ADBMS1818 transitions to
pin to 5 V through an external transistor. Alternatively, VREG can be either the REFUP or standby state, depending on the REFON bit.
powered by an external supply. Additional ADC conversions can be initiated more quickly by setting
When a valid ADC command is received or the REFON bit is set REFON = 1 to take advantage of the REFUP state.
to 1 in Configuration Register Group A, the IC pauses for tREFUP to Note that non ADC commands do not cause a core state transition.
allow the reference to power up and then enters either the REFUP Only an ADC conversion or diagnostic commands place the core in
or measure state. Otherwise, if no valid commands are received for the measure state.
tSLEEP (when both the watchdog and discharge timer expire), the

Figure 53. ADBMS1818 Operation State Diagram

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Data Sheet ADBMS1818
THEORY OF OPERATION

ISOSPI STATE DESCRIPTIONS POWER CONSUMPTION

The ADBMS1818 has two isoSPI ports (Port A and Port B) for The ADBMS1818 is powered via two pins: V+ and VREG. The V+
daisy-chain communication. input requires voltage greater than or equal to the top cell voltage
minus 0.3 V and provides power to the high voltage elements of
Idle State the core circuits. The VREG input requires 5 V and provides power
to the remaining core circuits and the isoSPI circuitry. The VREG
In the idle state, the isoSPI ports are powered down. input can be powered through an external transistor, driven by the
When isoSPI Port A or Port B receives a wake-up signal (see the regulated DRIVE output pin. Alternatively, VREG can be powered by
Waking Up the Serial Interface section), the isoSPI enters the ready an external supply.
state. This transition happens quickly (within tREADY) if the core is in The power consumption varies according to the operational states.
the standby state. If the core is in the sleep state when the isoSPI Table 17 and Table 18 provide equations to approximate the supply
receives a wake-up signal, the core transitions to the ready state pin currents in each state. The V+ pin current depends only on the
within tWAKE. core state. However, the VREG pin current depends on both the
core state and isoSPI state, and can therefore be divided into two
Ready State components. The isoSPI interface draws current only from the VREG
In the ready state, the isoSPI port(s) are ready for communication. pin.
The serial interface current in the ready state depends on the status IREG = IREG(CORE) + IREG(isoSPI)
of the ISOMD pin and RBIAS = RB1 + RB2 (the external resistors tied
to the IBIAS pin). If there is no activity (that is, no wake-up signal) In the sleep state, the VREG pin draws approximately 3.1 μA if
on Port A or Port B for greater than tIDLE, the ADBMS1818 enters powered by an external supply. Otherwise, the V+ pin supplies the
the idle state. When the serial interface is transmitting or receiving necessary current.
data, the ADBMS1818 enters the active state. Table 17. Core Supply Current
State IVP IREG(CORE)
Active State
Sleep
In the active state, the ADBMS1818 is transmitting and receiving VREG = 0 V 6.1 µA 0 µA
data using one or both of the isoSPI ports. The serial interface VREG = 5 V 3 µA 3.1 µA
consumes maximum power in the active state. The supply current Standby 14 µA 35 µA
increases with clock frequency as the density of isoSPI pulses REFUP 550 µA 900 µA
increases. Measure 950 µA 15 mA
Table 18. isoSPI Supply Current Equations
isoSPI State ISOMD Connection IREG(isoSPI)
Idle Not applicable 0 mA
Ready VREG 2.2 mA + 3 × IB
V− 1.5 mA + 3 × IB
Active VREG Write: 2 . 5mA + 3 + 20 × 100ns
× IB
tCLK
100ns × 1 . 5
Read: 2 . 5mA + 3 + 20 × tCLK × IB

V− 1 . 8mA + 3 + 20 × 100ns
× IB
tCLK

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Data Sheet ADBMS1818
THEORY OF OPERATION

ADC OPERATION referred to as the fast mode. The increase in speed comes from a
reduction in the OSR. This increase results in an increase in noise
There are three ADCs inside the ADBMS1818. The three ADCs and average measurement error.
operate simultaneously when measuring 18 cells. Only one ADC is
used to measure the general-purpose inputs. This section uses the Mode 26 Hz (filtered): In this mode, the ADC digital filter –3 dB
term ADC to refer to one or all ADCs, depending on the operation frequency is lowered to 26 Hz by increasing the OSR. This mode is
being performed. This section refers to ADC1, ADC2, and ADC3 also referred to as the filtered mode due to its low –3 dB frequency.
when it is necessary to distinguish between the three circuits, such The accuracy is similar to the 7 kHz (normal) mode with lower
as in the timing diagrams. noise.
Modes 14 kHz, 3 kHz, 2 kHz, 1 kHz, and 422 Hz: Modes 14 kHz, 3
ADC Modes kHz, 2 kHz, 1 kHz, and 422 Hz provide additional options to set the
The ADCOPT bit (CFGAR0, Bit 0) in Configuration Register Group ADC digital filter –3 dB at 13.5 kHz, 3.4 kHz, 1.7 kHz, 845 Hz, and
A and the mode selection bits, MD, Bits[1:0], in the conversion 422 Hz, respectively. The accuracy of the 14 kHz mode is similar to
command together provide eight modes of operation for the ADC the 27 kHz (fast) mode. The accuracy of the 3 kHz, 2 kHz, 1 kHz,
which correspond to different oversampling ratios (OSRs). The and 422 Hz modes is similar to the 7 kHz (normal) mode.
accuracy and timing of these modes are summarized in Table 19. In The filter bandwidths and the conversion times for these modes
each mode, the ADC first measures the inputs and then performs a are provided in Table 19. If the core is in the standby state,
calibration of each channel. The names of the modes are based on an additional tREFUP time is required to power up the reference
the –3 dB bandwidth of the ADC measurement. before beginning the ADC conversions. The reference can remain
Mode 7 kHz (normal): In this mode, the ADC has high resolution powered up between ADC conversions if the REFON bit in Configu-
and low TME. This mode is considered the normal operating mode ration Register Group A is set to 1 so that the core is in REFUP
because of the optimum combination of speed and accuracy. state after delay tREFUP. The subsequent ADC commands do not
have the tREFUP delay before beginning ADC conversions.
Mode 27 kHz (fast): In this mode, the ADC has maximum through-
put but has some increase in TME. Therefore, this mode is also
Table 19. ADC Filter Bandwidth and Accuracy
TME Specification at 3.3 V, TME Specification at 3.3V, –
Mode –3 dB Filter BW –40 dB Filter BW 25°C 40°C, +85°C
27 kHz (Fast Mode) 27 kHz 84 kHz ±8.5 mV ±8.5 mV
14 kHz 13.5 kHz 42 kHz ±8.5 mV ±8.5 mV
7 kHz (Normal Mode) 6.8 kHz 21 kHz ±3 mV ±4 mV
3 kHz 3.4 kHz 10.5 kHz ±3 mV ±4 mV
2 kHz 1.7 kHz 5.3 kHz ±3 mV ±4 mV
1 kHz 845 Hz 2.6 kHz ±3 mV ±4 mV
422 Hz 422 Hz 1.3 kHz ±3 mV ±4 mV
26 Hz (Filtered Mode) 26 Hz 82 Hz ±2.2 mV ±3.0 mV

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Data Sheet ADBMS1818
THEORY OF OPERATION

ADC Range and Resolution ADC Range vs. Voltage Reference Value
The C inputs and GPIO inputs have the same range and resolution. Typical ADCs have a range that is exactly twice the value of
The ADC inside the ADBMS1818 has an approximate range from the voltage reference, and the ADC measurement error is directly
–0.82 V to +5.73 V. Negative readings are rounded to 0 V. The proportional to the error in the voltage reference. The ADBMS1818
format of the data is a 16-bit unsigned integer where the LSB rep- ADC is not typical.
resents 100 μV. Therefore, a reading of 0x80E8 (33,000 decimal)
indicates a measurement of 3.3 V. The absolute value of VREF1 is trimmed up or down to compensate
for gain errors in the ADC. Therefore, the ADC TME specifications
Δ-Σ ADCs have quantization noise which depends on the input are superior to the VREF1 specifications. For example, the 25°C
voltage, especially at low oversampling ratios, such as in fast mode. specification of the TME when measuring 3.300 V in 7 kHz (normal)
In some of the ADC modes, the quantization noise increases as mode is ±3 mV, and the 25°C specification for VREF1 is 3.150 V ±
the input voltage approaches the upper and lower limits of the ADC 150 mV.
range. For example, the total measurement noise vs. input voltage
in normal and filtered modes is shown in Figure 54. Measuring Cell Voltages (ADCV Command)
The specified range of the ADC is 0 V to 5 V. In Table 20, the preci- The ADCV command initiates the measurement of the battery cell
sion range of the ADC is arbitrarily defined as 0.5 V to 4.5 V. This inputs, Pin C0 through Pin C18. This command has options to
range is where the quantization noise is relatively constant even in select the number of channels to measure and the ADC mode. See
the lower OSR modes (see Figure 54). Table 20 summarizes the the Commands section for the ADCV command format.
total noise in this range for all eight ADC operating modes. Also
shown in Table 20 is the noise free resolution. For example, 14-bit Figure 55 shows the timing of the ADCV command that measures
noise free resolution in normal mode implies that the top 14 bits are all 18 cells. After the receipt of the ADCV command to measure
noise free with a dc input, but that the 15th and 16th LSBs flicker. all 18 cells, ADC1 sequentially measures the bottom 6 cells. ADC2
measures the middle 6 cells and ADC3 measures the top 6 cells.
After the cell measurements complete, each channel is calibrated to
remove any offset errors.
Table 21 shows the conversion times for the ADCV command
measuring all 18 cells. The total conversion time is given by t6C
which indicates the end of the calibration step.
Figure 56 shows the timing of the ADCV command that measures
only 3 cells.

Figure 54. Measurement Noise vs. Input Voltage

Table 20. ADC Range and Resolution
Noise Free
Mode Full Range1 Specified Range Precision Range2 LSB Format Maximum Noise Resolution3
27 kHz (Fast) –0.8192 V to 0 V to 5 V 0.5 V to 4.5 V 100 μV Unsigned 16 bits ±4 mV p-p 10 bits
+5.7344 V
14 kHz –0.8192 V to 0 V to 5 V 0.5 V to 4.5 V 100 μV Unsigned 16 bits ±1 mV p-p 12 bits
+5.7344 V
7 kHz (Normal) –0.8192 V to 0 V to 5 V 0.5 V to 4.5 V 100 μV Unsigned 16 bits ±250 μV p-p 14 bits
+5.7344 V
3 kHz –0.8192 V to 0 V to 5 V 0.5 V to 4.5 V 100 μV Unsigned 16 bits ±150 μV p-p 14 bits
+5.7344 V
2 kHz –0.8192 V to 0 V to 5 V 0.5 V to 4.5 V 100 μV Unsigned 16 bits ±100 μV p-p 15 bits
+5.7344 V
1 kHz –0.8192 V to 0 V to 5 V 0.5 V to 4.5 V 100 μV Unsigned 16 bits ±100 μV p-p 15 bits
+5.7344 V
422 Hz –0.8192 V to 0 V to 5 V 0.5 V to 4.5 V 100 μV Unsigned 16 bits ±100 μV p-p 15 bits
+5.7344 V

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Data Sheet ADBMS1818
THEORY OF OPERATION

Table 20. ADC Range and Resolution

Noise Free
Mode Full Range1 Specified Range Precision Range2 LSB Format Maximum Noise Resolution3
26 Hz (Filtered) –0.8192 V to 0 V to 5 V 0.5 V to 4.5 V 100 μV Unsigned 16 bits ±50 μV p-p 16 bits
+5.7344 V
1 Negative readings are rounded to 0 V.
2 Precision range is the range over which the noise is less than the maximum noise.
3 Noise free resolution is a measure of the noise level within the precision range.

Figure 55. Timing for ADCV Command Measuring all 18 Cells

Table 21. Conversion and Synchronization Times for ADCV Command Measuring All 18 Cells in Different Modes
Conversion Times (μs) Synchronization Time (μs)
Mode t0 t1M t2M t5M t6M t6C tSKEW2
27 kHz 0 58 104 244 291 1,121 233
14 kHz 0 87 163 390 466 1,296 379
7 kHz 0 145 279 681 815 2343 670
3 kHz 0 261 512 1263 1513 3041 1252
2 kHz 0 494 977 2426 2909 4437 2415
1 kHz 0 960 1,908 4753 5702 7230 4742
422 Hz 0 1890 3770 9408 11,287 12,816 9397
26 Hz 0 29,818 59,624 149,044 178,851 201,325 149,033

Figure 56. Timing for ADCV Command Measuring 3 Cells

Table 22 shows the conversion time for the ADCV command measuring only 3 cells. t1C indicates the total conversion time for this command.

Table 22. Conversion Times for ADCV Command Measuring 3 Cells in Different Modes
Conversion Times (μs)
Mode t0 t1M t1C
27 kHz 0 58 203
14 kHz 0 87 232
7 kHz 0 145 407

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Data Sheet ADBMS1818
THEORY OF OPERATION

Table 22. Conversion Times for ADCV Command Measuring 3 Cells in Different Modes
Conversion Times (μs)
Mode t0 t1M t1C
3 kHz 0 261 523
2 kHz 0 494 756
1 kHz 0 960 1221
422 Hz 0 1890 2152
26 Hz 0 29,818 33,570

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Data Sheet ADBMS1818
THEORY OF OPERATION

Undervoltage and Overvoltage Monitoring the ADAX command to measure subsets of the GPIOs and the
2nd reference separately or to measure all nine GPIOs and the
Whenever the C inputs are measured, the results are compared 2nd reference in a single command. See the Commands section
to undervoltage and overvoltage thresholds stored in the memory. for the ADAX command format. All auxiliary measurements are
If the reading of a cell is above the overvoltage limit, a bit in the relative to the V– pin voltage. This command can be used to read
memory is set as a flag. Similarly, measurement results below the external temperatures by connecting temperature sensors to the
undervoltage limit cause a flag to be set. The overvoltage and GPIOs. These sensors can be powered from the 2nd reference,
undervoltage thresholds are stored in Configuration Register Group which is also measured by the ADAX command, resulting in precise
A. The flags are stored in Status Register Group B and Auxiliary ratiometric measurements.
Register Group D.
Figure 57 shows the timing of the ADAX command measuring
Auxiliary (GPIO) Measurements (ADAX all nine GPIOs and the 2nd reference. All 10 measurements are
Command) carried out on ADC1 alone. The 2nd reference is measured after
GPIO5 and before GPIO6.
The ADAX command initiates the measurement of the GPIO inputs.
This command has options to select which GPIO input to measure Table 23 shows the conversion time for the ADAX command meas-
(GPIO1 to GPIO9) and which ADC mode to use. The ADAX uring all nine GPIOs and the 2nd reference. t10C indicates the total
command also measures the 2nd reference. There are options in conversion time.

Figure 57. Timing for ADAX Command Measuring All GPIOs and 2nd Reference

Table 23. Conversion and Synchronization Times for ADAX Command Measuring All GPIOs and 2nd Reference in Different Modes
Conversion Times (μs) Synchronization Time (μs)
Mode t0 t1M t2M t9M t10M t10C tSKEW
27 kHz 0 58 104 431 478 1825 420
14 kHz 0 87 163 693 769 2116 682
7 kHz 0 145 279 1217 1350 3862 1205
3 kHz 0 261 512 2264 2514 5025 2253
2 kHz 0 494 977 4358 4841 7353 4347
1 kHz 0 960 1908 8547 9496 12,007 8536
422 Hz 0 1890 3770 16,926 18,805 21,316 16,915
26 Hz 0 29,818 59,624 268,271 298,078 335,498 268,260

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Data Sheet ADBMS1818
THEORY OF OPERATION

Auxiliary (GPIO) Measurements with Digital fies the synchronization of battery cell voltage and current measure-
Redundancy (ADAXD Command) ments when current sensors are connected to the GPIO1 or GPIO2
inputs. Figure 58 shows the timing of the ADCVAX command. See
The ADAXD command operates similarly to the ADAX command the Commands section for the ADCVAX command format. The
except that an additional diagnostic is performed using digital re- synchronization of the current and voltage measurements, tSKEW1,
dundancy. PS, Bits[1:0] in Configuration Register Group B must be in fast mode is within 194 μs.
set to 0 or 1 during the ADAXD command to enable redundancy.
See the ADC Conversion with Digital Redundancy section. Table 24 shows the conversion and synchronization time for the
ADCVAX command in different modes. The total conversion time
The execution time of the ADAX command and the ADAXD com- for the command is given by t8C.
mand is the same.

Measuring Cell Voltages and GPIOs (ADCVAX

Command)
The ADCVAX command combines 18 cell measurements with 2
GPIO measurements (GPIO1 and GPIO2). This command simpli-

Figure 58. Timing of ADCVAX Command

Table 24. Conversion and Synchronization Times for ADCVAX Command in Different Modes
Conversion Times (μs) Synchronization Time (μs)
Mode t0 t1M t2M t3M t4M t5M t6M t7M t8M t8C tSKEW1
27 kHz 0 58 104 151 205 252 306 352 399 1511 194
14 kHz 0 87 163 238 321 397 480 556 632 1744 310
7 kHz 0 145 279 413 554 688 829 963 1097 3140 543
3 kHz 0 261 512 762 1020 1270 1527 1778 2028 4071 1008
2 kHz 0 494 977 1460 1,950 2433 2924 3407 3890 5933 1939
1 kHz 0 960 1908 2857 3812 4761 5717 6665 7613 9657 3801
422 Hz 0 1890 3770 5649 7536 9415 11,302 13,181 15,061 17,104 7525
26 Hz 0 29,818 59,624 89,431 119,245 149,052 178,866 208,672 238,479 268,450 119,234

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Data Sheet ADBMS1818
THEORY OF OPERATION

DATA ACQUISITION SYSTEM DIAGNOSTICS internal die temperature (ITMP), analog power supply (VA), and
digital power supply (VD). These parameters are described in
The battery monitoring data acquisition system is comprised of the Sum of All Cells Measurement section, Internal Die Temperature
multiplexers, ADCs, 1st reference, digital filters, and memory. To Measurement section, and Power Supply Measurements section.
ensure long term reliable performance, there are several diagnostic All 8 ADC modes described in the ADC Modes section are available
commands that can be used to verify the proper operation of these for these conversions. See the Commands section for the ADSTAT
circuits. command format. Figure 59 shows the timing of the ADSTAT
command measuring all 4 internal device parameters.
Measuring Internal Device Parameters
(ADSTAT Command) Table 25 shows the conversion time of the ADSTAT command
measuring all 4 internal parameters. t4C indicates the total conver-
The ADSTAT command is a diagnostic command that measures sion time for the ADSTAT command.
the following internal device parameters: Sum of all cells (SC),

Figure 59. Timing for ADSTAT Command Measuring SC, ITMP, VA, and VD

Table 25. Conversion and Synchronization Times for ADSTAT Command Measuring SC, ITMP, VA, and VD in Different Modes
Conversion Times (μs) Synchronization Time (μs)
Mode t0 t1M t2M t3M t4M t4C tSKEW
27 kHz 0 58 104 151 198 742 140
14 kHz 0 87 163 238 314 858 227
7 kHz 0 145 279 413 547 1556 402
3 kHz 0 261 512 762 1012 2022 751
2 kHz 0 494 977 1460 1943 2953 1449
1 kHz 0 960 1908 2857 3805 4814 2845
422 Hz 0 1890 3770 5649 7529 8538 5638
26 Hz 0 29,818 59,624 89,431 119,238 134,211 89,420

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Sum of All Cells Measurement fourth digital integration and differentiation machine that is used for
redundancy and error checking.
The sum of all cells (SC) measurement is the voltage between C18
and C0 with a 30:1 attenuation. The 16-bit ADC value of sum of All of the ADC and self test commands, except ADAX and ADSTAT,
all cells measurement is stored in Status Register Group A. Any can operate with digital redundancy. This includes ADCV, ADOW,
potential difference between the C0 and V– pins results in an error CVST, ADOL, ADAXD, AXOW, AXST, ADSTATD, STATST, ADC-
in the SC measurement equal to this difference. From the SC value, VAX, and ADCVSC. When performing an ADC conversion with
the sum of all cell voltage measurements is given by: redundancy, the analog modulator sends its bit stream to both
the primary digital machine and the redundant digital machine. At
Sum of all cells = SC × 30 × 100 µV the end of the conversion, the results from the two machines are
compared. If any mismatch occurs, a value of 0xFF0X (≥6.528 V)
Internal Die Temperature Measurement
is written to the result register. This value is outside of the clamping
The ADSTAT command can measure the internal die temperature range of the ADC and the host identifies this as a fault indication.
(ITMP). The 16-bit ADC value of the ITMP is stored in Status Regis- The last four bits are used to indicate which nibble(s) of the result
ter Group A. From ITMP, the actual die temperature is calculated values did not match.
using the expression: Table 26. Indication of Digital Redundancy Fault Bit Location
Internal Die Temperature (°C) = Result Indication
100μV 0b1111_1111_0000_0XXX No fault detected in Bit 15 to Bit 12
ITMP × 7 . 6mV 0b1111_1111_0000_1XXX Fault detected in Bit 15 to Bit 12
°C - 276°C 0b1111_1111_0000_X0XX No fault detected in Bit 11 to Bit 8
0b1111_1111_0000_X1XX Fault detected in Bit 11 to Bit 8
Power Supply Measurements
0b1111_1111_0000_XX0X No fault detected in Bit 7 to Bit 4
The ADSTAT command is also used to measure the analog power 0b1111_1111_0000_XX1X Fault detected in Bit 7 to Bit 4
supply (VREG) and digital power supply (VREGD). The 16-bit ADC 0b1111_1111_0000_XXX0 No fault detected in Bit 3 to Bit 0
value of the analog power supply measurement (VA) is stored in 0b1111_1111_0000_XXX1 Fault detected in Bit 3 to Bit 0
Status Register Group A. The 16-bit ADC value of the digital power
supply measurement (VD) is stored in Status Register Group B. Because there is a single redundant digital machine, the machine
From VA and VD, the power supply measurements are given by: can apply redundancy to only one ADC at a time. By default,
the ADBMS1818 automatically selects the ADC path redundancy.
Analog power supply measurement (VREG) = VA × 100 µV However, the user can choose an ADC redundancy path selection
Digital power supply measurement (VREGD) = VD × 100 µV by writing to the PS, Bits[1:0] in Configuration Register Group B.

The value of VREG is determined by external components. VREG Table 27 shows all possible ADC path redundancy selections.
must be between 4.5 V and 5.5 V to maintain accuracy. The value When the FDRF bit in Configuration Register Group B is written to
of VREGD is determined by internal components. The normal range 1, this bit forces the digital redundancy comparison to fail during
of VREGD is 2.7 V to 3.6 V. subsequent ADC conversions.

Measuring Internal Device Parameters with Measuring Cell Voltages and Sum of All Cells
Digital Redundancy (ADSTATD Command) (ADCVSC Command)
The ADSTATD command operates similarly to the ADSTAT com- The ADCVSC command combines 18 cell measurements and
mand except that an additional diagnostic is performed using digital the sum of all cells measurement. This command simplifies the
redundancy. PS, Bits[1:0] in Configuration Register Group B must synchronization of the individual battery cell voltage and the total
be set to 0 or 1 during the ADSTATD command to enable redun- sum of all cells measurements. Figure 60 shows the timing of the
dancy. See the ADC Conversion with Digital Redundancy section. ADCVSC command. See the Commands section for the ADCVSC
The execution time of the ADSTAT command and the ADSTATD command format. The synchronization of the cell voltage and sum
command is the same. of all cells measurements, tSKEW, in fast mode is within 147 μs.
Table 28 shows the conversion and synchronization time for the
ADC Conversion with Digital Redundancy ADCVSC command in different modes. The total conversion time
for the command is given by t7C.
Each of the three internal ADCs contains its own digital integra-
tion and differentiation machine. The ADBMS1818 also contains a

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Data Sheet ADBMS1818
THEORY OF OPERATION

Table 27. ADC Path Redundancy Selection

PS, Bits[1:0] = 00 PS, Bits[1:0] = 01 PS, Bits[1:0] = 10 PS, Bits[1:0] = 11
Redundant Redundant Redundant Redundant
Measure Path Select Measure Path Select Measure Path Select Measure Path Select Measure
Cells 1, 7, 13 ADC1 Cell 1 ADC1 Cell 1 ADC2 Cell 7 ADC3 Cell 13
Cells 2, 8, 14 ADC2 Cell 8 ADC1 Cell 2 ADC2 Cell 8 ADC3 Cell 14
Cells 3, 9, 15 ADC3 Cell 15 ADC1 Cell 3 ADC2 Cell 9 ADC3 Cell 15
Cells 4, 10, 16 ADC1 Cell 4 ADC1 Cell 4 ADC2 Cell 10 ADC3 Cell 16
Cells 5, 11, 17 ADC2 Cell 11 ADC1 Cell 5 ADC2 Cell 11 ADC3 Cell 17
Cells 6, 12, 18 ADC3 Cell 18 ADC1 Cell 6 ADC2 Cell 12 ADC3 Cell 18
Cell 7 (ADOL) ADC2 Cell 7 ADC1 Cell 7 ADC2 Cell 7 ADC3 N/A 1
Cell 13 (ADOL) ADC2 Cell 13 ADC1 N/A1 ADC2 Cell 13 ADC3 Cell 13
GPIO[n]2 ADC1 GPIO[n] ADC1 GPIO[n] ADC2 N/A1 ADC3 N/A1
2nd Reference2 ADC1 2nd Reference ADC1 2nd Reference ADC2 N/A1 ADC3 N/A1
SC2 ADC1 SC ADC1 SC ADC2 N/A1 ADC3 N/A1
ITMP2 ADC1 ITMP ADC1 ITMP ADC2 N/A1 ADC3 N/A1
VA2 ADC1 VA ADC1 VA ADC2 N/A1 ADC3 N/A1
VD 2 ADC1 VD ADC1 VD ADC2 N/A1 ADC3 N/A1
1 N/A means not applicable.
2 Note that the ADAX and ADSTAT commands are identical to the ADAXD and ADSTATD commands except that ADAX and ADSTAT do not apply any digital redundancy.

Figure 60. Timing of ADCVSC Command Measuring All 19 Cells, SC

Table 28. Conversion and Synchronization Times for ADCVSC Command in Different Modes
Synchronization
Conversion Times (μs) Time (μs)
Mode t0 t1M t2M t3M t4M t5M t6M t7M t7C tSKEW
27 0 58 104 151 205 259 306 352 1331 147
kHz
14 0 87 163 238 321 404 480 556 1534 235
kHz
7 kHz 0 145 279 413 554 695 829 963 2756 409
3 kHz 0 261 512 762 1020 1277 1527 1778 3571 758
2 kHz 0 494 977 1460 1950 2441 2924 3407 5200 1456
1 kHz 0 960 1908 2857 3812 4768 5717 6665 8458 2853
422 0 1890 3770 5649 7536 9423 11,302 13,181 14,974 5645
Hz
26 Hz 0 29,818 59,624 89,431 119,245 149,059 178,866 208,672 234,902 89,427

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Data Sheet ADBMS1818
THEORY OF OPERATION

Overlap Cell Measurement (ADOL Command) Table 29. Conversion Times for ADOL Command
Conversion Times (μs)
The ADOL command first simultaneously measures Cell 7 with
ADC1 and ADC2. Then, the ADOL command simultaneously meas- Mode t0 t1M t2M t2C
ures Cell 13 with both ADC2 and ADC3. The host can compare 3 kHz 0 262 513 1024
the results against each other to look for inconsistencies that may 2 kHz 0 495 979 1490
indicate a fault. The result of the Cell 7 measurement from ADC2 1 kHz 0 960 1910 2420
is placed in Cell Voltage Register Group C where the Cell 7 result 422 Hz 0 1891 3772 4282
normally resides. The result from ADC1 is placed in Cell Voltage 26 Hz 0 29,818 59,626 67,119
Register Group C where the Cell 8 result normally resides. The
result of the Cell 13 measurement from ADC3 is placed in Cell Digital Filter Check
Voltage Register Group E where the Cell 13 result normally resides.
The result from ADC2 is placed in Cell Voltage Register Group E The Δ-Σ ADC is composed of a 1-bit pulse density modulator
where the Cell 14 result normally resides. Figure 61 shows the followed by a digital filter. A pulse density modulated bit stream has
timing of the ADOL command. See the Commands section for the a higher percentage of 1s for higher analog input voltages. The
ADOL command format. digital filter converts this high frequency 1-bit stream into a single
16-bit word.
This is why a Δ-Σ ADC is often referred to as an oversampling
converter.
The self test commands verify the operation of the digital filters
and memory. Figure 62 shows the operation of the ADC during self
test. The output of the 1-bit pulse density modulator is replaced by
a 1-bit test signal. The test signal passes through the digital filter
and is converted to a 16-bit value. The 1-bit test signal undergoes
Figure 61. Timing for ADOL Command the same digital conversion as the regular 1-bit signal from the
modulator, so the conversion time for any self test command is
Table 29 shows the conversion time for the ADOL command. t2C exactly the same as the corresponding regular ADC conversion
indicates the total conversion time for this command. command. The 16-bit ADC value is stored in the same register
Table 29. Conversion Times for ADOL Command groups as the corresponding regular ADC conversion command.
Conversion Times (μs) The test signals are designed to place alternating one-zero patterns
Mode t0 t1M t2M t2C
in the registers. Table 30 provides a list of the self test commands.
If the digital filters and memory are working properly, then the
27 kHz 0 58 106 384 registers contain the values shown in Table 30. For more details
14 kHz 0 87 164 442 see the Commands section.
7 kHz 0 146 281 791

Figure 62. Operation of ADBMS1818 ADC Self Test

Table 30. Self Test Command Summary

Output Pattern in Different ADC Modes
Command Self Test Option 27 kHz 14 kHz 7 kHz, 3 kHz, 2 kHz, 1 kHz, 422 Hz, 26 Hz Results Register Groups
CVST ST, Bits[1:0] = 01 0x9565 0x9553 0x9555 C1V to C18V (CVA, CVB, CVC, CVD, CVE, CVF)
ST, Bits[1:0] = 10 0x6A9A 0x6AAC 0x6AAA
AXST ST, Bits[1:0] = 01 0x9565 0x9553 0x9555 G1V to GV9, REF (AUXA, AUXB, AUXC, AUXD)
ST, Bits[1:0] = 10 0x6A9A 0x6AAC 0x6AAA

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Data Sheet ADBMS1818
THEORY OF OPERATION

Table 30. Self Test Command Summary

Output Pattern in Different ADC Modes
Command Self Test Option 27 kHz 14 kHz 7 kHz, 3 kHz, 2 kHz, 1 kHz, 422 Hz, 26 Hz Results Register Groups
STATST ST, Bits[1:0] = 01 0x9565 0x9553 0x9555 SC, ITMP, VA, VD (STATA, STATB)
ST, Bits[1:0] = 10 0x6A9A 0x6AAC 0x6AAA

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Data Sheet ADBMS1818
THEORY OF OPERATION

Accuracy Check performs ADC conversions on the C pin inputs identically to the
ADCV command, except for two internal current sources sink or
Measuring an independent voltage reference is the optimal source current into the two C pins while they are being measured.
means to verify the accuracy of a data acquisition system. The The pull-up (PUP) bit of the ADOW command determines whether
ADBMS1818 contains a 2nd reference for this purpose. The ADAX the current sources are sinking or sourcing 100 μA.
command initiates the measurement of the 2nd reference. The
results are placed in Auxiliary Register Group B. The range of The following simple algorithm can be used to check for an open
the result depends on the ADC1 measurement accuracy and the wire on any of the 19 C pins:
accuracy of the 2nd reference, including thermal hysteresis and 1. Run the 18-cell command ADOW with PUP = 1 at least twice.
long term drift. Readings outside the 2.992 V to 3.012 V range Read the cell voltages for cells 1 through 18 once at the end
indicate the system is out of its specified tolerance. ADC2 is verified and store them in array CELLPU(n).
by comparing it to ADC1 using the ADOL command. ADC3 is
verified by comparing it to ADC2 using the ADOL command. 2. Run the 18-cell command ADOW with PUP = 0 at least twice.
Read the cell voltages for cells 1 through 18 once at the end
and store them in array CELLPD(n).
Mux Decoder Check
3. Take the difference between the pull-up and pull-down meas-
The diagnostic command DIAGN ensures the proper operation urements made in Step 1 and Step 2 for cells 2 to 18: CELL∆(n)
of each multiplexer channel. The command cycles through all = CELLPU(n) – CELLPD(n).
channels and sets the MUXFAIL bit to 1 in Status Register Group 4. For all values of n from 1 to 17: If CELL∆(n+1) < –400 mV,
B if any channel decoder fails. The MUXFAIL bit is set to 0 if the then C(n) is open. If CELLPU(1) = 0.0000, then C(0) is open. If
channel decoder passes the test. The MUXFAIL bit is also set to 1 CELLPD(18) = 0.0000, then C(18) is open.
on a power-on reset (POR) or after a CLRSTAT command.
The above algorithm detects open wires using normal mode con-
The DIAGN command takes approximately 400 μs to complete if versions with as much as 10 nF of capacitance remaining on the
the core is in the REFUP state and about 4.5 ms to complete if the ADBMS1818 side of the open wire. However, if more external
core is in the standby state. The polling methods described in the capacitance is on the open C pin, then the length of time that
Polling Methods section can be used to determine the completion of the open wire conversions run in Step 1 and Step 2 must be
the DIAGN command. increased to give the 100 μA current sources time to create a large
enough difference for the algorithm to detect an open connection.
ADC Clear Commands This action can be accomplished by running more than two ADOW
commands in Step 1 and Step 2, or by using filtered mode conver-
ADBMS1818 has 3 clear ADC commands: CLRCELL, CLRAUX,
sions instead of normal mode conversions. Refer to Table 31 to
and CLRSTAT. These commands clear the registers that store all
determine how many conversions are necessary.
ADC conversion results.
Table 31. Number of ADOW Commands Required
The CLRCELL command clears Cell Voltage Register Groups A, B,
Number of ADOW Commands Required in Step 1
C, D, E, and F. All bytes in these registers are set to 0xFF by the
External C Pin and Step 2
CLRCELL command.
Capacitance Normal Mode Filtered Mode
The CLRAUX command clears Auxiliary Register Groups A, B, C, ≤10 nF 2 2
and D. All bytes in these registers, except the last four registers of
100 nF 10 2
Group D, are set to 0xFF by the CLRAUX command.
1 μF 100 2
The CLRSTAT command clears Status Register Groups A and C 1 + ROUNDUP (C/10 nF) 2
B, except for the REV and RSVD bits in Status Register Group
B. A read back of the REV bits returns the revision code of the Auxiliary Open Wire Check (AXOW Command)
part. RSVD bits always read back 0s. All overvoltage (OV) and
undervoltage (UV) flags, MUXFAIL bit, and THSD bit in Status The AXOW command is used to check for any open wires between
Register Group B and Auxiliary Register Group D are set to 1 the GPIO pins of the ADBMS1818 and the external circuit. This
by the CLRSTAT command. The THSD bit is set to 0 after the command performs ADC conversions on the GPIO pin inputs identi-
RDSTATB command. The registers storing SC, ITMP, VA, and VD cally to the ADAX command, except internal current sources sink or
are all set to 0xFF by the CLRSTAT command. source current into each GPIO pin while it is being measured. The
pull-up (PUP) bit of the AXOW command determines whether the
Open Wire Check (ADOW Command) current sources are sinking or sourcing 100 μA.

The ADOW command is used to check for any open wires between
the ADCs of the ADBMS1818 and the external cells. This command

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Data Sheet ADBMS1818
THEORY OF OPERATION

Thermal Shutdown WATCHDOG AND DISCHARGE TIMER

To protect the ADBMS1818 from overheating, there is a thermal When there is no valid command for more than 2 seconds, the
shutdown circuit included inside the IC. If the temperature detected watchdog timer expires, which resets the configuration register
on the die rises above approximately 150°C, the thermal shutdown bytes CFGAR0-3 and the GPIO bits in Configuration Register
circuit trips and resets the configuration register groups and S Group B in all cases. CFGAR4, CFGAR5, the S Control Register
Control Register Group (including S control bits in PWM/S Control Group (including S control bits in PWM/S Control Register Group
Register Group B) to their default states and turns off all discharge B) and the remainder of Configuration Register Group B are reset
switches. When a thermal shutdown event has occurred, the THSD by the watchdog timer when the discharge timer is disabled. The
bit in Status Register Group B goes high. The CLRSTAT command WDT pin is pulled high by the external pull-up when the watchdog
can also set the THSD bit high for diagnostic purposes. This bit time elapses. The watchdog timer is always enabled, and the timer
is cleared when a read operation is performed on Status Register resets after every valid command with matching command PEC.
Group B (RDSTATB command). The CLRSTAT command sets the
THSD bit high for diagnostic purposes but does not reset the The discharge timer is used to keep the discharge switches turned
configuration register groups. on for programmable time duration. If the discharge timer is being
used, the discharge switches are not turned off when the watchdog
timer is activated.
Revision Code
To enable the discharge timer, connect the DTEN pin to VREG (see
The Status Register Group B contains a 4-bit revision code (REV). Figure 63). In this configuration, the discharge switches remain on
If software detection of the device revision is necessary, contact for the programmed time duration that is determined by the DCTO
the factory for details. Otherwise, ignore the code. In all cases, value written in Configuration Register Group A. Table 33 shows the
however, the values of all bits must be used when calculating the various time settings and the corresponding DCTO value.
packet error code (PEC) on data reads.

Figure 63. Watchdog and Discharge Timer

Table 32. DCTO Settings

DCTO 0 1 2 3 4 5 6 7 8 9 A B C D E F
Time Disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120
(Minutes)

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Data Sheet ADBMS1818
THEORY OF OPERATION

Table 33. Discharge Timer Settings and CFGAR5 and CFGBR0 and CFGBR1 may be corrupted. If the
Watchdog Timer Discharge Timer discharge timer activates in the middle of a RDSCTRL or RDPSB
DTEN = 0, DCTO = XXXX Resets CFGAR0-5, Disabled command, the S Control Register Group (including S control bits in
CFGBR0-1 and SCTRL PWM/S Control Register Group B) resets, as per Table 33. As a
when it fires result, the read back data may be corrupted.
DTEN = 1, DCTO = 0000 Resets CFGAR0-5, Disabled
CFGBR0-1 and SCTRL
S PIN PULSE-WIDTH MODULATION FOR CELL
when it fires BALANCING
DTEN = 1, DCTO != 0000 Resets CFGAR0-3 and Resets CFGAR4-5, For additional control of cell discharging, the host may configure
GPIO Bits in CFGBR0 SCTRL, and remainder of
the S pins to operate using PWM. While the watchdog timer is
when it fires CFGBR0-1 when it fires
not expired, the DCC bits in the configuration register groups
Table 33 summarizes the status of the configuration register groups control the S pins directly. After the watchdog timer expires, PWM
after a watchdog timer or discharge timer event. The status of operation begins and continues for the remainder of the selected
the discharge timer can be determined by reading Configuration discharge time or until a wake-up event occurs (and the watchdog
Register Group A using the RDCFGA command. The DCTO value timer is reset). During PWM operation, the DCC bits must be set to
indicates the time left before the discharge timer expires, as shown 1 for the PWM feature to operate.
in Table 34. Once PWM operation begins, the configurations in the PWM regis-
Table 34. Status of the Discharge Timer ter can cause some or all S pins to be periodically deasserted to
DCTO (Read Value) Discharge Timer Left (Minutes) achieve the desired duty cycle as shown in Table 35. Each PWM
0 Disabled (or) timer has timed out
signal operates on a 30 second period. For each cycle, the duty
cycle can be programmed from 0% to 100% in increments of 1/15 =
1 0 < timer ≤ 0.5
6.67% (2 seconds).
2 0.5 < timer ≤ 1
3 1 < timer ≤ 2 Each S pin PWM signal is sequenced at different intervals to ensure
4 2 < timer ≤ 3 that no two pins switch on or off at the same time. The switching
5 3 < timer ≤ 4 interval between channels is 62.5 ms, and 1.125 sec is required for
6 4 < timer ≤ 5 all 18 pins to switch (18 × 62.5 ms).
7 5 < timer ≤ 10 Table 35. S Pin Pulse-Width Modulation Settings
8 10 < timer ≤ 15 DCC Bit
9 15 < timer ≤ 20 (Configuration
A 20 < timer ≤ 30 Register PWMC On Time Off Time Duty Cycle
B 30 < timer ≤ 40 Groups) Setting (sec) (sec) (%)
C 40 < timer ≤ 60 0 4’bXXXX 0 Continuously 0
D 60 < timer ≤ 75 Off
E 75 < timer ≤ 90 1 4’b1111 Continuously 0 100.0
On
F 90 < timer ≤ 120
1 4’b1110 28 2 93.3
Unlike the watchdog timer, the discharge timer does not reset 1 4’b1101 26 4 86.7
when there is a valid command. The discharge timer can only be 1 4’b1100 24 6 80.0
reset after a valid WRCFGA (Write Configuration Register Group A) 1 4’b1011 22 8 73.3
command. There is a possibility that the discharge timer expires in 1 4’b1010 20 10 66.7
the middle of some commands. 1 4’b1001 18 12 60.0
If the discharge timer activates in the middle of a WRCFGA com- 1 4’b1000 16 14 53.3
mand, the configuration register groups and S Control Register 1 4’b0111 14 16 46.7
Group (including S control bits in PWM/S Control Register Group B) 1 4’b0110 12 18 40.0
reset as per Table 33. However, at the end of the valid WRCFGA 1 4’b0101 10 20 33.3
command, the new data is copied to Configuration Register Group 1 4’b0100 8 22 26.7
A. The new configuration data is not lost when the discharge timer 1 4’b0011 6 24 20.0
is activated. 1 4’b0010 4 26 13.3
If the discharge timer activates in the middle of a RDCFGA or 1 4’b0001 2 28 6.7
RDCFGB command, the configuration register groups reset as per 1 4’b0000 0 Continuously 0
Table 33. As a result, the read back data from bytes CFGAR4 Off

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Data Sheet ADBMS1818
THEORY OF OPERATION

The default values of the PWM control settings (located in PWM and SCKM ports of the SPI, respectively. The SPI master on the
Register Group and PWM/S Control Register Group B) are all 1s. ADBMS1818 supports SPI Mode 3 (CHPA = 1 and CPOL = 1).
Upon entering sleep mode, the PWM control settings are initialized
to their default values. The GPIOs are open-drain outputs, so an external pull-up is re-
quired on these ports to operate as an I2C or SPI master. It is also
DISCHARGE TIMER MONITOR important to write the GPIO bits to 1 in the configuration register
groups so these ports are not pulled low internally by the device.
The ADBMS1818 has the ability to periodically monitor cell voltages
while the discharge timer is active. The host writes the DTMEN bit COMM Register
in Configuration Register Group B to 1 to enable this feature.
ADBMS1818 has a 6-byte COMM register, as shown in Table 36.
When the discharge timer monitor is enabled and the watchdog This register stores all data and control bits required for I2C or
timer has expired, the ADBMS1818 performs a conversion of all cell SPI communication to a slave. The COMM register contains three
voltages in 7 kHz (normal) mode every 30 seconds. The overvolt- bytes of data Dn, Bits[7:0] to be transmitted to or received from
age and undervoltage comparisons are performed and flags are set the slave device. ICOMn, Bits[3:0] specify control actions before
if cells have crossed a threshold. For any undervoltage cells, the transmitting/receiving each data byte. FCOMn, Bits[3:0] specify
discharge timer monitor automatically clears the associated DCC bit control actions after transmitting/receiving each data byte.
in Configuration Register Group A or Configuration Register Group
B so that the cell is no longer discharged. Clearing the DCC bit also If ICOMn, Bit 3 in the COMM register is set to 1, the device
disables PWM discharge. With this feature, the host can write the becomes an SPI master, and if the bit is set to 0, the device
undervoltage threshold to the desired discharge level and use the becomes an I2C master.
discharge timer monitor to discharge all, or selected, cells (using
either constant discharge or PWM discharge) down to that level. Table 37 describes the valid write codes for ICOMn, Bits[3:0] and
FCOMn, Bits[3:0] and their behavior when using the device as an
During discharge timer monitoring, digital redundancy checking is I2C master.
performed on the cell voltage measurements. If a digital redundan-
cy failure occurs, all DCC bits are cleared. Table 38 describes the valid write codes for ICOMn, Bits[3:0] and
FCOMn, Bits[3:0] and their behavior when using the device as an
I2C/SPI MASTER ON ADBMS1818 USING SPI master.
GPIOS Note that only the codes listed in Table 37 and Table 38 are valid
The I/O ports GPIO3, GPIO4, and GPIO5 on the ADBMS1818 can for ICOMn, Bits[3:0] and FCOMn, Bits[3:0]. Writing any other code
be used as an I2C or SPI master port to communicate to an I 2C or that is not listed in Table 37 and Table 38 to ICOMn, Bits[3:0] and
SPI slave. In the case of an I2C master, GPIO4 and GPIO5 form the FCOMn, Bits[3:0] may result in unexpected behavior on the I2C or
SDA and SCL ports of the I2C interface, respectively. In the case of SPI port.
an SPI master, GPIO3, GPIO4, and GPIO5 are the CSBM, SDIOM,
Table 36. COMM Register Memory Map
Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
COMM0 R/W ICOM0, Bit 3 ICOM0, Bit 2 ICOM0, Bit 1 ICOM0, Bit 0 D0, Bit 7 D0, Bit 6 D0, Bit 5 D0, Bit 4
COMM1 R/W D0, Bit 3 D0, Bit 2 D0, Bit 1 D0, Bit 0 FCOM0, Bit 3 FCOM0, Bit 2 FCOM0, Bit 1 FCOM0, Bit 0
COMM2 R/W ICOM1, Bit 3 ICOM1, Bit 2 ICOM1, Bit 1 ICOM1, Bit 0 D1, Bit 7 D1, Bit 6 D1, Bit 5 D1, Bit 4
COMM3 R/W D1, Bit 3 D1, Bit 2 D1, Bit 1 D1, Bit 0 FCOM1, Bit 3 FCOM1, Bit 2 FCOM1, Bit 1 FCOM1, Bit 0
COMM4 R/W ICOM2, Bit 3 ICOM2, Bit 2 ICOM2, Bit 1 ICOM2, Bit 0 D2, Bit 7 D2, Bit 6 D2, Bit 5 D2, Bit 4
COMM5 R/W D2, Bit 3 D2, Bit 2 D2, Bit 1 D2, Bit 0 FCOM2, Bit 3 FCOM2, Bit 2 FCOM2, Bit 1 FCOM2, Bit 0

Table 37. Write Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C Master
Control Bits Code Action Description
ICOMn, Bits[3:0] 0110 Start Generate a start signal on I2C port followed by a data transmission
0001 Stop Generate a stop signal on I2C port
0000 Blank Proceed directly to data transmission on I2C port
0111 No transmit Release SDA and SCL and ignore the rest of the data
FCOMn, Bits[3:0] 0000 Master ACK Master generates an ACK Signal on ninth clock cycle
1000 Master NACK Master generates a NACK signal on ninth clock cycle
1001 Master NACK + stop Master generates a NACK signal followed by a stop signal

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Table 38. Write Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on SPI Master
Control Bits Code Action Description
ICOMn, Bits[3:0] 1000 CSBM low Generates a CSBM low signal on SPI port (GPIO3)
1010 CSBM falling edge Drives CSBM (GPIO3) high, then low
1001 CSBM high Generates a CSBM high signal on SPI port (GPIO3)
1111 No transmit Releases the SPI port and ignores the rest of the data
FCOMn, Bits[3:0] X000 CSBM low Holds CSBM low at the end of byte transmission
1001 CSBM high Transitions CSBM high at the end of byte transmission

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COMM Commands Table 39. Read Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C
Master
Three commands help accomplish I2C or SPI communication to the Control
slave device: WRCOMM, STCOMM, and RDCOMM. Bits Code Description
WRCOMM Command: This command is used to write data to the 1001 Slave generated a NACK signal, master generated a
COMM register. This command writes 6 bytes of data to the COMM stop signal
register. The PEC needs to be written at the end of the data. If the In case of the SPI master, the read back codes for ICOMn, Bits[3:0]
PEC does not match, all data in the COMM register is cleared to and FCOMn, Bits[3:0] are always 0111 and 1111, respectively. Dn,
1s when CSB goes high. See the Bus Protocols section for more Bits[7:0] contain the data byte transmitted by the SPI slave.
details on a write command format.
Figure 64 shows the operation of ADBMS1818 as an I2C or SPI
STCOMM Command: This command initiates I2C/SPI communica- master using the GPIOs.
tion on the GPIO ports. The COMM register contains 3 bytes of
data to be transmitted to the slave. During this command, the data
bytes stored in the COMM register are transmitted to the slave I2C
or SPI device and the data received from the I2C or SPI device is
stored in the COMM register. This command uses GPIO4 (SDA),
and GPIO5 (SCL) for I2C communication or GPIO3 (CSBM), GPIO4
(SDIOM), and GPIO5 (SCKM) for SPI communication. Figure 64. ADBMS1818 I2C or SPI Master Using GPIOs
The STCOMM command is followed by 24 clock cycles for each
Any number of bytes can be transmitted to the slave in groups
byte of data transmitted to the slave device while holding CSB low.
of 3 bytes using these commands. The GPIO ports do not reset
For example, to transmit three bytes of data to the slave, send
between different STCOMM commands. However, if the wait time
the STCOMM command and its PEC followed by 72 clock cycles.
between the commands is greater than 2 sec, the watchdog times
Pull CSB high at the end of the 72 clock cycles of the STCOMM
out and resets the ports to their default values.
command.
To transmit several bytes of data using an I2C master, a start
During I2C or SPI communication, the data received from the slave
signal is only required at the beginning of the entire data stream.
device is updated in the COMM register.
A stop signal is only required at the end of the data stream. All
RDCOMM Command: The data received from the slave device intermediate data groups can use a blank code before the data byte
can be read back from the COMM register using the RDCOMM and an ACK/NACK signal as appropriate after the data byte. SDA
command. The command reads back six bytes of data followed by and SCL do not reset between different STCOMM commands.
the PEC. See the Bus Protocols section for more details on a read
To transmit several bytes of data using an SPI master, a CSBM
command format.
low signal is sent at the beginning of the 1st data byte. CSBM can
Table 39 describes the possible read back codes for ICOMn, be held low or taken high for intermediate data groups using the
Bits[3:0] and FCOMn, Bits[3:0] when using the device as an I2C appropriate code on FCOMn, Bits[3:0]. A CSBM high signal is sent
master. Dn, Bits[7:0] contain the data byte transmitted by the I2C at the end of the last byte of data. CSBM, SDIOM, and SCKM do
slave. not reset between different STCOMM commands.
Table 39. Read Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C Figure 65 shows the 24 clock cycles following the STCOMM com-
Master mand for an I2C master in different cases. Note that if ICOMn,
Control Bits[3:0] specified a stop condition, after the stop signal is sent, the
Bits Code Description SDA and SCL lines are held high and all data in the rest of the word
ICOMn, 0110 Master generated a start signal is ignored. If ICOMn, Bits[3:0] are a no transmit, both SDA and SCL
Bits[3:0] lines are released, and the rest of the data in the word is ignored.
0001 Master generated a stop signal This is used when a particular device in the stack does not have to
0000 Blank, SDA was held low between bytes communicate to a slave.
0111 Blank, SDA was held high between bytes Figure 66 shows the 24 clock cycles following the STCOMM com-
FCOMn, 0000 Master generated an ACK signal mand for an SPI master. Similar to the I2C master, if ICOMn,
Bits[3:0] Bits[3:0] specified a CSBM HIGH or a no transmit condition, the
0111 Slave generated an ACK signal CSBM, SCKM, and SDIOM lines of the SPI master are released
1111 Slave generated a NACK signal and the rest of the data in the word is ignored.
0001 Slave generated an ACK signal, master generated a
stop signal

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Figure 65. STCOMM Timing Diagram for an I2C Master

Figure 66. STCOMM Timing Diagram for an SPI Master

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Timing Specifications of I2C and SPI Master Table 41. SPI Master Timing
Timing Relationship to Timing Specifications at
The timing of the ADBMS1818 I2C or SPI master is controlled SPI Master Parameter Primary SPI tCLK = 1 μs
by the timing of the communication at the primary SPI of the
ADBMS1818. Table 40 shows the I2C master timing relationship 1 When using isoSPI, t4 is generated internally and is a minimum of 30 ns. Also,
to the primary SPI clock. Table 41 shows the SPI master timing t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high times of the SCK
specifications. input, each with a specified minimum of 200 ns.

Table 40. I2C Master Timing

S PIN PULSING USING THE S PIN CONTROL
Timing Relationship to Timing Specifications at
SETTINGS
I2C Master Parameter Primary SPI tCLK = 1 μs
SCL Clock Frequency 1/(2 × tCLK) 500 kHz maximum The S pins of the ADBMS1818 can be used as a simple serial
tHD, STA t3 200 ns minimum interface, which is particularly useful for controlling the LT8584, a
tLOW tCLK 1 μs minimum monolithic flyback dc-to-dc converter, designed to actively balance
tHIGH tCLK 1 μs minimum large battery stacks. The LT8584 has several operating modes
tSU, STA tCLK + t41 1.03 μs minimum
which are controlled through a serial interface. The ADBMS1818
tHD, DAT t4 30 ns minimum
can communicate to an LT8584 by sending a sequence of pulses
on each S pin to select a specific LT8584 mode. The S pin control
tSU, DAT t3 200 ns minimum
settings (located in S Control Register Group and PWM/S Control
tSU, STO tCLK + t4 1 1.03 μs minimum
Register Group B) are used to specify the behavior for each of
tBUF 3 × tCLK 3 μs minimum the 18 S pins, where each nibble specifies whether the S pin
1 When using isoSPI, t4 is generated internally and is a minimum of 30 ns. Also, drives high, drives low, or sends a pulse sequence between 1
t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high times of the SCK and 7 pulses. The figures in this section show the possible S pin
input, each with a specified minimum of 200 ns. behaviors that can be sent to the LT8584.

Table 41. SPI Master Timing

The S pin pulses occur at a pulse rate of 6.44 kHz (155 μs period).
The pulse width is 77.6 μs. The S pin pulsing begins when the
Timing Relationship to Timing Specifications at
STSCTRL command is sent, after the last command PEC clock,
SPI Master Parameter Primary SPI tCLK = 1 μs
provided that the command PEC matches. The host can then
SDIOM Valid to SCKM t3 200 ns minimum continue to clock SCK in order to poll the status of the pulsing.
Rising Setup This polling works similarly to the ADC polling feature. The data out
SDIO Valid from SCKM tCLK + t41 1.03 μs minimum remains logic low until the S pin pulsing sequence completes.
Rising Hold
SCKM Low tCLK 1 μs minimum While the S pin pulsing is in progress, new STSCTRL, WRSCTRL,
SCKM High tCLK 1 μs minimum or WRPSB commands are ignored. The PLADC command can be
SCKM Period 2 × tCLK 2 μs minimum used to determine when the S pin pulsing completes.
(SCKM_Low +
If the WRSCTRL (or WRPSB) command and command PEC are
SCKM_High)
received correctly but the data PEC does not match, the S pin
CSBM Pulse Width 3 × tCLK 3 μs minimum
control settings are cleared.
SCKM Rising to CSBM 5 × tCLK + t4 1 5.03 μs minimum
Rising If a DCC bit in Configuration Register Group A or Configuration
CSBM Falling to SCKM t3 200 ns minimum Register Group B is asserted, the ADBMS1818 drives the selected
Falling S pin low, regardless of the S pin control settings. The host must
CSBM Falling to SCKM tCLK + t3 1.2 μs minimum leave the DCC bits set to 0 when using the S pin control settings.
Rising
SCKM Falling to SDIOM Master Requires < tCLK
The CLRSCTRL command can be used to quickly reset the S pin
Valid control settings to all 0s and force the pulsing machine to release
control of the S pins. This command can be helpful in reducing the
diagnostic control loop time in an high reliability application.
The following figures show the S pin pulsing behavior.

Figure 67. S Pin Behavior when S Pin Control Bits = 0000

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Figure 68. S Pin Behavior when S Pin Control Bits = 0001

Figure 69. S Pin Behavior when S Pin Control Bits = 0010

Figure 70. S Pin Behavior when S Pin Control Bits = 0011

Figure 71. S Pin Behavior when S Pin Control Bits = 0100

Figure 72. S Pin Behavior when S Pin Control Bits = 0101

Figure 73. S Pin Behavior when S Pin Control Bits = 0110

Figure 74. S Pin Behavior when S Pin Control Bits = 0111

Figure 75. S Pin Behavior when S Pin Control Bits = 1xxx

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S PIN MUTING 2-WIRE ISOLATED INTERFACE (ISOSPI)

PHYSICAL LAYER
The S pins can be disabled by sending the mute command and
reenabled by sending the unmute command. The mute and un- The 2-wire interface provides a means to interconnect ADBMS1818
mute commands do not require any subsequent data and thus devices using simple twisted pair cabling. The interface is designed
the commands propagate quickly through a stack of ADBMS1818 for low packet error rates when the cabling is subjected to high RF
devices. This action allows the host to quickly (<100 µs) disable fields. Isolation is achieved through an external transformer.
and reenable discharging without disturbing register contents. This
ability can be useful, for instance, to allow a specific settling time Standard SPI signals are encoded into differential pulses. The
before taking cell measurements. The mute status is reported in the strength of the transmission pulse and the threshold level of the re-
read-only MUTE bit in Configuration Register Group B. ceiver are set by two external resistors. The values of the resistors
allow the user to trade-off power dissipation for noise immunity.
SERIAL INTERFACE OVERVIEW
Figure 78 shows how the isoSPI circuit operates. A 2 V reference
There are two types of serial ports on the ADBMS1818: a standard drives the IBIAS pin. External resistors RB1 and RB2 create the
4-wire SPI and a 2-wire isoSPI. The state of the ISOMD pin reference current, IB. This current sets the drive strength of the
determines whether Pin 53, Pin 54, Pin 61, and Pin 62 are a 2-wire transmitter. RB1 and RB2 also form a voltage divider to supply a
or 4-wire serial port. fraction of the 2 V reference for the ICMP pin. The receiver circuit
threshold is half of the voltage at the ICMP pin.
The ADBMS1818 is used in a daisy-chain configuration.
A second isoSPI uses Pin 57, Pin 58, Pin 63, and Pin 64. External Connections
4-WIRE SERIAL PERIPHERAL INTERFACE The ADBMS1818 has 2 serial ports, Port B and Port A. Port B is
(SPI) PHYSICAL LAYER always configured as a 2-wire interface. Port A is either a 2-wire or
4-wire interface, depending on the connection of the ISOMD pin.
External Connections When Port A is configured as a 4-wire interface, Port A is always
Connecting ISOMD to V– configures serial Port A for 4-wire SPI. the slave port and Port B is the master port. Communication is
The SDO pin is an open drain output that requires a pull-up resistor always initiated on Port A of the first device in the daisy-chain
tied to the appropriate supply voltage (see Figure 76). configuration. The final device in the daisy chain does not use
Port B, and it must be terminated into RM. Figure 79 shows the
simplest port connections possible when the microprocessor and
the ADBMS1818s are located on the same PCB. In Figure 79,
capacitors are used to couple signals between the ADBMS1818s.
When Port A is configured as a 2-wire interface, communication
can be initiated on either Port A or Port B. If communication is
initiated on Port A, ADBMS1818 configures Port A as a slave and
Port B as a master. Likewise, if communication is initiated on Port
B, ADBMS1818 configures Port B as a slave and Port A as a
master. See the Reversible isoSPI section for a detailed description
Figure 76. 4-Wire SPI Configuration of the reversible isoSPI.
Figure 80 is an example of a robust interconnection of multiple
Timing identical PCBs, each containing one ADBMS1818 configured for
The 4-wire serial port is configured to operate in an SPI system operation in a daisy chain. The microprocessor is located on a sep-
using CPHA = 1 and CPOL = 1. Consequently, data on SDI must arate PCB. To achieve 2-wire isolation between the microprocessor
be stable during the rising edge of SCK. The timing is depicted in PCB and the 1st ADBMS1818 PCB, use the LTC6820 support IC.
Figure 77. The maximum data rate is 1 Mbps. However, the device The LTC6820 is functionally equivalent to the diagram in Figure 78.
is tested at a higher data rate in production to guarantee operation In this example, communication is initiated on Port A. Therefore, the
at the maximum specified data rate. ADBMS1818 configures Port A as a slave and Port B as a master.

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Figure 77. Timing Diagram of 4-Wire Serial Peripheral Interface

Figure 78. isoSPI Interface

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Figure 79. Capacitive-Coupled Daisy-Chain Configuration

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Figure 80. Transformer-Isolated Daisy-Chain Configuration

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Using a Single ADBMS1818 Figure 82. ICMP must not be tied to GND but can be tied directly to
IBIAS. A bias resistance (2 kΩ to 20 kΩ) is required for IBIAS. Do
When only one ADBMS1818 is needed, the device can be used as not tie IBIAS directly to VREG or V–. Finally, IPB and IMB must be
a single (non daisy-chained) device if the second isoSPI port (Port terminated into a 100 Ω resistor (not tied to VREG or V–).
B) is properly biased and terminated, as shown in Figure 81 and

Figure 81. Single Device Using 2-Wire Port A

Figure 82. Single Device Using 4-Wire Port A

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Selecting Bias Resistors pulse. The duration of each pulse is defined as t1/2PW because each
pulse is half of the required symmetric pair. (The total isoSPI pulse
The adjustable signal amplitude allows the system to trade power duration is 2 × t1/2PW).
consumption for communication robustness, and the adjustable
comparator threshold allows the system to account for signal loss- Table 42. isoSPI Pulse Types
es. First Level Second Level
Pulse Type (t1/2PW) (t1/2PW) Ending Level
The isoSPI transmitter drive current and comparator voltage thresh-
old are set by a resistor divider (RBIAS = RB1 + RB2) between IBIAS Long +1 +VA (150 ns) –VA (150 ns) 0V
and V–. The divided voltage is connected to the ICMP pin, which Long –1 –VA (150 ns) +VA (150 ns) 0V
sets the comparator threshold to half of this voltage (VICMP). When Short +1 +VA (50 ns) –VA (50 ns) 0V
either isoSPI is enabled (not idle), IBIAS is held at 2 V, causing IB to Short –1 –VA (50 ns) +VA (50 ns) 0V
flow out of the IBIAS pin. The IPx and IMx pin drive currents are 20
The receiver is designed to detect each of these isoSPI pulse
× IB.
types. For successful detection, the incoming isoSPI pulses (CSB
As an example, if the divider resistor, RB1, is 2.8 kΩ and resistor or data) must meet the following requirements:
RB2 is 1.21 kΩ (so that RBIAS = 4 kΩ), then
► t1/2PW of incoming pulse > tFILT of the receiver and
2 V ► tINV of incoming pulse < tWNDW of the receiver
IB = RB1 + RB2 = 0 . 5 mA

IDRV = IIPx = IIMx = 20 × IB = 10 mA The worst-case margin (Margin 1) for the first condition is the
difference between the minimum t1/2PW of the incoming pulse and
VICMP = 2 V × the maximum tFILT of the receiver. Likewise, the worst-case margin
RB2 (Margin 2) for the second condition is the difference between
RB1 + RB2 minimum tWNDW of the receiver and maximum tINV of the incoming
= IB × RB2 = 603 mV pulse. These timing relations are shown in Figure 83.
VTCMP = 0.5 × VICMP = 302 mV A host microcontroller does not have to generate isoSPI pulses to
In this example, the pulse drive current IDRV is 10 mA, and the use this 2-wire interface. The first ADBMS1818 in the system can
receiver comparators detect pulses with IPx to IMx amplitudes communicate to the microcontroller using the 4-wire SPI on its Port
greater than ±302 mV. A, then daisy chain to other ADBMS1818s using the 2-wire isoSPI
on its Port B. Alternatively, the LTC6820 can be used to translate
If the isolation barrier uses 1:1 transformers connected by a twisted the SPI signals into isoSPI pulses.
pair and terminated with 120 Ω resistors on each end, then the
transmitted differential signal amplitude (±) is the following:
VA = IDRV ×
RM
2
= 0.6 V
This calculation result ignores transformer and cable losses, which
may reduce the amplitude.

isoSPI Pulse Detail

Two ADBMS1818 devices can communicate by transmitting and
receiving differential pulses back and forth through an isolation
barrier. The transmitter can output three voltage levels: +VA, 0 V,
and –VA. A positive output results from IPx sourcing current and
IMx sinking current across the load resistor, RM. A negative voltage Figure 83. isoSPI Pulse Detail
is developed by IPx sinking and IMx sourcing. When both outputs
are off, the load resistance forces the differential output to 0 V. Operation with Port A Configured for SPI
To eliminate the dc signal component and enhance reliability, the When the ADBMS1818 is operating with Port A as a SPI (ISOMD
isoSPI uses two different pulse lengths. This allows four types of = V–), the SPI detects one of four communication events: CSB
pulses to be transmitted, as shown in Table 42. A +1 pulse is falling, CSB rising, SCK rising with SDI = 0, and SCK rising with
transmitted as a positive pulse followed by a negative pulse. A SDI = 1. Each event is converted into one of the four pulse types
–1 pulse is transmitted as a negative pulse followed by a positive for transmission through the daisy chain. Long pulses are used to
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transmit CSB changes and short pulses are used to transmit data, Table 44. Port A (Slave) isoSPI Port Function
as explained in Table 43. Received Pulse (Port A
isoSPI) Internal SPI Port Action Return Pulse
Table 43. Port B (Master) isoSPI Port Function
2. Pulse SCK
Communication Event (Port A SPI) Transmitted Pulse (Port B isoSPI)
Short –1 1. Set SDI = 0 (No return pulse if not in
CSB Rising Long +1 read mode or if reading a
CSB Falling Long –1 1 bit)
SCK Rising Edge, SDI = 1 Short +1 2. Pulse SCK
SCK Rising Edge, SDI = 0 Short –1
The slave isoSPI port never transmits long (CSB) pulses. Further-
Operation with Port A Configured for isoSPI more, a slave isoSPI port only transmits short –1 pulses, never a +1
pulse. The master port recognizes a null response as a Logic 1.
On the other side of the isolation barrier (that is, at the other end
of the cable), the 2nd ADBMS1818 has ISOMD = VREG so that its Reversible isoSPI
Port A is configured for isoSPI. The slave isoSPI port (Port A or
Port B) receives each transmitted pulse and reconstructs the SPI When the ADBMS1818 is operating with Port A configured for
signals internally, as shown in Table 44. In addition, during a read isoSPI, communication can be initiated from either Port A or Port B.
command this port can transmit return data pulses. In other words, ADBMS1818 can configure either Port A or Port B
as a slave or master, depending on the direction of communication.
Table 44. Port A (Slave) isoSPI Port Function The reversible isoSPI feature permits communication from both
Received Pulse (Port A directions in a stack of daisy-chained devices. See Figure 84 for an
isoSPI) Internal SPI Port Action Return Pulse example schematic. Figure 85 shows the operation of the reversible
Long +1 Drive CSB high None isoSPI.
Long –1 Drive CSB low
Short +1 1. Set SDI = 1 Short –1 pulse if reading a
0 bit

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Figure 84. Reversible isoSPI Daisy Chain

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Figure 85. Reversible isoSPI State Diagram

When ADBMS1818 is in the sleep state, the device responds to that was transmitted by the device. Any long isoSPI pulse sent to
a valid wake-up signal on either Port A or Port B. This is true for the master port inside tBLOCK is rejected by the device. This ensures
either configuration of the ISOMD pin. the ADBMS1818 cannot switch ports because of signal reflections
from poorly terminated cables (<100 m cable length).
If the wake-up signal is sent on Port A, ADBMS1818 transmits a
long +1 isoSPI pulse (CSB rising) on Port B after the isoSPI is
Timing Diagrams
powered up. If the wake-up signal is sent on Port B, ADBMS1818
powers up the isoSPI but does not transmit a long +1 isoSPI pulse Figure 86 shows the isoSPI timing diagram for a read command to
on Port A. daisy-chained ADBMS1818 devices. The ISOMD pin is tied to V–
When ADBMS1818 is in the ready state, communication can be on the bottom part so that its Port A is configured as an SPI port
initiated by sending a long –1 isoSPI pulse (CSB falling) on either (CSB, SCK, SDI, and SDO). The isoSPI signals of three stacked
Port A or Port B. The ADBMS1818 automatically configures the port devices are shown labeled with the port (Port A or Port B) and part
that receives the long –1 isoSPI pulse as the slave and the other number. Note that ISO B1 and ISO A2 is actually the same signal,
port is configured as the master. The isoSPI pulses are transmitted but shown on each end of the transmission cable that connects Part
through the master port to the rest of the devices in the daisy chain. 1 and Part 2. Likewise, ISO B2 and ISO A3 is the same signal, but
with the cable delay shown between Part 2 and Part 3.
In the active state, the ADBMS1818 is in the middle of the com-
munication and CSB of the internal SPI port is low. At the end Bit WN to Bit W0 refer to the 16-bit command code and the 16-bit
of communication a long +1 pulse (CSB rising) on the slave port PEC of a read command. At the end of Bit W0, the three parts
returns the device to the ready state. Although it is not part of decode the read command and begin shifting out data, which is
a normal communication routine, the ADBMS1818 allows Port A valid on the next rising edge of clock SCK. Bit XN to Bit X0 refer
and Port B to be swapped inside the active state. This feature to the data shifted out by Part 1. Bit YN to Bit Y0 refer to the data
is useful for the master controller to reclaim control of the slave shifted out by Part 2, and Bit ZN to Bit Z0 refer to the data shifted
port of ADBMS1818, irrespective of the current state of the ports. out by Part 3. All this data is read back from the SDO port on Part 1
This action can be done by sending a long –1 isoSPI pulse on the in a daisy-chained fashion.
master port after a time delay of tBLOCK from the last isoSPI signal

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Figure 86. isoSPI Timing Diagram

Waking Up the Serial Interface up the next device in the stack which, in turn, wakes up the next
device. If there are N devices in the stack, all the devices are
The serial ports (SPI or isoSPI) enter the low power idle state powered up within the time
if there is no activity on Port A or Port B for a time of tIDLE.
The wake-up circuit monitors activity on Pin 61 through Pin 64. If N × tWAKE or N × tREADY, depending on the core state. For large
ISOMD = V–, Port A is in SPI mode. Activity on the CSB pin or stacks, the time N × tWAKE may be equal to or larger than tIDLE. In
SCK pin wakes up the SPI. If ISOMD = VREG, Port A is in isoSPI this case, after waiting longer than the time of N × tWAKE, the host
mode. Differential activity on IPA to IMA (or IPB to IMB) wakes up can send another dummy byte and wait for the time N × tREADY to
the isoSPI. The ADBMS1818 is ready to communicate when the ensure that all devices are in the ready state.
isoSPI state changes to ready within tWAKE or tREADY, depending on Method 1 can be used when all devices on the daisy chain are
the core state (see Figure 53 and the Sleep State, Standby State, in the idle state, which guarantees that the devices propagate the
REFUP State, and Measure State sections for details). wake-up signal up the daisy chain. However, this method fails to
Figure 87 shows the timing and the functionally equivalent circuit wake up all devices when a device in the middle of the chain is in
(only Port A shown). Common-mode signals do not wake up the the ready state instead of the idle state. When this happens, the
serial interface. The interface is designed to wake up after receiving device in the ready state does not propagate the wake-up pulse,
a large signal single-ended pulse, or a low-amplitude symmetric so the devices above it remain in the idle state. This situation can
pulse. The differential signal (SCK(IPA) – CSB(IMA)), must be at occur when attempting to wake up the daisy chain after only tIDLE of
least VWAKE = 200 mV for a minimum duration of tDWELL = 240 ns to idle time (some devices may be idle, some may not).
qualify as a wake-up signal that powers up the serial interface.

Waking a Daisy Chain—Method 1

The ADBMS1818 sends a long +1 pulse on Port B after it is ready
to communicate. In a daisy-chained configuration, this pulse wakes

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Data Sheet ADBMS1818
THEORY OF OPERATION

Figure 87. Wake-Up Detection and Idle Timer

Waking a Daisy Chain—Method 2 IN7 = IN0 XOR PEC, Bit 6

►
► IN8 = IN0 XOR PEC, Bit 7
A more robust wake-up method does not rely on the built-in wake-
up pulse, but manually sends isoSPI traffic for enough time to ► IN10 = IN0 XOR PEC, Bit 9
wake the entire daisy chain. At a minimum, a pair of long isoSPI ► IN14 = IN0 XOR PEC, Bit 13
pulses (–1 and +1) is needed for each device, separated by more 3. Update the 15-bit PEC as follows:
than tREADY or tWAKE (if the core state is standby mode or sleep
mode, respectively), but less than tIDLE. This allows each device to ►PEC, Bit 14 = IN14
wake up and propagate the next pulse to the following device. This ► PEC, Bit 13 = PEC, Bit 12
method works even if some devices in the chain are not in the idle ► PEC, Bit 12 = PEC, Bit 11
state. In practice, implementing Method 2 requires toggling the CSB ► PEC, Bit 11 = PEC, Bit 10
pin (of the LTC6820, or bottom ADBMS1818 with ISOMD = 0) to ► PEC, Bit 10 = IN10
generate the long isoSPI pulses. Alternatively, dummy commands
► PEC, Bit 9 = PEC, Bit 8
(such as RDCFGA) can be executed to generate the long isoSPI
pulses. ► PEC, Bit 8 = IN8
► PEC, Bit 7 = IN7
DATA LINK LAYER ► PEC, Bit 6 = PEC, Bit 5
All data transfers on ADBMS1818 occur in byte groups. Every byte ► PEC, Bit 5 = PEC, Bit 4
consists of 8 bits. Bytes are transferred with the MSB first. CSB ► PEC, Bit 4 = IN4
must remain low for the entire duration of a command sequence, ► PEC, Bit 3 = IN3
including between a command byte and subsequent data. On a
► PEC, Bit 2 = PEC, Bit 1
write command, data is latched in on the rising edge of CSB.
► PEC, Bit 1 = PEC, Bit 0
NETWORK LAYER ► PEC, Bit 0 = IN0
4. Go back to Step 2 until all the data is shifted. The final PEC
Packet Error Code (16 bits) is the 15-bit value in the PEC register with a 0 bit
The PEC is a 15-bit cyclic redundancy check (CRC) value calculat- appended to its LSB.
ed for all of the bits in a register group in the order they are passed, Figure 88 shows the 15-bit PEC algorithm. An example to calculate
using the initial PEC value of 000000000010000 and the following the PEC for a 16-bit word (0x0001) is listed in Table 45. The PEC
characteristic polynomial: x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1. for 0x0001 is computed as 0x3D6E after stuffing a 0 bit at the LSB.
To calculate the 15-bit PEC value, a simple procedure can be For longer data streams, the PEC is valid at the end of the last bit of
established: data sent to the PEC register.
1. Initialize the PEC to 000000000010000 (PEC is a 15‑bit register The ADBMS1818 calculates the PEC for any command or data
group). received and compares it with the PEC following the command or
2. For each bit DIN coming into the PEC register group, set: data. The command or data is regarded as valid only if the PEC
matches. ADBMS1818 also attaches the calculated PEC at the end
► IN0 = DIN XOR PEC, Bit 14 of the data it shifts out. Table 46 shows the format of PEC while
► IN3 = IN0 XOR PEC, Bit 2 writing to or reading from ADBMS1818.
► IN4 = IN0 XOR PEC, Bit 3

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Data Sheet ADBMS1818
THEORY OF OPERATION

Figure 88. 15-Bit PEC Computation Circuit

Table 45. PEC Calculation for 0x0001

PEC, Bit 13 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0
PEC, Bit 13 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0
PEC, Bit 12 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1
PEC, Bit 11 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1
PEC, Bit 10 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 1
PEC, Bit 9 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1
PEC, Bit 8 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0
PEC, Bit 7 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1
PEC, Bit 6 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
PEC, Bit 5 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1
PEC, Bit 4 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1
PEC, Bit 3 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0
PEC, Bit 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
PEC, Bit 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
PEC, Bit 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
IN14 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0
IN10 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 PEC Word
IN8 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0
IN7 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1
IN4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1
IN3 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0
IN0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
DIN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Clock Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Table 46. Write/Read PEC Format

Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PEC0 R PEC, Bit 14 PEC, Bit 13 PEC, Bit 12 PEC, Bit 11 PEC, Bit 10 PEC, Bit 9 PEC, Bit 8 PEC, Bit 17
PEC1 R PEC, Bit 6 PEC, Bit 5 PEC, Bit 4 PEC, Bit 3 PEC, Bit 2 PEC, Bit 1 PEC, Bit 0 0

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Data Sheet ADBMS1818
THEORY OF OPERATION

While writing any command to ADBMS1818, the command bytes The next method overcomes this limitation. The controller can send
CMD0 and CMD1 (see Table 49 and Table 50) and the PEC bytes an ADC start command, perform other tasks, and then send a poll
PEC0 and PEC1 are sent on Port A in the following order: ADC converter status (PLADC) command to determine the status
of the ADC conversions (see Figure 90). After entering the PLADC
CMD0, CMD1, PEC0, PEC1 command, SDO goes low if the device is busy performing conver-
After a write command to daisy-chained ADBMS1818 devices, sions. SDO is pulled high at the end of conversions. However, SDO
data is sent to each device followed by the PEC. For example, also goes high when CSB goes high even if the device has not
when writing Configuration Register Group A to two daisy-chained completed the conversion.
devices (primary device P, stacked device S), the data is sent to the If using a single ADBMS1818 that communicates in isoSPI mode,
primary device on Port A in the following order: the low-side port transmits a data pulse only in response to a
CFGAR0(S), … , CFGAR5(S), PEC0(S), PEC1(S), CFGAR0(P), master isoSPI pulse received by it. Therefore, after entering the
… , CFGAR5(P), PEC0(P), PEC1(P) command in either method of polling described previously, isoSPI
data pulses are sent to the part to update the conversion status.
After a read command for daisy-chained devices, each device shifts These pulses can be sent using the LTC6820 by simply clocking its
out its data and the PEC that it computed for its data on Port SCK pin. In response to this pulse, the ADBMS1818 sends back a
A followed by the data received on Port B. For example, when low isoSPI pulse if it is still busy performing conversions or a high
reading Status Register Group B from two daisy -chained devices data pulse if it has completed the conversions. If a CSB high isoSPI
(primary device P, stacked device S), the primary device sends out pulse is sent to the device, the device exits the polling command.
data on Port A in the following order:
In a daisy-chained configuration of N stacked devices, the same
STBR0(P), … , STBR5(P), PEC0(P), PEC1(P), STBR0(S), … , two polling methods can be used. If the bottom device communi-
STBR5(S), PEC0(S), PEC1(S) cates in SPI mode, the SDO of the bottom device indicates the
See the Bus Protocols section for the command format. conversion status of the entire stack. That is, SDO remains low until
all the devices in the stack have completed the conversions. In the
All devices in a daisy-chained configuration receive the command first method of polling, after an ADC conversion command is sent,
bytes simultaneously. For example, to initiate ADC conversions in a clock pulses are sent on SCK while keeping CSB low. The SDO
stack of devices, a single ADCV command is sent, and all devices status becomes valid only at the end of N clock pulses on SCK.
start conversions at the same time. For read and write commands, During the first N clock pulses, the bottom ADBMS1818 in the daisy
a single command is sent, and the stacked devices effectively turn chain outputs a 0 or a low data pulse. After N clock pulses, the
into a cascaded shift register, in which data is shifted through each output data from the bottom ADBMS1818 gets updated for every
device to the next higher (on a write) or the next lower (on a read) clock pulse that follows (see Figure 91). In the second method, the
device in the stack. See the Serial Interface Overview section. PLADC command is sent followed by clock pulses on SCK while
keeping CSB low. Similar to the first method, the SDO status is
Polling Methods valid only after N clock cycles on SCK and gets updated after every
The simplest method to determine ADC completion is for the clock cycle that follows (see Figure 92).
controller to start an ADC conversion and wait for the specified If the bottom device communicates in isoSPI mode, isoSPI data
conversion time to pass before reading the results. pulses are sent to the device to update the conversion status.
If using a single ADBMS1818 that communicates in SPI mode Using the LTC6820, this action can be achieved by just clocking
(ISOMD pin tied low), there are two methods of polling. The first the SCK pin. The conversion status is valid only after the bottom
method is to hold CSB low after an ADC conversion command ADBMS1818 device receives N isoSPI data pulses and the status
is sent. After entering a conversion command, the SDO line is gets updated for every isoSPI data pulse that follows. The device
driven low when the device is busy performing conversions. SDO returns a low data pulse if any of the devices in the stack is busy
is pulled high when the device completes conversions. However, performing conversions and returns a high data pulse if all the
SDO also goes high when CSB goes high even if the device has devices are free.
not completed the conversion (see Figure 89). A problem with this
method is that the controller is not free to perform other serial
communications while waiting for ADC conversions to complete.

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Data Sheet ADBMS1818
THEORY OF OPERATION

Figure 89. SDO Polling After an ADC Conversion Command (Single ADBMS1818)

Figure 90. SDO Polling Using PLADC Command (Single ADBMS1818)

Figure 91. SDO Polling After an ADC Conversion Command (Daisy-Chain Configuration)

Figure 92. SDO Polling Using PLADC Command (Daisy-Chain Configuration)

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Data Sheet ADBMS1818
THEORY OF OPERATION

Bus Protocols Table 47. Protocol Key

Byte Description
The protocol formats for commands are depicted in Table 48, Table
49, and Table 50. Table 47 is the key for reading the protocol PEC0 PEC Byte 0 (see Table 46)
diagrams. PEC1 PEC Byte 1 (see Table 46)
n Number of bytes
Table 47. Protocol Key
… Continuation of protocol
Byte Description Master to slave
CMD0 Command Byte 0 (see Table 51) Slave to master
CMD1 Command Byte 1 (see Table 51)
Table 48. Poll Command
8 8 8 8
CMD0 CMD1 PEC0 PEC1 Poll Data

Table 49. Write Command

8 8 8 8 8 8 8 8 8 8
CMD0 CMD1 PEC0 PEC1 Data byte … Data byte PEC0 PEC1 Shift Byte 1 … Shift Byte n
low high

Table 50. Read Command

8 8 8 8 8 8 8 8 8 8
CMD0 CMD1 PEC0 PEC1 Data byte … Data byte PEC0 PEC1 Shift Byte 1 … Shift Byte n
low high

Command Format: The format for the commands is shown in Table 51. CC, Bits[10:0] is the 11-bit command code. A list of all the command
codes is shown in Table 52. All commands have a value 0 for CMD0, Bit 7 through CMD0, Bit 3. The PEC must be computed on the entire
16-bit command (CMD0 and CMD1).

Table 51. Command Format

Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CMD0 W 0 0 0 0 0 CC, Bit 10 CC, Bit 9 CC, Bit 8
CMD1 W CC, Bit 7 CC, Bit 6 CC, Bit 5 CC, Bit 4 CC, Bit 3 CC, Bit 2 CC, Bit 1 CC, Bit 0

Commands
Table 52 lists all the commands and their options.
Table 52. Command Codes
CC, Bits[10:0] – Command Code
Command Description Name 10 9 8 7 6 5 4 3 2 1 0
Write Configuration Register Group A WRCFGA 0 0 0 0 0 0 0 0 0 0 1
Write Configuration Register Group B WRCFGB 0 0 0 0 0 1 0 0 1 0 0
Read Configuration Register Group A RDCFGA 0 0 0 0 0 0 0 0 0 1 0
Read Configuration Register Group B RDCFGB 0 0 0 0 0 1 0 0 1 1 0
Read Cell Voltage Register Group A RDCVA 0 0 0 0 0 0 0 0 1 0 0
Read Cell Voltage Register Group B RDCVB 0 0 0 0 0 0 0 0 1 1 0
Read Cell Voltage Register Group C RDCVC 0 0 0 0 0 0 0 1 0 0 0
Read Cell Voltage Register Group D RDCVD 0 0 0 0 0 0 0 1 0 1 0
Read Cell Voltage Register Group E RDCVE 0 0 0 0 0 0 0 1 0 0 1
Read Cell Voltage Register Group F RDCVF 0 0 0 0 0 0 0 1 0 1 1
Read Auxiliary Register Group A RDAUXA 0 0 0 0 0 0 0 1 1 0 0
Read Auxiliary Register Group B RDAUXB 0 0 0 0 0 0 0 1 1 1 0
Read Auxiliary Register Group C RDAUXC 0 0 0 0 0 0 0 1 1 0 1

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Data Sheet ADBMS1818
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Table 52. Command Codes

CC, Bits[10:0] – Command Code
Command Description Name 10 9 8 7 6 5 4 3 2 1 0
Read Auxiliary Register Group D RDAUXD 0 0 0 0 0 0 0 1 1 1 1
Read Status Register Group A RDSTATA 0 0 0 0 0 0 1 0 0 0 0
Read Status Register Group B RDSTATB 0 0 0 0 0 0 1 0 0 1 0
Write S Control Register Group WRSCTRL 0 0 0 0 0 0 1 0 1 0 0
Write PWM Register Group WRPWM 0 0 0 0 0 1 0 0 0 0 0
Write PWM/S Control Register Group B WRPSB 0 0 0 0 0 0 1 1 1 0 0
Read S Control Register Group RDSCTRL 0 0 0 0 0 0 1 0 1 1 0
Read PWM Register Group RDPWM 0 0 0 0 0 1 0 0 0 1 0
Read PWM/S Control Register Group B RDPSB 0 0 0 0 0 0 1 1 1 1 0
Start S Control Pulsing and Poll Status STSCTRL 0 0 0 0 0 0 1 1 0 0 1
Clear S Control Register Group CLRSCTRL 0 0 0 0 0 0 1 1 0 0 0
Start Cell Voltage ADC Conversion and Poll Status ADCV 0 1 MD, Bit MD, Bit 1 1 DCP 0 CH, Bit 2 CH, Bit 1 CH, Bit 0
1 0
Start Open Wire ADC Conversion and Poll Status ADOW 0 1 MD, Bit MD, Bit PUP 1 DCP 1 CH, Bit 2 CH, Bit 1 CH, Bit 0
1 0
Start Self Test Cell Voltage Conversion and Poll CVST 0 1 MD, Bit MD, Bit ST, Bit ST, Bit 0 0 1 1 1
Status 1 0 1 0
Start Overlap Measurements of Cell 7 and Cell 13 ADOL 0 1 MD, Bit MD, Bit 0 0 DCP 0 0 0 1
Voltages 1 0
Start GPIOs ADC Conversion and Poll Status ADAX 1 0 MD, Bit MD, Bit 1 1 0 0 CHG, Bit 2 CHG, Bit 1 CHG, Bit 0
1 0
Start GPIOs ADC Conversion with Digital ADAXD 1 0 MD, Bit MD, Bit 0 0 0 0 CHG, Bit 2 CHG, Bit 1 CHG, Bit 0
Redundancy and Poll Status 1 0
Start GPIOs Open Wire ADC Conversion and Poll AXOW 1 0 MD, Bit MD, Bit PUP 0 1 0 CHG, Bit 2 CHG, Bit 1 CHG, Bit 0
Status 1 0
Start Self Test GPIOs Conversion and Poll Status AXST 1 0 MD, Bit MD, Bit ST, Bit ST, Bit 0 0 1 1 1
1 0 1 0
Start Status Group ADC Conversion and Poll ADSTAT 1 0 MD, Bit MD, Bit 1 1 0 1 CHST, Bit CHST, Bit CHST, Bit 0
Status 1 0 2 1
Start Status Group ADC Conversion with Digital ADSTATD 1 0 MD, Bit MD, Bit 0 0 0 1 CHST, Bit CHST, Bit CHST, Bit 0
Redundancy and Poll Status 1 0 2 1
Start Self Test Status Group Conversion and Poll STATST 1 0 MD, Bit MD, Bit ST, Bit ST, Bit 0 1 1 1 1
Status 1 0 1 0
Start Combined Cell Voltage and GPIO1, GPIO2 ADCVAX 1 0 MD, Bit MD, Bit 1 1 DCP 1 1 1 1
Conversion and Poll Status 1 0
Start Combined Cell Voltage and SC Conversion ADCVSC 1 0 MD, Bit MD, Bit 1 1 DCP 0 1 1 1
and Poll Status 1 0
Clear Cell Voltage Register Groups CLRCELL 1 1 1 0 0 0 1 0 0 0 1
Clear Auxiliary Register Groups CLRAUX 1 1 1 0 0 0 1 0 0 1 0
Clear Status Register Groups CLRSTAT 1 1 1 0 0 0 1 0 0 1 1
Poll ADC Conversion Status PLADC 1 1 1 0 0 0 1 0 1 0 0
Diagnose MUX and Poll Status DIAGN 1 1 1 0 0 0 1 0 1 0 1
Write COMM Register Group WRCOMM 1 1 1 0 0 1 0 0 0 0 1
Read COMM Register Group RDCOMM 1 1 1 0 0 1 0 0 0 1 0
Start I2C/SPI Communication STCOMM 1 1 1 0 0 1 0 0 0 1 1
Mute Discharge Mute 0 0 0 0 0 1 0 1 0 0 0
Unmute Discharge Unmute 0 0 0 0 0 1 0 1 0 0 1

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Data Sheet ADBMS1818
THEORY OF OPERATION

Table 53. Command Bit Descriptions

Name Description Values
MD, Bits[1:0] ADC Mode MD ADCOPT(CFGAR0, Bit 0) = 0 ADCOPT(CFGAR0, Bit 0) = 1
00 422 Hz mode 1 kHz mode
01 27 kHz mode (fast) 14 kHz mode
10 7 kHz mode (normal) 3 kHz mode
11 26 Hz mode (filtered) 2 kHz mode
DCP Discharge Permitted DCP
0 Discharge Not Permitted
1 Discharge Permitted
CH, Bits[2:0] Cell Selection for Total Conversion Time in the 8 ADC Modes
ADC Conversion
CH 27 kHz 14 kHz 7 kHz 3 kHz 2 kHz 1 kHz 422 Hz 26 Hz
000 All cells 1.1 ms 1.3 ms 2.3 ms 3.0 ms 4.4 ms 7.2 ms 12.8 ms 201 ms
001 Cells 1, 7, 13 203 μs 232 μs 407 μs 523 μs 756 μs 1.2 ms 2.2 ms 34 ms
010 Cells 2, 8, 14 203 μs 232 μs 407 μs 523 μs 756 μs 1.2 ms 2.2 ms 34 ms
011 Cells 3, 9, 15 203 μs 232 μs 407 μs 523 μs 756 μs 1.2 ms 2.2 ms 34 ms
100 Cells 4, 10, 16 203 μs 232 μs 407 μs 523 μs 756 μs 1.2 ms 2.2 ms 34 ms
101 Cells 5, 11, 17 203 μs 232 μs 407 μs 523 μs 756 μs 1.2 ms 2.2 ms 34 ms
110 Cells 6, 12, 18 203 μs 232 μs 407 μs 523 μs 756 μs 1.2 ms 2.2 ms 34 ms
PUP Pull-Up/Pull- Down PUP
Current for Open
Wire Conversions
0 Pull-down current
1 Pull-up current
Self Test Conversion Result
ST, Bits[1:0] Self Test Mode ST 27 kHz 14 kHz 7 kHz 3 kHz 2 kHz 1 kHz 422 Hz 26 Hz
Selection 01 Self Test 1 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 0x9555 0x9555
10 Self test 2 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA 0x6AAA 0x6AAA
CHG, Bits[2:0] GPIO Selection for Total Conversion Time in the 8 ADC Modes
ADC Conversion
CHG 27 kHz 14 kHz 7 kHz 3 kHz 2 kHz 1 kHz 422 Hz 26 Hz
000 GPIO1 to 1.8 ms 2.1 ms 3.9 ms 5.0ms 7.4 ms 12.0 ms 21.3 ms 335 ms
GPIO5, 2nd
Reference,
GPIO6 to
GPIO9
001 GPIO1 and 380 μs 439 μs 788 μs 1.0 ms 1.5 ms 2.4 ms 4.3 ms 67.1 ms
GPIO6
010 GPIO2 and 380 μs 439 μs 788 μs 1.0 ms 1.5 ms 2.4 ms 4.3 ms 67.1 ms
GPIO7
011 GPIO3 and 380 μs 439 μs 788 μs 1.0 ms 1.5 ms 2.4 ms 4.3 ms 67.1 ms
GPIO8
100 GPIO4 and 380 μs 439 μs 788 μs 1.0 ms 1.5 ms 2.4 ms 4.3 ms 67.1 ms
GPIO9
101 GPIO5 200 μs 229 μs 403 μs 520 μs 753 μs 1.2 ms 2.1 ms 34 ms
110 2nd Reference 200 μs 229 μs 403 μs 520 μs 753 μs 1.2 ms 2.1 ms 34 ms
CHST, Status Group Total Conversion Time in the 8 ADC Modes
Bits[2:0]1 Selection
CHST 27 kHz 14 kHz 7 kHz 3 kHz 2 kHz 1 kHz 422 Hz 26 Hz
000 SC, ITMP, VA, 742 μs 858 μs 1.6 ms 2.0 ms 3.0 ms 4.8 ms 8.5 ms 134 ms
VD

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Table 53. Command Bit Descriptions

Name Description Values
001 SC 200 μs 229 μs 403 μs 520 μs 753 μs 1.2 ms 2.1 ms 34 ms
010 ITMP 200 μs 229 μs 403 μs 520 μs 753 μs 1.2 ms 2.1 ms 34 ms
011 VA 200 μs 229 μs 403 μs 520 μs 753 μs 1.2 ms 2.1 ms 34 ms
100 VD 200 μs 229 μs 403 μs 520 μs 753 μs 1.2 ms 2.1 ms 34 ms
1 Note: Valid options for CHST in ADSTAT command are 0 to 4. If CHST is set to 5/6 in ADSTAT command, the ADBMS1818 ignores the command.

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Table 54. Configuration Register Group A

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CFGAR0 R/W GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 REFON DTEN ADCOPT
CFGAR1 R/W VUV[7] VUV[6] VUV[5] VUV[4] VUV[3] VUV[2] VUV[1] VUV[0]
CFGAR2 R/W VOV[3] VOV[2] VOV[1] VOV[0] VUV[11] VUV[10] VUV[9] VUV[8]
CFGAR3 R/W VOV[11] VOV[10] VOV[9] VOV[8] VOV[7] VOV[6] VOV[5] VOV[4]
CFGAR4 R/W DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1
CFGAR5 R/W DCTO[3] DCTO[2] DCTO[1] DCTO[0] DCC12 DCC11 DCC10 DCC9

Table 55. Configuration Register Group B

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CFGBR0 R/W DCC16 DCC15 DCC14 DCC13 GPIO9 GPIO8 GPIO7 GPIO6
CFGBR1 R/W MUTE FDRF PS[1] PS[0] DTMEN DCC0 DCC18 DCC17
CFGBR2 R/W RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0
CFGBR3 R/W RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0
CFGBR4 R/W RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0
CFGBR5 R/W RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0

Table 56. Cell Voltage Register Group A

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CVAR0 R C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[0]
CVAR1 R C1V[15] C1V[14] C1V[13] C1V[12] C1V[11] C1V[10] C1V[9] C1V[8]
CVAR2 R C2V[7] C2V[6] C2V[5] C2V[4] C2V[3] C2V[2] C2V[1] C2V[0]
CVAR3 R C2V[15] C2V[14] C2V[13] C2V[12] C2V[11] C2V[10] C2V[9] C2V[8]
CVAR4 R C3V[7] C3V[6] C3V[5] C3V[4] C3V[3] C3V[2] C3V[1] C3V[0]
CVAR5 R C3V[15] C3V[14] C3V[13] C3V[12] C3V[11] C3V[10] C3V[9] C3V[8]

Table 57. Cell Voltage Register Group B

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CVBR0 R C4V[7] C4V[6] C4V[5] C4V[4] C4V[3] C4V[2] C4V[1] C4V[0]
CVBR1 R C4V[15] C4V[14] C4V[13] C4V[12] C4V[11] C4V[10] C4V[9] C4V[8]
CVBR2 R C5V[7] C5V[6] C5V[5] C5V[4] C5V[3] C5V[2] C5V[1] C5V[0]
CVBR3 R C5V[15] C5V[14] C5V[13] C5V[12] C5V[11] C5V[10] C5V[9] C5V[8]
CVBR4 R C6V[7] C6V[6] C6V[5] C6V[4] C6V[3] C6V[2] C6V[1] C6V[0]
CVBR5 R C6V[15] C6V[14] C6V[13] C6V[12] C6V[11] C6V[10] C6V[9] C6V[8]

Table 58. Cell Voltage Register Group C

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CVCR0 R C7V[7] C7V[6] C7V[5] C7V[4] C7V[3] C7V[2] C7V[1] C7V[0]
CVCR1 R C7V[15] C7V[14] C7V[13] C7V[12] C7V[11] C7V[10] C7V[9] C7V[8]
CVCR21 R C8V[7] 1 C8V[6] 1 C8V[5] 1 C8V[4] 1 C8V[3] 1 C8V[2] 1 C8V[1] 1 C8V[0] 1
CVCR3 1 R C8V[15] 1 C8V[14] 1 C8V[13] 1 C8V[12] 1 C8V[11] 1 C8V[10] 1 C8V[9] 1 C8V[8] 1
CVCR4 R C9V[7] C9V[6] C9V[5] C9V[4] C9V[3] C9V[2] C9V[1] C9V[0]
CVCR5 R C9V[15] C9V[14] C9V[13] C9V[12] C9V[11] C9V[10] C9V[9] C9V[8]
1 After performing the ADOL command, CVCR2 and CVCR3 of Cell Voltage Register Group C contain the result of measuring Cell 7 from ADC1.

Table 59. Cell Voltage Register Group D

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CVDR0 R C10V[7] C10V[6] C10V[5] C10V[4] C10V[3] C10V[2] C10V[1] C10V[0]
CVDR1 R C10V[15] C10V[14] C10V[13] C10V[12] C10V[11] C10V[10] C10V[9] C10V[8]

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MEMORY MAP

Table 59. Cell Voltage Register Group D

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CVDR2 R C11V[7] C11V[6] C11V[5] C11V[4] C11V[3] C11V[2] C11V[1] C11V[0]
CVDR3 R C11V[15] C11V[14] C11V[13] C11V[12] C11V[11] C11V[10] C11V[9] C11V[8]
CVDR4 R C12V[7] C12V[6] C12V[5] C12V[4] C12V[3] C12V[2] C12V[1] C12V[0]
CVDR5 R C12V[15] C12V[14] C12V[13] C12V[12] C12V[11] C12V[10] C12V[9] C12V[8]

Table 60. Cell Voltage Register Group E

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CVER0 R C13V[7] C13V[6] C13V[5] C13V[4] C13V[3] C13V[2] C13V[1] C13V[0]
CVER1 R C13V[15] C13V[14] C13V[13] C13V[12] C13V[11] C13V[10] C13V[9] C13V[8]
CVER21 R C14V[7] 1 C14V[6] 1 C14V[5] 1 C14V[4] 1 C14V[3] 1 C14V[2] 1 C14V[1] 1 C14V[0] 1
CVER3 1 R C14V[15] 1 C14V[14] 1 C14V[13] 1 C14V[12] 1 C14V[11] 1 C14V[10] 1 C14V[9] 1 C14V[8] 1
CVER4 R C15V[7] C15V[6] C15V[5] C15V[4] C15V[3] C15V[2] C15V[1] C15V[0]
CVER5 R C15V[15] C15V[14] C15V[13] C15V[12] C15V[11] C15V[10] C15V[9] C15V[8]
1 After performing the ADOL command, CVER2 and CVER3 of Cell Voltage Register Group E contain the result of measuring Cell 13 from ADC2.

Table 61. Cell Voltage Register Group F

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CVFR0 R C16V[7] C16V[6] C16V[5] C16V[4] C16V[3] C16V[2] C16V[1] C16V[0]
CVFR1 R C16V[15] C16V[14] C16V[13] C16V[12] C16V[11] C16V[10] C16V[9] C16V[8]
CVFR2 R C17V[7] C17V[6] C17V[5] C17V[4] C17V[3] C17V[2] C17V[1] C17V[0]
CVFR3 R C17V[15] C17V[14] C17V[13] C17V[12] C17V[11] C17V[10] C17V[9] C17V[8]
CVFR4 R C18V[7] C18V[6] C18V[5] C18V[4] C18V[3] C18V[2] C18V[1] C18V[0]
CVFR5 R C18V[15] C18V[14] C18V[13] C18V[12] C18V[11] C18V[10] C18V[9] C18V[8]

Table 62. Auxiliary Register Group A

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AVAR0 R G1V[7] G1V[6] G1V[5] G1V[4] G1V[3] G1V[2] G1V[1] G1V[0]
AVAR1 R G1V[15] G1V[14] G1V[13] G1V[12] G1V[11] G1V[10] G1V[9] G1V[8]
AVAR2 R G2V[7] G2V[6] G2V[5] G2V[4] G2V[3] G2V[2] G2V[1] G2V[0]
AVAR3 R G2V[15] G2V[14] G2V[13] G2V[12] G2V[11] G2V[10] G2V[9] G2V[8]
AVAR4 R G3V[7] G3V[6] G3V[5] G3V[4] G3V[3] G3V[2] G3V[1] G3V[0]
AVAR5 R G3V[15] G3V[14] G3V[13] G3V[12] G3V[11] G3V[10] G3V[9] G3V[8]

Table 63. Auxiliary Register Group B

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AVBR0 R G4V[7] G4V[6] G4V[5] G4V[4] G4V[3] G4V[2] G4V[1] G4V[0]
AVBR1 R G4V[15] G4V[14] G4V[13] G4V[12] G4V[11] G4V[10] G4V[9] G4V[8]
AVBR2 R G5V[7] G5V[6] G5V[5] G5V[4] G5V[3] G5V[2] G5V[1] G5V[0]
AVBR3 R G5V[15] G5V[14] G5V[13] G5V[12] G5V[11] G5V[10] G5V[9] G5V[8]
AVBR4 R REF[7] REF[6] REF[5] REF[4] REF[3] REF[2] REF[1] REF[0]
AVBR5 R REF[15] REF[14] REF[13] REF[12] REF[11] REF[10] REF[9] REF[8]

Table 64. Auxiliary Register Group C

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AVCR0 R G6V[7] G6V[6] G6V[5] G6V[4] G6V[3] G6V[2] G6V[1] G6V[0]
AVCR1 R G6V[15] G6V[14] G6V[13] G6V[12] G6V[11] G6V[10] G6V[9] G6V[8]
AVCR2 R G7V[7] G7V[6] G7V[5] G7V[4] G7V[3] G7V[2] G7V[1] G7V[0]
AVCR3 R G7V[15] G7V[14] G7V[13] G7V[12] G7V[11] G7V[10] G7V[9] G7V[8]

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Data Sheet ADBMS1818
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Table 64. Auxiliary Register Group C

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AVCR4 R G8V[7] G8V[6] G8V[5] G8V[4] G8V[3] G8V[2] G8V[1] G8V[0]
AVCR5 R G8V[15] G8V[14] G8V[13] G8V[12] G8V[11] G8V[10] G8V[9] G8V[8]

Table 65. Auxiliary Register Group D

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AVDR0 R G9V[7] G9V[6] G9V[5] G9V[4] G9V[3] G9V[2] G9V[1] G9V[0]
AVDR1 R G9V[15] G9V[14] G9V[13] G9V[12] G9V[11] G9V[10] G9V[9] G9V[8]
AVDR2 R RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1
AVDR3 R RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1
AVDR4 R C16OV C16UV C15OV C15UV C14OV C14UV C13OV C13UV
AVDR5 R RSVD1 RSVD1 RSVD1 RSVD1 C18OV C18UV C17OV C17UV

Table 66. Status Register Group A

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STAR0 R SC[7] SC[6] SC[5] SC[4] SC[3] SC[2] SC[1] SC[0]
STAR1 R SC[15] SC[14] SC[13] SC[12] SC[11] SC[10] SC[9] SC[8]
STAR2 R ITMP[7] ITMP[6] ITMP[5] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[0]
STAR3 R ITMP[15] ITMP[14] ITMP[13] ITMP[12] ITMP[11] ITMP[10] ITMP[9] ITMP[8]
STAR4 R VA[7] VA[6] VA[5] VA[4] VA[3] VA[2] VA[1] VA[0]
STAR5 R VA[15] VA[14] VA[13] VA[12] VA[11] VA[10] VA[9] VA[8]

Table 67. Status Register Group B

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STBR0 R VD[7] VD[6] VD[5] VD[4] VD[3] VD[2] VD[1] VD[0]
STBR1 R VD[15] VD[14] VD[13] VD[12] VD[11] VD[10] VD[9] VD[8]
STBR2 R C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV
STBR3 R C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV
STBR4 R C12OV C12UV C11OV C11UV C10OV C10UV C9OV C9UV
STBR5 R REV[3] REV[2] REV[1] REV[0] RSVD RSVD MUXFAIL THSD

Table 68. COMM Register Group

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
COMM0 R/W ICOM0[3] ICOM0[2] ICOM0[1] ICOM0[0] D0[7] D0[6] D0[5] D0[4]
COMM1 R/W D0[3] D0[2] D0[1] D0[0] FCOM0[3] FCOM0[2] FCOM0[1] FCOM0[0]
COMM2 R/W ICOM1[3] ICOM1[2] ICOM1[1] ICOM1[0] D1[7] D1[6] D1[5] D1[4]
COMM3 R/W D1[3] D1[2] D1[1] D1[0] FCOM1[3] FCOM1[2] FCOM1[1] FCOM1[0]
COMM4 R/W ICOM2[3] ICOM2[2] ICOM2[1] ICOM2[0] D2[7] D2[6] D2[5] D2[4]
COMM5 R/W D2[3] D2[2] D2[1] D2[0] FCOM2[3] FCOM2[2] FCOM2[1] FCOM2[0]

Table 69. S Control Register Group

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SCTRL0 R/W SCTL2[3] SCTL2[2] SCTL2[1] SCTL2[0] SCTL1[3] SCTL1[2] SCTL1[1] SCTL1[0]
SCTRL1 R/W SCTL4[3] SCTL4[2] SCTL4[1] SCTL4[0] SCTL3[3] SCTL3[2] SCTL3[1] SCTL3[0]
SCTRL2 R/W SCTL6[3] SCTL6[2] SCTL6[1] SCTL6[0] SCTL5[3] SCTL5[2] SCTL5[1] SCTL5[0]
SCTRL3 R/W SCTL8[3] SCTL8[2] SCTL8[1] SCTL8[0] SCTL7[3] SCTL7[2] SCTL7[1] SCTL7[0]
SCTRL4 R/W SCTL10[3] SCTL10[2] SCTL10[1] SCTL10[0] SCTL9[3] SCTL9[2] SCTL9[1] SCTL9[0]
SCTRL5 R/W SCTL12[3] SCTL12[2] SCTL12[1] SCTL12[0] SCTL11[3] SCTL11[2] SCTL11[1] SCTL11[0]

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Data Sheet ADBMS1818
MEMORY MAP

Table 70. PWM Register Group

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWMR0 R/W PWM2[3] PWM2[2] PWM2[1] PWM2[0] PWM1[3] PWM1[2] PWM1[1] PWM1[0]
PWMR1 R/W PWM4[3] PWM4[2] PWM4[1] PWM4[0] PWM3[3] PWM3[2] PWM3[1] PWM3[0]
PWMR2 R/W PWM6[3] PWM6[2] PWM6[1] PWM6[0] PWM5[3] PWM5[2] PWM5[1] PWM5[0]
PWMR3 R/W PWM8[3] PWM8[2] PWM8[1] PWM8[0] PWM7[3] PWM7[2] PWM7[1] PWM7[0]
PWMR4 R/W PWM10[3] PWM10[2] PWM10[1] PWM10[0] PWM9[3] PWM9[2] PWM9[1] PWM9[0]
PWMR5 R/W PWM12[3] PWM12[2] PWM12[1] PWM12[0] PWM11[3] PWM11[2] PWM11[1] PWM11[0]

Table 71. PWM/S Control Register Group B

Register R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PSR0 R/W PWM14[3] PWM14[2] PWM14[1] PWM14[0] PWM13[3] PWM13[2] PWM13[1] PWM13[0]
PSR1 R/W PWM16[3] PWM16[2] PWM16[1] PWM16[0] PWM15[3] PWM15[2] PWM15[1] PWM15[0]
PSR2 R/W PWM18[3] PWM18[2] PWM18[1] PWM18[0] PWM17[3] PWM17[2] PWM7[1] PWM17[0]
PSR3 R/W SCTL14[3] SCTL14[2] SCTL14[1] SCTL14[0] SCTL13[3] SCTL13[2] SCTL13[1] SCTL13[0]
PSR4 R/W SCTL16[3] SCTL16[2] SCTL16[1] SCTL16[0] SCTL15[3] SCTL15[2] SCTL15[1] SCTL15[0]
PSR5 R/W SCTL18[3] SCTL18[2] SCTL18[1] SCTL18[0] SCTL17[3] SCTL17[2] SCTL17[1] SCTL17[0]

Table 72. Memory Map Bit Descriptions

Bit Description Values
GPIOx GPIOx pin control Write:
0: GPIOx pin pull-down on
1: GPIOx pin pull-down off (default)
Read:
0: GPIOx pin at Logic 0
1: GPIOx pin at Logic 1
REFON Reference powered up 1: reference remains powered up until watchdog timeout
0: reference shuts down after conversions (default)
DTEN Discharge timer enable (read on- 0: disables discharge timer
ly)
1: enables the discharge timer for discharge switches
ADCOPT ADC mode option bit 0: selects modes 27 kHz, 7 kHz, 422 Hz or 26 Hz with MD, Bits[1:0] in ADC conversion commands (default)
1: selects modes 14 kHz, 3 kHz, 1 kHz, or 2 kHz with MD, Bits[1:0] in ADC conversion commands
VUV Undervoltage comparison volt- Comparison voltage = (VUV + 1) × 16 × 100 μV, default: VUV = 0x000
age1
VOV Overvoltage comparison voltage1 Comparison voltage = VOV × 16 × 100 μV, default: VOV = 0x000
DCC[x] Discharge Cell x x = 1 to 18:
1: turn on shorting switch for Cell x
0: turn off shorting switch for Cell x (default)
x = 0:
1: turn on GPIO9 pull-down
0: turn off GPIO9 pull-down (default)
DCTO Discharge time out value DCTO (write) 0 1 2 3 4 5 6 7 8 9 A B C D E F
Time (minutes) Disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120
DCTO (read) 0 1 2 3 4 5 6 7 8 9 A B C D E F
Time left (mi- Disabled 0 to 0.5 1 to 2 to 3 to 4 to 5 to 10 15 20 30 40 60 75 90
nutes) or time- 0.5 to 1 2 3 4 5 10 to to to to to to to to
out 15 20 30 40 60 75 90 120

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Data Sheet ADBMS1818
MEMORY MAP

Table 72. Memory Map Bit Descriptions

Bit Description Values
MUTE Mute status (read only) 1: mute is activated and discharging is disabled
0: mute is deactivated
FDRF Force digital redundancy failure 1: forces the digital redundancy comparison for ADC conversions to fail
0: enables the normal redundancy comparison
PS, Bits[1:0] Digital redundancy path selection 11: redundancy is applied only to the ADC3 digital path
10: redundancy is applied only to the ADC2 digital path
01: redundancy is applied only to the ADC1 digital path
00: redundancy is applied sequentially to the ADC1, ADC2, and ADC3 digital paths during cell conversions and applied
to ADC1 during AUX and STATUS conversions
DTMEN Enable discharge timer monitor 1: enables the discharge timer monitor function if the DTEN pin is asserted
0: disables the discharge timer monitor function. The normal discharge timer function is enabled if the DTEN pin is
asserted
CxV Cell x voltage1 x = 1 to 18
16-bit ADC measurement value for Cell x
Cell voltage for Cell x = CxV × 100 μV
CxV is rest to 0xFFFF on power-up and after clear command
GxV GPIO x voltage1 x = 1 to 9
16-bit ADC measurement value for GPIOx
Voltage for GPIOx = GxV × 100 μV
GxV is reset to 0xFFFF on power-up and after clear command
REF 2nd reference voltage1 16-bit ADC measurement value for 2nd reference
SC Sum of all cells measurement1 16-bit ADC measurement value of the sum of all cell voltages, sum of all cells voltage = SC × 100 μV × 30
ITMP Internal die temperature1 16-bit ADC measurement value of the internal die temperature, temperature measurement voltage = ITMP × 100
μV/7.6mV/°C − 276°C
VA Analog power supply voltage1 16-bit ADC measurement value of the analog power supply voltage, analog power supply voltage = VA × 100 μV, the
value of VA is set by external components that must be in the range of 4.5 V to 5.5 V for normal operation
VD Digital power supply voltage1 16-bit ADC measurement value of the digital power supply voltage, digital power supply voltage = VD × μV, normal
range is within 2.7 V to 3.6 V
CxOV Cell x overvoltage flag x = 1 to 18
Cell voltage compared to VOV comparison voltage
0: cell x not flagged for overvoltage condition
1: cell x flagged
CxUV Cell x undervoltage flag x = 1 to 18
Cell voltage compared to VUV comparison voltage
0: cell x not flagged for undervoltage condition
1: cell x flagged
REV Revision code Device revision code
RSVD Reserved bits Read: read back value can be 1 or 0
RSVD0 Reserved bits Read: read back value is always 0
RSVD1 Reserved bits Read: read back value is always 1
MUXFAIL Multiplexer self test result Read:
0: multiplexer passed self test
1: multiplexer failed self test
THSD Thermal shutdown status Read:
0: thermal shutdown has not occurred

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Data Sheet ADBMS1818
MEMORY MAP

Table 72. Memory Map Bit Descriptions

Bit Description Values
1: thermal shutdown has occurred, THSD Bit cleared to 0 on read of Status Register Group B
SCTx[x] S pin control bits 0000: drive S pin high (deasserted)
0001: send 1 high pulse on S pin
0010: send 2 high pulses on S pin
0011: send 3 high pulses on S pin
0100: send 4 high pulses on S pin
0101: send 5 high pulses on S pin
0110: send 6 high pulses on S pin
0111: send 7 high pulses on S pin
1xxx: drive S pin low (asserted)
PWMx[x] PWM discharge control 0000: selects 0% discharge duty cycle if DCCx = 1 and watchdog timer has expired
0001: selects 6.7% discharge duty cycle if DCCx = 1 and watchdog timer has expired
0010: selects 13.3% discharge duty cycle if DCCx = 1 and watchdog timer has expired
...
1110: selects 93.3% discharge duty cycle if DCCx = 1 and watchdog timer has expired
1111: selects 100% discharge duty cycle if DCCx = 1 and watchdog timer has expired
ICOMn Initial communication bits Write I2C 0110 0001 0000 0111
Start Stop Blank No trans-
mit
SPI 1000 1010 1001 1111
CSB low CSB falling CSB high No trans-
edge mit
Read I 2C 0110 0001 0000 0111
Start from mas- stop from mas- SDA low be- SDA high
ter ter tween bytes between
bytes
SPI 0111 0001 0000 0111
Dn I2C/SPI communication data byte Data transmitted (received) to (from) I2C/SPI slave device
FCOMn Final communication control bits Write I2C 0000 1000 1001
Master ACK Master NACK Master NACK + stop
SPI X000 1001
CSB high
Read I 2C 0000 0111 1111 0001 1001
ACK from ACK from NACK ACK from NACK from
master slave from slave + slave + stop
slave stop from from master
master
SPI 1111
1 Voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits.

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

PROVIDING DC POWER

Simple Linear Regulator

The primary supply pin for the ADBMS1818 is the 5 V (±0.5 V)
VREG input pin. To generate the required 5 V supply for VREG,
the DRIVE pin can be used to form a discrete regulator with the
addition of a few external components, as shown in Figure 93. The
DRIVE pin provides a 5.7 V output, capable of sourcing 1 mA.
When buffered with an NPN transistor, the DRIVE pin provides a Figure 94. VREG Powered From Cell Stack with High Efficiency Regulator
stable 5 V over temperature. The NPN transistor must be chosen
to have a sufficient Beta over temperature (> 40) to supply the INTERNAL PROTECTION AND FILTERING
necessary supply current. The peak VREG current requirement of
the ADBMS1818 approaches 35 mA when simultaneously commu- Internal Protection Features
nicating over isoSPI and making ADC conversions. If the VREG pin
The ADBMS1818 incorporates various ESD safeguards to ensure
is required to support any additional load, a transistor with an even
robust performance. An equivalent circuit showing the specific
higher Beta may be required.
protection structures is shown in Figure 95. Zener- like suppressors
are shown with their nominal clamp voltage, and the unmarked
diodes exhibit standard PN junction behavior.

Filtering of Cell and GPIO Inputs

The ADBMS1818 uses a Δ-Σ ADC, which includes a Δ-Σ modulator
followed by a sinc3 finite impulse response (FIR) digital filter,
which greatly relaxes input filtering requirements. Furthermore, the
programmable oversampling ratio allows the user to determine
the best trade-off between measurement speed and filter cutoff fre-
Figure 93. Simple VREG Power Source Using NPN Pass Transistor quency. Even with this high order low-pass filter, fast transient noise
can still induce some residual noise in measurements, especially
The NPN collector can be powered from any voltage source that in the faster conversion modes. This noise can be minimized by
is a minimum 6 V above V–. This includes the cells that are being adding an RC, low-pass decoupling to each ADC input, which also
monitored, or an unregulated power supply. A 100 Ω, 100 nF helps reject potentially damaging high energy transients. Adding
RC decoupling network is recommended for the collector power more than about 100 Ω to the ADC inputs begins to introduce a
connection to protect the NPN from transients. The emitter of the systematic error in the measurement, which can be improved by
NPN must be bypassed with a 1 µF capacitor. Larger capacitance raising the filter capacitance or mathematically compensating in
must be avoided because this increases the wake-up time of the software with a calibration procedure. For situations that demand
ADBMS1818. Some attention must be given to the thermal charac- the highest level of battery voltage ripple rejection, grounded ca-
teristic of the NPN, as there can be significant heating with a high pacitor filtering is recommended. This configuration has a series
collector voltage. resistance and capacitors that decouple high frequency noise to
V–. In systems where noise is less periodic or higher oversampling
Improved Regulator Power Efficiency rates are in use, a differential capacitor filter structure is adequate.
In this configuration there are series resistors to each input, but
For improved efficiency when powering the ADBMS1818 from the the capacitors connect between the adjacent C pins. However,
cell stack, VREG can be powered from a dc-to-dc converter, rather the differential capacitor sections interact. As a result, the filter
than the NPN pass transistor. An ideal circuit is based on the response is less consistent and results in less attenuation than
LT8631 step-down regulator, as shown in Figure 94. A 100 Ω predicted by the RC, by approximately a decade. Note that the
resistor is recommended between the battery stack and the LT8631 capacitors only see one cell of applied voltage (thus smaller and
input, which prevents in-rush current when connecting to the stack lower cost) and tend to distribute transient energy uniformly across
and reduces conducted electromagnetic interference (EMI). The the IC (reducing stress events on the internal protection structure).
EN/UV pin must be connected to the DRIVE pin, which puts the Figure 96 shows the two methods schematically. ADC accuracy
LT8631 into a low power state when the ADBMS1818 is in the sleep varies with R and C as shown in the typical performance curves,
state. but the error is minimized if R = 100 Ω and C = 10 nF. The GPIO
pins always use a grounded capacitor configuration because the
measurements are all with respect to V–.

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

Figure 95. Internal ESD Protection Structures of the ADBMS1818

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

Figure 96. Input Filter Structure Configurations

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

Using Nonstandard Cell Input Filters ADCV command. Figure 98 shows the standard ADCV command
sequence. Figure 98 shows the recommended command sequence
A cell pin filter of 100 Ω and 10 nF is recommended for all applica- and timing that allow the mux to settle. The purpose of the modified
tions. This filter provides the best combination of noise rejection procedure is to allow the mux to settle at C1/C7/C13 before the
and TME performance. In applications that use C pin RC filters start of the measurement cycle. The delay between the C1/C7/C13
larger than 100 Ω and 10 nF, there may be additional measurement ADCV command and the all channel ADCV command is dependent
error. Figure 97 shows how both total TME and TME variation on the time constant of the RC being used. The general guidance
increase as the RC time constant increases. The increased error is to wait 6τ between the C1/C7/C13 ADCV command and the
is related to the mux settling. It is possible to reduce TME lev- all channel ADCV command. Figure 97 shows the expected TME
els to near data sheet specifications by implementing an extra when using the recommended command sequence.
single channel conversion before issuing a standard all channel

Figure 97. Cell Measurement TME

Figure 98. ADC Command Order

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

CELL BALANCING transistors. The ADBMS1818 includes an internal pull-up PMOS

transistor with a 1 kΩ series resistor. The S pins can act as digital
Cell Balancing with Internal MOSFETs outputs suitable for driving the gate of an external MOSFET, as
shown in Figure 99. Figure 96 shows external MOSFET circuits that
With passive balancing, if one cell in a series stack becomes over- include RC filtering. For applications with very low cell voltages, the
charged, an S output can slowly discharge this cell by connecting it PMOS in Figure 99 can be replaced with a PNP. When a PNP is
to a resistor. Each S output is connected to an internal N-channel used, the resistor in series with the base must be reduced.
MOSFET with a maximum on resistance of 10 Ω. An external
resistor must be connected in series with these MOSFETs to allow Choosing a Discharge Resistor
most of the heat to be dissipated outside of the ADBMS1818
package, as shown in Figure 99. When sizing the balancing resistor, it is important to know the
typical battery imbalance and the allowable time for cell balancing.
The internal discharge switches (MOSFETs) S1 through S18 can In most small battery applications, it is reasonable for the balancing
be used to passively balance cells as shown in Figure 99 with circuitry to be able to correct for a 5% state of charge (SOC) error
balancing current of 200 mA or less (80 mA or less if the die with 5 hours of balancing. For example, a 5 AHr battery with a 5%
temperature is over 85°C). Balancing current larger than 200 mA SOC imbalance has approximately 250 mA Hrs of imbalance. Using
is not recommended for the internal switches due to excessive a 50 mA balancing current, the error can be corrected in 5 hours.
die heating. When discharging cells with the internal discharge With a 100 mA balancing current, the error can be corrected in 2.5
switches, the die temperature must be monitored. See the Thermal hours. In systems with very large batteries, it is difficult to use pas-
Shutdown section. sive balancing to correct large SOC imbalances in short periods of
Note that the antialiasing filter resistor is part of the discharge path time. The excessive heat created during balancing generally limits
and must be removed or reduced. Use of an RC for added cell the balancing current. In large capacity battery applications, if short
voltage measurement filtering is permitted, but the filter resistor balancing times are required, an active balancing solution must
must remain small, typically around 10 Ω to reduce the effect on the be considered. When choosing a balance resistor, the following
balance current. equations can be used to help determine a resistor value:
Balance Current =
% of SOC Imbalance × Battery Capacity
Number of Hours to Balance

Balance Resistor =
Nominal Cell Voltage
Balance Current

Active Cell Balancing

Applications that require 1 A or greater of cell balancing current
must consider implementing an active balancing system. Active
balancing allows for much higher balancing currents without the
generation of excessive heat. Active balancing also allows for ener-
gy recovery since most of the balance current is redistributed back
to the battery pack. Figure 100 shows a simple active balancing
Figure 99. Internal/External Discharge Circuits implementation using the LT8584. The LT8584 also has advanced
features that can be controlled via the ADBMS1818. See the S Pin
Cell Balancing with External Transistors Pulsing Using the S Pin Control Settings section and the LT8584
data sheet for more details.
For applications that require balancing currents above 200 mA or
large cell filters, the S outputs can be used to control external

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Data Sheet ADBMS1818
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Figure 100. 18-Cell Battery Stack Module with Active Balancing

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

DISCHARGE CONTROL DURING CELL fast enough for the cell voltage to completely settle before the
MEASUREMENTS measurement starts. For the best measurement accuracy when
running discharge, the mute and unmute commands must be
If the discharge permitted (DCP) bit is high at the time of a cell used. The mute command can be issued to temporarily disable
measurement command, the S pin discharge states do not change all discharge transistors before the ADCV command is issued. After
during cell measurements. If the DCP bit is low, S pin discharge the cell conversion completes, an unmute command can be sent
states are disabled while the corresponding cell or adjacent cells to reenable all discharge transistors that were previously on. Using
are being measured. If using an external discharge transistor, the this method maximizes the measurement accuracy with a very
relatively low 1 kΩ impedance of the internal ADBMS1818 PMOS small time penalty.
transistors allow the discharge currents to fully turn off before the
cell measurement. Table 73 shows the ADCV command with DCP Method to Verify Discharge Circuits
= 0. In this table, off indicates that the S pin discharge is forced off
irrespective of the state of the corresponding DCC bit. On indicates When using the internal discharge feature, the ability to verify
that the S pin discharge remains on during the measurement period discharge functionality can be implemented in the software. In
if it was on prior to the measurement command. applications using an external discharge MOSFET, an additional
resistor can be added between the battery cell and the source of
In some cases, it is not possible for the automatic discharge the discharge MOSFET, which allows the system to test discharge
control to eliminate all measurement error caused by running the functionality.
discharges. This is due to the discharge transistor not turning off
Table 73. Discharge Control During an ADCV Command with DCP = 0
Cell Measurement Periods Cell Calibration Periods
Cell 1, Cell 2, Cell 3, Cell 1, Cell 2, Cell 3,
Cell 7, Cell 8, Cell 9, Cell 4, Cell Cell 5, Cell Cell 6, Cell Cell 7, Cell 8, Cell 9, Cell 4, Cell Cell 5, Cell Cell 6, Cell
Cell 13 Cell 14 Cell 15 10, Cell 16 11, Cell 17 12, Cell 18 Cell 13 Cell 14 Cell 15 10, Cell 16 11, Cell 17 12, Cell 18
Discharge Pin t0 to t1M t1M to t2M t2M to t3M t3M to t4M t4M to t5M t5M to t6M t6M to t1C t1C to t2C t2C to t3C t3C to t4C t4C to t5C t5C to t6C
S1 Off Off On On On Off Off Off On On On Off
S2 Off Off Off On On On Off Off Off On On On
S3 On Off Off Off On On On Off Off Off On On
S4 On On Off Off Off On On On Off Off Off On
S5 On On On Off Off Off On On On Off Off Off
S6 Off On On On Off Off Off On On On Off Off
S7 Off Off On On On Off Off Off On On On Off
S8 Off Off Off On On On Off Off Off On On On
S9 On Off Off Off On On On Off Off Off On On
S10 On On Off Off Off On On On Off Off Off On
S11 On On On Off Off Off On On On Off Off Off
S12 Off On On On Off Off Off On On On Off Off
S13 Off Off On On On Off Off Off On On On Off
S14 Off Off Off On On On Off Off Off On On On
S15 On Off Off Off On On On Off Off Off On On
S16 On On Off Off Off On On On Off Off Off On
S17 On On On Off Off Off On On On Off Off Off
S18 Off On On On Off Off Off On On On Off Off

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

Both circuits are shown in Figure 101. The functionality of the DIGITAL COMMUNICATIONS
discharge circuits can be verified by conducting cell measurements
and comparing measurements when the discharge is off to meas- PEC Calculation
urements when the discharge is on. The measurement taken when
the discharge is on requires that the discharge permit (DCP) bit The PEC can be used to ensure that the serial data read from the
be set. The change in the measurement when the discharge is ADBMS1818 is valid and has not been corrupted. This feature is
turned on is calculable based on the resistor values. The following critical for reliable communication, particularly in environments of
algorithm can be used in conjunction with Figure 101 to verify each high noise. The ADBMS1818 requires that a PEC be calculated for
discharge circuit: all data being read from and written to the ADBMS1818. For this
reason, it is important to have an efficient method for calculating the
► Step 1: Measure all cells with no discharging (all S outputs off) PEC.
and read and store the results.
► Step 2: Turn on S1, S7, and S13. The C code provides a simple implementation of a lookup table
derived PEC calculation method. There are two functions. The first
► Step 3: Measure C1 to C0, C7 to C6, and C13 to C12. function init_PEC15_Table() must only be called once when the
► Step 4: Turn off S1, S7, and S13. microcontroller starts and initializes a PEC15 table array called
► Step 5: Turn on S2, S8, and S14. pec15Table[]. This table is used in all future PEC calculations.
► Step 6: Measure C2 to C1, C8 to C7, and C14 to C13. The PEC15 table can also be hard coded into the microcontroller
► Step 7: Turn off S2, S8, and S14. rather than running the init_PEC15_Table() function at startup. The
► ... pec15() function calculates the PEC and returns the correct 15-bit
PEC for byte arrays of any given length.
► Step 17: Turn on S6, S12, and S18.
► Step 18: Measure C6 to C5, C12 to C11, and C18 to C17. /************************************
► Step 19: Turn off S6, S12, and S18. Copyright 2012 Analog Devices, Inc. (ADI)
► Step 20: Read the Cell Voltage Register Groups to get the
Permission to freely use, copy, modify, and distribute this software
results of Step 2 through Step 19.
for any purpose with or without fee is hereby granted, provided
► Step 21: Compare new readings with old readings. Each cell that the above copyright notice and this permission notice appear
voltage reading must have decreased by a fixed percentage set in all copies: THIS SOFTWARE IS PROVIDED “AS IS” AND ADI
by RDISCHARGE and RFILTER for internal designs and RDISCHARGE1 DISCLAIMS ALL WARRANTIES
and RDISCHARGE2 for external MOSFET designs. The exact
amount of the decrease depends on the resistor values and INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
MOSFET characteristics. AND FITNESS. IN NO EVENT SHALL ADI BE LIABLE FOR ANY
SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES
OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY
USE OF SAME, INCLUDING ANY LOSS OF USE OR DATA
OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLI-
GENCE OR OTHER TORTUOUS ACTION, ARISING OUT OF OR
IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
SOFTWARE.
***************************************/
int16 pec15Table[256];
int16 CRC15_POLY = 0x4599;
void init_PEC15_Table()
{
for (int i = 0; i < 256; i++)
Figure 101. Balancing Self Test Circuit
{
remainder = i << 7;
for (int bit = 8; bit > 0; --bit)
{

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

if (remainder & 0x4000) by the RB1 and RB2 resistors. The receiver threshold is half of the
voltage present on the ICMP pin.
{
The following guidelines must be followed when setting IB (100 μA
remainder = ((remainder << 1)); to 1 mA) and the receiver comparator threshold voltage VICMP/2:
remainder = (remainder ^ CRC15_POLY) RM = Transmission Line Cℎaracteristic
} Impedance Z0
else Signal Amplitude =
{ VA = 20 × IB × RM /2
remainder = ((remainder << 1)); Receiver Comparator Threshold (VTCMP) = K × VA
} Voltage on ICMP Pin (VCIMP) = 2 × VTCMP
} RB2 = VICMP/IB
pec15Table[i] = remainder&0xFFFF; RB1 = (2/IB) - (RB2)
} Select IB and K (signal amplitude VA to receiver comparator thresh-
old ratio) according to the application:
}
► For lower power links: IB = 0.5 mA and K = 0.5.
unsigned int16 pec15 (char *data , int len)
► For full power links: IB = 1 mA and K = 0.5.
{ ► For long links (>50m): IB = 1 mA and K = 0.25.
int16 remainder,address; For applications with little system noise, setting IB to 0.5 mA is a
remainder = 16;//PEC seed good compromise between power consumption and noise immuni-
ty. Using this IB setting with a 1:1 transformer and RM = 100 Ω,
for (int i = 0; i < len; i++) RB1 must be set to 3.01 k, and RB2 set to 1 kΩ. With a typical
{ CAT5 twisted pair, these settings allow communication up to 50 m.
For applications in very noisy environments or that require cables
address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate PEC table longer than 50 m, it is recommended to increase IB to 1 mA. Higher
address remainder = (remainder << 8 ) ^ pec15Table[address]; drive current compensates for the increased insertion loss in the
cable and provides high noise immunity. When using cables over
}
50 m and a transformer with a 1:1 turns ratio and RM = 100 Ω, RB1
return (remainder*2);//The CRC15 has a 0 in the LSB so the final is 1.5 k, and RB2 is 499 Ω.
value must be multiplied by 2
The maximum clock rate of an isoSPI link is determined by the
} length of the isoSPI cable. For cables 10 m or less, the maximum
1 MHz SPI clock frequency is possible. As the length of the cable
isoSPI IBIAS and ICMP Setup increases, the maximum possible SPI clock rate decreases. This
dependence is a result of the increased propagation delays that
The ADBMS1818 allows the isoSPI links of each application to can create possible timing violations. Figure 102 shows how the
be optimized for power consumption or for noise immunity. The maximum data rate reduces as the cable length increases when
power and noise immunity of an isoSPI system is determined by using a CAT5 twisted pair.
the programmed IB current, which controls the isoSPI signaling
currents. IB can range from 100 μA to 1 mA. Internal circuitry scales Cable delay affects three timing specifications: tCLK, t6, and t7. In
up this bias current to create the isoSPI signal currents equal to the electrical characteristics table, each of these specifications is
be 20 × IB. A low IB reduces the isoSPI power consumption in the derated by 100 ns to allow for 50 ns of cable delay. For longer
ready and active states, whereas a high IB increases the amplitude cables, the minimum timing parameters may be calculated as
of the differential signal voltage VA across the matching termination shown below:
resistor, RM. The IB current is programmed by the sum of the RB1 tCLK, t6, and t7 > 0.9 μs + 2 × tCABLE (0.2 m per ns)
and RB2 resistors connected between the 2 V IBIAS pin and GND,
as shown in Figure 103. The receiver input threshold is set by the
ICMP voltage that is programmed with the resistor divider created

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

Figure 102. Data Rate vs. Cable Length

Figure 103. isoSPI Circuit

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

Implementing a Modular isoSPI Daisy Chain the serial timing and affects data latency and throughput. The
maximum number of devices in an isoSPI daisy chain is strictly
The hardware design of a daisy-chain isoSPI bus is identical for dictated by the serial timing requirements. However, it is important
each device in the network due to the daisy-chain point to point to note that the serial read back time, and the increased current
architecture. The simple design as shown in Figure 103 is function- consumption, might dictate a practical limitation.
al, but inadequate for most designs. The termination resistor, RM,
must be split and bypassed with a capacitor, as shown in Figure For a daisy chain, the following two timing considerations for proper
104. This change provides both a differential and a common mode operation dominate (see Figure 86):
termination, and as such, increases the system noise immunity. 1. t6, the time between the last clock and the rising chip select,
must be long enough.
2. t5, the time from a rising chip select to the next falling chip
select (between commands), must be long enough.
Both t5 and t6 must be lengthened as the number of
ADBMS1818 devices in the daisy chain increases. The equa-
tions for these times are below:
t5 > (Number of Devices × 70 ns) + 900 ns, t6 > (Number of
Devices × 70 ns) + 950 ns

Connecting Multiple ADBMS1818s on the Same

PCB
Figure 104. Daisy Chain Interface Components When connecting multiple ADBMS1818 devices on the same PCB,
only a single transformer is required between the ADBMS1818
The use of cables between battery modules, particularly in hazard isoSPI ports. The absence of the cable also reduces the noise
applications, can lead to increased noise susceptibility in the com- levels on the communication lines and often only a split termination
munication lines. For high levels of electromagnetic interference is required. Figure 105 shows an example application that has
(EMC), additional filtering is recommended. The circuit example in multiple ADBMS1818 devices on the same PCB, communicating to
Figure 104 shows the use of common-mode chokes (CMC) to add the bottom MCU through an LTC6820 isoSPI driver. If a transformer
common-mode noise rejection from transients on the battery lines. with a center tap is used, a capacitor can be added for improved
The use of a center tapped transformer also provides additional noise rejection. Additional noise filtering can be provided with dis-
noise performance. A bypass capacitor connected to the center tap crete common-mode chokes (not shown) placed on both sides of
creates a low impedance for common-mode noise (see Figure 104). the single transformer.
Since transformers without a center tap can be less expensive, they
may be preferred. In this case, the addition of a split termination On single board designs with low noise requirements, it is possible
resistor and a bypass capacitor (see Figure 104) can enhance the for a simplified capacitor isolated coupling as shown in Figure 106
isoSPI performance. Large center tap capacitors greater than 10 nF to replace the transformer.
must be avoided as they may prevent the isoSPI common-mode
In this circuit, the transformer is directly replaced by two 10 nF
voltage from settling. Common-mode chokes similar to those used
capacitors. An optional CMC provides noise rejection similar to
in Ethernet or CANbus applications are recommended. Specific
application circuits using transformers. The circuit is designed to
examples are provided in Table 75.
use IBIAS and ICMP settings identical to the transformer circuit.
An important daisy chain design consideration is the number of
devices in the isoSPI network. The length of the chain determines

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

Figure 105. Daisy Chain Interface Components on Single Board

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

Figure 106. Capacitive Isolation Coupling for ADBMS1818s on the Same PCB

Connecting an MCU to an ADBMS1818 with an the receiver as the time the signal is above the threshold set at
isoSPI Data Link the ICMP pin. Slow rise and fall times cut into the timing margins.
Generally, it is best to keep pulse edges as fast as possible. When
The LTC6820 converts a standard 4-wire SPI into a 2-wire iso- evaluating transformers, it is also worth noting the parallel winding
SPI link that can communicate directly with the ADBMS1818. An capacitance. While transformers have very good CMRR at a low
example is shown in Figure 107. The LTC6820 can be used in frequency, this rejection degrades at higher frequencies, largely due
applications to provide isolation between the microcontroller and to the winding to winding capacitance. When choosing a transform-
the stack of ADBMS1818 devices. The LTC6820 also enables er, it is best to pick one with less parallel winding capacitance when
system configurations that have the battery management system possible.
(BMS) controller at a remote location relative to the ADBMS1818
devices and the battery pack. When choosing a transformer, it is equally important to pick a
device that has an adequate isolation rating for the application.
Transformer Selection Guide The working voltage rating of a transformer is a key specification
when selecting a device for an application. Interconnecting daisy-
As shown in Figure 103, a transformer or pair of transformers chain links between ADBMS1818 devices see <60 V stress in
isolates the isoSPI signals between two isoSPI ports. The isoSPI typical applications. Ordinary pulse and local area network (LAN)
signals have programmable pulse amplitudes up to 1.6 V p-p and type transformers suffice. Connections to the LTC6820, in general,
pulse widths of 50 ns and 150 ns. To be able to transmit these may need much higher working voltage ratings for good long-term
pulses with the necessary fidelity, the system requires that the reliability. Usually, matching the working voltage to the voltage of
transformers have primary inductances above 60 μH and a 1:1 the entire battery stack is conservative. Unfortunately, transformer
turns ratio. It is also necessary to use a transformer with less vendors often only specify one-second high voltage testing, and
than 2.5 μH of leakage inductance. In terms of pulse shape, the this is not equal to the long-term (permanent) rating of the device.
primary inductance mostly affects the pulse droop of the 50 ns For example, according to most safety standards, a 1.5 kV rated
and 150 ns pulses. If the primary inductance is too low, the pulse transformer is expected to handle 230 V continuously, and a 3
amplitude begins to droop and decay over the pulse period. When kV device is capable of 1100 V long-term, though manufacturers
the pulse droop is severe enough, the effective pulse width seen may not always certify to those levels (refer to actual vendor data
by the receiver drops substantially, reducing noise margin. Some for specifics). Usually, the higher voltage transformers are called
droop is acceptable as long as it is a relatively small percentage of high-isolation or reinforced insulation types by the suppliers. Table
the total pulse amplitude. The leakage inductance primarily affects 74 shows a list of transformers that have been evaluated in isoSPI
the rise and fall times of the pulses. Slower rise and fall times links.
effectively reduce the pulse width. Pulse width is determined by

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

In most applications, a CMC is also necessary for noise rejection.

Table 75 includes a list of suitable CMCs if the CMC is not already
integrated into the transformer being used.

Figure 107. Interfacing an ADBMS1818 with a μC Using an LTC6820 for Isolated SPI Control

Table 74. Recommended Transformers

Working Cent
Voltage er Width (with
Supplier Part Number Temperature Range (VWORKING) VHIPOT/60 sec Tap CMC Height Length Leads) Pins AEC-Q200
Recommended Dual Transformers
Pulse HX1188FNL –40°C to 85°C 60 V 1.5 kV rms Yes Yes 6.0 mm 12.7 9.7 mm 16SMT No
(estimate) mm
Pulse HX0068ANL –40°C to 85°C 60 V 1.5 kV rms Yes Yes 2.1 mm 12.7 9.7 mm 16SMT No
(estimate) mm
Pulse HM2100NL –40°C to 105°C 1000 V 4.3 kV dc No Yes 3.4 mm 14.7 14.9 mm 10SMT Yes
mm
Pulse HM2112ZNL –40°C to 125°C 1000 V 4.3 kV dc Yes Yes 4.9 mm 14.8 14.7 mm 12SMT Yes
mm
Sumida CLP178-C20114 –40°C to 125°C 1000 V 3.75 kV rms Yes Yes 9 mm 17.5 15.1 mm 12SMT No
(estimate) mm
Sumida CLP0612-C20115 600 V rms 3.75 kV rms Yes No 5.7 mm 12.7 9.4 mm 16SMT No
mm
Wurth 7490140110 –40°C to 85°C 250 V rms 4 kV rms Yes Yes 10.9 24.6 17.0 mm 16SMT No
mm mm
Wurth 7490140111 0°C to 70°C 1000 V 4.5 kV rms Yes No 8.4 mm 17.1 15.2 mm 12SMT No
(estimate) mm
Wurth 749014018 0°C to 70°C 250 V rms 4 kV rms Yes Yes 8.4 mm 17.1 15.2 mm 12SMT No
mm
Halo TG110-AE050N5LF –40°C to 85/125°C 60 V 1.5 kV rms Yes Yes 6.4 mm 12.7 9.5 mm 16SMT Yes
(estimate) mm
Recommended Single Transformers
Pulse PE-68386NL –40°C to 130°C 60 V 1.5 kV dc No No 2.5 mm 6.7 mm 8.6 mm 6SMT No
(estimate)
Pulse HM2101NL –40°C to 105°C 1000 V 4.3 kV dc No Yes 5.7 mm 7.6 mm 9.3 mm 6SMT Yes
Pulse HM2113ZNL –40°C to 125°C 1600 V 4.3 kV dc Yes Yes 3.5 mm 9 mm 15.5 mm 6SMT Yes
Wurth 750340848 –40°C to 105°C 250 V 3 kV rms No No 2.2 mm 4.4 mm 9.1 mm 4SMT No
Halo TGR04-6506V6LF –40°C to 125°C 300 V 3 kV rms Yes No 10 mm 9.5 mm 12.1 mm 6SMT No
Halo TGR04-A6506NA6NL –40°C to 125°C 300 V 3 kV rms Yes No 9.4 mm 8.9 mm 12.1 mm 6SMT Yes
Halo TDR04-A550ALLF –40°C to 105°C 1000 V 5 kV rms Yes No 6.4 mm 8.9 mm 16.6 mm 6TH Yes

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Data Sheet ADBMS1818
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Table 74. Recommended Transformers

Working Cent
Voltage er Width (with
Supplier Part Number Temperature Range (VWORKING) VHIPOT/60 sec Tap CMC Height Length Leads) Pins AEC-Q200
TDK ALT4532V-201-T001 –40°C to 105°C 60 V ~1 kV Yes No 2.9 mm 3.2 mm 4.5 mm 6SMT Yes
(estimate)
Sumida CEEH96BNP- –40°C to 125°C 600 V 2.5 kV rms No No 7 mm 9.2 mm 12.0 mm 4SMT No
LTC6804/11
Sumida CEP99NP-LTC6804 –40°C to 125°C 600 V 2.5 kV rms Yes No 10 mm 9.2 mm 12.0 mm 8SMT No
Sumida ESMIT-4180/A –40°C to 105°C 250 V rms 3 kV rms No No 3.5 mm 5.2 mm 9.1 mm 4SMT Yes
TDK VGT10/9EE-204S2P4 –40°C to 125°C 250 V 2.8 kV rms Yes No 10.6 10.4 12.7 mm 8SMT No
(estimate) mm mm

Table 75. Recommended Common-Mode Chokes

Manufacturer Part Number
TDK ACT45B-101-2P
Murata DLW43SH101XK2

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

isoSPI Layout Guidelines connected cell or left open. The unused S pins can simply be left
disconnected.
The layout of the isoSPI signal lines also plays a significant role in
maximizing the noise immunity of a data link. The following layout Alternatively, to optimize measurement synchronization in applica-
guidelines are recommended: tions with fewer than 18 cells, the unused C pins can be equally
distributed between the top of the third mux (C18), the top of the
1. The transformer must be placed as close to the isoSPI cable second mux (C12) and the top of the first mux (C6) (see Figure
connector as possible. The distance must be kept less than 2 108). If the number of cells being measured is not a multiple
cm. The ADBMS1818 must be placed close to but at least 1 cm of three, the top mux(es) must have fewer cells connected. The
to 2 cm away from the transformer to help isolate the IC from unused cell inputs must be tied to the other unused inputs on the
magnetic field coupling. same mux and connected to the battery stack through a 100 Ω
2. A V– ground plane must not extend under the transformer, resistor. The unused inputs result in a reading of 0.0 V for those
the isoSPI connector, or in between the transformer and the cells.
connector.
3. The isoSPI signal traces must be as direct as possible while Current Measurement with a Hall-Effect Sensor
isolated from adjacent circuitry by ground metal or space. No
traces must cross the isoSPI signal lines, unless separated by a The ADBMS1818 auxiliary ADC inputs (GPIO pins) may be used
ground plane on an inner layer. for any analog signal, including active sensors with 0 V to 5
V analog outputs. For battery current measurements, Hall-effect
System Supply Current sensors provide an isolated, low power solution. Figure 109 shows
schematically a typical Hall-effect sensor that produces two outputs
The ADBMS1818 has various supply current specifications for the that proportion to the VCC provided. The sensor in Figure 109 has
different states of operation. The average supply current depends two bidirectional outputs centered at half of VCC. CH1 is a 0 A to 50
on the control loop in the system. It is necessary to know which A low range and CH2 is a 0 A to 200 A high range. The sensor is
commands are being executed each control loop cycle, and the powered from a 5 V source and produces analog outputs that are
duration of the control loop cycle. With this information, it is possible connected to the GPIO pins or inputs of the mux application shown
to determine the percentage of time the ADBMS1818 is in the in Figure 111. The use of GPIO1 and GPIO2 as the ADC inputs
measure state versus the low power sleep state. The amount has the possibility of being digitized within the same conversion
of isoSPI or SPI communication also affects the average supply sequence as the cell inputs (using the ADCVAX command), thus
current. synchronizing cell voltage and cell current measurements.
Table 76. Daisy Chain Serial Time Equations
Calculating Serial Throughput
Data Bytes
For any given ADBMS1818, the calculation to determine communi- Command CMD Bytes + Data PEC Communication
cation time is simple: it is the number of bits in the transmission Type + CMD PEC per IC Total Bits Time
multiplied by the SPI clock period being used. The control protocol Read 4 8 (4 + (8 × #ICs)) × 8 Total bits × clock
of the ADBMS1818 is uniform. Therefore, almost all commands can period
be categorized as a write or read operation. Table 76 can be used Write 4 8 (4 + (8 × #ICs)) × 8 Total bits × clock
to determine the number of bits in a given ADBMS1818 command. period
Operation 4 0 4 × 8 = 32 32 × clock period
ENHANCED APPLICATIONS

Using the ADBMS1818 with Fewer than 18

Cells
Cells can be connected in a conventional bottom (C1) to top (C18)
sequence with all unused C inputs either shorted to the highest

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

Figure 108. Cell Connection Schemes for 16 Cells and 14 Cells

Figure 109. Interfacing a Typical Hall-Effect Battery Current Sensor to Auxiliary ADC Inputs

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Data Sheet ADBMS1818
APPLICATIONS INFORMATION

READING EXTERNAL TEMPERATURE ments to 16 different signals (Figure 111). The GPIO1 ADC input
PROBES is used for measurement and mux control is provided by the I2C
port on GPIO4 and GPIO5. The buffer amplifier is selected for fast
Figure 110 shows the typical biasing circuit for a negative tempera- settling and increases the usable throughput rate.
ture coefficient (NTC) thermistor. The 10 kΩ at 25°C is the most
popular sensor value and the VREF2 output stage is designed to
provide the current required to bias several of these probes. The
biasing resistor is selected to correspond to the NTC value so the
circuit provides 1.5 V at 25°C (VREF2 is 3 V nominal). The overall
circuit response is approximately –1%/°C in the range of typical cell
temperatures, as shown in the chart of Figure 110.

Expanding the Number of Auxiliary

Measurements
The ADBMS1818 has nine GPIO pins that can be used as ADC
inputs. In applications that need to measure more than nine signals, Figure 110. Typical Temperature Probe Circuit and Relative Output
a mux circuit can be implemented to expand the analog measure-

Figure 111. Mux Circuit Supports 16 Additional Analog Measurements

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Data Sheet ADBMS1818
TYPICAL APPLICATION

Figure 112. Typical Application Circuit

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Data Sheet ADBMS1818
RELATED DEVICES

Table 77. Related Devices

Model Description Comments
LTC6811-1/LTC6811-2 4th generation 12-cell battery stack Measures cell voltages for up to 12 series battery cells. Daisy-chain capability allows multiple devices to be
monitor and balancing IC. connected to measure many battery cells simultaneously via the built-in 1 MHz, 2-wire isoSPI. Includes capability
for passive cell balancing.
LTC6820 isoSPI isolated communications Provides an isolated interface for SPI communication up to 100 meters, using a twisted pair. Companion to the
interface. LTC6804-1, LTC6806, LTC6811-1, LTC6812-1, LTC6813-1, and ADBMS1818.
LTC6812-1 4th generation 15-cell battery stack Measures cell voltages for up to 15 series battery cells. The isoSPI daisy-chain capability allows multiple devices
monitor and balancing IC. to be interconnected to measure many battery cells simultaneously. The isoSPI bus can operate up to 1 MHz and
can be operated bidirectionally for fault conditions, such as a broken wire or connector. Includes internal passive
cell balancing capability of up to 200 mA.
LTC6813-1 4th generation 18-cell battery stack Automotive/industry application, measures cell voltages for up to 18 series battery cells. The isoSPI daisy-chain
monitor and balancing IC. capability allows multiple devices to be interconnected to measure many battery cells simultaneously. The isoSPI
bus can operate up to 1 MHz and can be operated bidirectionally for fault conditions, such as a broken wire or
connector. Includes internal passive cell balancing capability of up to 200 mA with a wider temperature range
compared to the ADBMS1818.

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Data Sheet ADBMS1818
OUTLINE DIMENSIONS

Figure 113. 64-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]
(05-08-1982)
Dimensions shown in millimeters

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Data Sheet ADBMS1818
OUTLINE DIMENSIONS

Figure 114. 64-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]
(SW-64-2)
Dimensions shown in millimeters

Updated: July 27, 2021

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Packing Quantity Option
ADBMS1818ASWZ -40°C to +85°C 64-Lead LQFP_EP Tray, 160 05-08-1982
ADBMS1818ASWZ-R7 -40°C to +85°C 64-Lead LQFP_EP Reel, 300 05-08-1982
ADBMS1818ASWZ-RL -40°C to +85°C 64-Lead LQFP_EP Reel, 1500 05-08-1982
ADBMS1818ASWAZ -40°C to +85°C 64-Lead LQFP_EP Tray, 160 SW-64-2
ADBMS1818ASWAZ-R7 -40°C to +85°C 64-Lead LQFP_EP Reel, 300 SW-64-2
ADBMS1818ASWAZ-RL -40°C to +85°C 64-Lead LQFP_EP Reel, 1500 SW-64-2
1 Z = RoHS Compliant Part.

EVALUATION BOARDS
Model1 Description
EVAL-ADBMS1818Z Evaluation Board
1 Z = RoHS Compliant Part.

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