HP8559A Operating An Service Manual
HP8559A Operating An Service Manual
SPECTRUM ANALYZER
Hewlett-Packard Company certifies that this product met its published specifications at the time o f
shipment from the factory. Hewlett-Packard further certij?es that its calibration measurements are
traceable to the United States National Bureau of Standards, to the extent allowed b y the Bureau's
calibration facility. and t o the calibration facilities of other International Standards Organization
members.
WARRANTY
This Hewlett-Packard instrument product is warranted against defects in material and workmanship
for a period of one year from date of shipment. During the warranty period, Hewlett-Packard Com-
pany will, at its option, either repair or replace products which prove to be defective.
For warranty service or repair, this product must be returned to a service facility designated by HP.
Buyer shall prepay shipping charges to HP and HP shall pay shipping charges t o return the product t o
Buyer. However, Buyer shall pay all shipping charges, duties, and taxes for products returned to HP
from another country.
HP warrants that its software and firmware designated by HP for use with an instrument will execute
its programming instructions when properly installed on that instrument. HP does not warrant that the
operation of the instrument, or software, or firmware will be uninterrupted or error free.
LIMITATION 0F WARRANTY
The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance
by Buyer, Buyer-supplied software or interfacing, unauthorized modification or misuse, operation
outside of the environmental specifications for the product, or improper site preparation or main-
tenance.
EXCLUSIVE REMEDIES
THE REMEDIES PROVIDED HEREIN ARE BUYER'S SOLE AND EXCLUSIVE REMEDIES. HP
SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSE-
QUENTIAL DAMAGES, WHETHER BASED ON CONTRACT, TORT, OR ANY OTHER LEGAL
THEORY.
ASSISTANCE
Product maintenance agreements and other customer assistance agreements are available for Hewlett-
Packard products.
For any assistance, contact your nearest Hewlett-Packard Sales and Sewice Office. Addresses are
provided at the back of this manual.
HEWLETT
PACKARD
8559A
SPECTRUM ANALYZER
0.1 - 21 GHz
SERIAL NUMBERS
ii
CONTENTS
SAFETY SYMBOLS
The following safety symbols are used throughout this manual and in the instrument. Familiarize
yourself with each of the symbols and its meaning before operating this instrument.
Instruction manual symbol. The instrument will be marked with this symbol
when it is necessary for the user to refer to the instruction manual in order to
protect the instrument against damage. Location of pertinent information
within the manual is indicated by use of this symbol in the table of contents.
There are voltages at many points in the instrument which can, if contacted,
cause personal injury. Be extremely careful. Any adjustments or service pro-
cedures that require operation of the instrument with protective covers
removed should be performed only by trained service personnel.
SPECTRUM ANALYZER
ADAPTER SIDE STOP K I T OVERLAY K I T
1250-0780 08558-60131 5060-0319
SECTION I
GENERAL INFORMATION
SERIAL NUMBER
1-22. ACCESSORIES SUPPLIED
1-16. Manual Updating Supplement 1-25. Three graticule overlays provide the operator
with reference-level labels for the CRT. H P Part
1-17. An instrument manufactured after the print- Number 5020-8565 is the overlay for H P 180-series
ing of this manual might have a serial number prefix display mainframes. H P Part Number 5020-8566 is
that is not listed on the title page. This unlisted serial the overlay for H P 181-series display mainframes.
number prefix indicates the instrument is different H P Part Number 5020-8567 is the overlay for H P
from those described in this manual. The manual for 182-series display mainframes. For proper installa-
this newer instrument is accompanied by a yellow tion of the graticule overlay, refer to Section II.
MODEL 8559A GENERAL INFORMATION
SPECIFICATIONS
Average N o i ~ Level
e Frequency Response
The displayed average noise level determines Frequency response, measured with 0 or 10 dB
sensitivity (minimum discernible signal). Signals input attenuation, includes input attenuator flat-
at this input level peak approximately 3 dB ness, mixer flatness, and band-to-band ampli-
above the displayed noise. tude variation:
Maximum average noise level with 1 kHz resolu-
Frequency Response
tion bandwidth, 0 dB input attenuation, and Frequency Band GHz ( + dB MAX.)
video filter at MAX (detent): 01 - 3 10
6- 9 10
Frequency Harmonic Average Noise
3- 9 15
Band (GHz) Mode Level (dBrn)
9- 15 18
01 - 3 1- - 111
6- 15 21
6- 9 1 + - 108 121 - 18 23
3- 9 2- - 103 18 - 21 30
9- 15 2 + - 98
6- 15 3- - 93
121- 18 3 + - 92
18 - 21 3+ - 90
lnput Attenuator
Calibrated Display Range 0 dB to 70 dB of input attenuation selectable in 10-
Log (from Reference Level): dB steps
70 dB with 10 dB/DIV Amplitude Scale Step Accuracy:
8 dB with 1 dB/DIV Amplitude Scale 0 dB to 60 dB, 0.01 to 18.0 GHz: <k 1.0 dB
Linear: per 10-dB step
8 divisions with LIN Amplitude Scale Maximum Cumulative Step Error:
0 dB to 60 dB, 0.01 to 18.0 GHz: < k 2.4 dB
AMPLITUDE ACCURACY
With AUTO sweep time selected, amplitude accu- Bandwidth Switching (Amplitude Variation)
racy is determined by one or more of the following Bandwidths 3 MHz to 300 kHz: < k 0.5 dB
factors, depending on the measurement technique.' Bandwidths 3 MHz to 1 kHz: < + 1.O dB
DIMENSIONS
I
201.6
17 15/16) I! TOP 1-1
Note:
Dimensions in millimeten
and (inches).
34.9 498.5 (19 5 1 8 ) -
(17 13116)-4
I
200 11 TOP^-]
(7 7/01 [
Note
Dlmenr~onrIn m~lllmeterr
and Imches)
Note:
Dimensions in millimeters 38 1$L
5
3
0 (21 1,4)-~
and (~nches). +l11/2) p-491.9(193/4-q
C R E A R (11 3/01
Note:
Dimensions in millimeters and (inches).
~- E I rack
A height (including filler strip) d
for cabinet height (including feet)
add 0 15/16) to EIA rack height.
TOP
Note:
Dimensions in mtllorneters
and (inches).
MODEL 8559A GENERAL INFORMATION
SUPPLEMENTAL CHARACTERISTICS
NOTE: Values in this table are not specifications. They are typical characteristics
included for user information.
Spectral Resolution
The following graph shows typical spectrum Frequency (GHzl
SUPPLEMENTAL CHARACTERISTICS
NOTE: Values in this table are not specifications. They are typical characteristics
included for user information.
FRONT PANEL INPUT AND OUTPUT 'Rear panel outputs refer to 180T-series display main-
CHARACTERISTICS frames and other 180-series mainframes with Option 807
installed. Horizontal, vertical, and blanking outputs,
SIGNAL INPUT attenuated and shifted in dc level, are available on other
180-series mainframes at the MAIN SWEEP, MAIN
lnput Impedance GATE, and DELAYED GATE outputs, respectively. DO
50 ohms nominal; Precision Type N female NOT connect an X-Y recorder to the DELAYED GATE
connector. OUTPUT, or damage will result.
MODEL 8559A GENERAL INFORMATION
SUPPLEMENTAL CHARACTERISTICS
NOTE: Values in this table are not specifications. They are typical characteristics
included for user information.
1-26. EQUIPMENT REQUIRED BUT NOT SUP- response flatness is degraded by less than &0.5 dB
PLIED from 100 MHz to 12.4 GHz; the limiter is usable
from 10 MHz to 18 GHz. Invut levels of 1 watt aver-
1-27. Display Mainframe age or 75 watts peak can be tolerated.
1-28. An HP 853A digital Spectrum Analyzer Dis- 1.35. Low Pass Filter
play is recommended for use with the HP 8559A.
The rear panel of the HP 853A mainframe provides
the following output connections: HORIZ
(SWEEP), VERTICAL (VIDEO), BLANK
(PENLIFT), 21.4 MHz IF, and HP-IB interface con-
nector.
1-41. SERVICE ACCESSORIES 1-44. Table 1-4 lists all of the equipment required
for testing, adjusting and troubleshooting the
1-42. Service accessories are shown in Figure 1-6. Hewlett-Packard Model 8559A Spectrum Analyzer.
Other equipment may be substituted if it meets or
1-43. RECOMMENDED TEST EQUIPMENT exceeds the critical specifications listed in the table.
GENERAL INFORMATION MODEL 8559A
Instrument Recommended
Critical Specifications Use*
Model
Recommended
instrument Critical Specifications Use"
Model
Recommended
Instrument Critical Specifications Use*
Model
Recommended
Instrument Critical Specifications Model
SECTION II
INSTALLATION AND OPERATION VERIFICATION
2-12. To install side stops: 4. Place label on front panel of spectrum analyzer
(upper right-hand corner) to indicate that the
plug-in is secured with side stops.
--
2-23. The instrument may be stored or shipped in Use enough shock-absorbing material (3-inch to
environments within the following limits: 4-inch layer) around all sides of the instrument
to provide firm cushion and prevent movement
Temperature: - 40°C to + 75°C inside the container. Protect the control panel
Altitude: <7620 meters (25,000 feet) with cardboard.
The instrument should also be protected from tem- Seal the shipping container securely.
perature extremes which cause condensation within
the instrument. Mark the shipping container FRAGILE to
assure careful handling.
2-24. Packaging
2-27. OPERATION VERIFICATION
2-25. Original Packaging. Containers and
materials identical to those used in factory packaging 2-28. The Operation Verification tests only the
are available through Hewlett-Packard offices. If the most critical specifications and operating features of
instrument is being returned to Hewlett-Packard for the instrument. It requires much less time and equip-
servicing, attach a tag indicating the type of service ment than the complete performance tests provided
required, return address, model number, and full in Section IV, and is recommended for verification of
serial number. A supply of these tags is provided at overall instrument operation, either as part of
the end of this section. Also mark the container incoming inspection or after repair. Operation Verifi-
FRAGILE to assure careful handling. In any corre- cation consists of the following performance tests:
spondence, refer to the instrument by model number
and full serial number. Paragraph 4-11, Frequency Span Accuracy
2-26. Other Packaging. The following general Paragraph 4- 17, Average Noise Level
instructions should be used for repackaging with
commercially available materials: Paragraph 4-21, Bandwidth Switching (Arnpli-
tude Variation)
1. Wrap the instrument in heavy paper or plastic.
If shipping to a Hewlett-Packard office or serv- Paragraph 4-22, Input Attenuator Accuracy
ice center, attach a tag indicating the type of
service required, return address, model number, Paragraph 4-25, Calibrator Accuracy
and full serial number. A supply of these tags is
provided at the end of this section. Paragraph 4-26, Display Fidelity
MODEL 8559A INSTALLATION AND OPERATION VERIFICATION
CARTON- OUTER
FOAM PADS-INNER
MANUAL PAD- FRONT
CARTON- INNER
BAG-ANTISTATIC
SECTION Ill
OPERATION
3-3. The HP 8559A Spectrum Analyzer plug-in can 3-11. CONTROLS, INDICATORS, AND CON-
be used with either the 180-series display mainframes NECTORS
or the HP 853A Spectrum Analyzer Display main-
frame. 3-12. Control Grouping
TUNING
3-10. The HP 853A has limited HP-IB capabilities. FREQUENCY BAND GHz
CRT trace and graticule data is dumped directly to a ALT IF
listen-only HP-IB plotter by pressing two front-panel SIG IDENT
push buttons. Control settings on the spectrum ana- RESOLUTION BW
lyzer plug-in cannot be monitored via the HP-IB; FREQ SPAN/DIV
OPERATION MODEL 8559A
3-19. The amplitude group enables the operator to The spectrum analyzer and any device
measure signal amplitude in units of either voltage or connected to it must be connected to
dBm. power line ground. Failure to ensure
proper grounding could result in a
3-20. OPERATING PRECAUTIONS shock hazard to personnel or damage
to the instrument.
3-21. Signal lnput
3-25. LINE power is switched at the display main-
3-22. The HP 8559A Spectrum Analyzer plug-in is frame front panel. A safety indicator lights when the
a sensitive measuring instrument. Overloading the ac power is on. NEVER remove a spectrum analyzer
input with too much power, peak voltage, or dc volt- plug-in from the display mainframe without first
age will permaner:tly damage the input circuits. Do switching the ac LINE power switch to OFF
not exceed the input levels specified below:
3-26. For optimum performance, you should allow
the spectrum analyzer to warm up for at least 30
Maximum lnput (Damage) Levels minutes before using it to make measurements.
HP 8559A
Total Power:
+ 20 dBm (0.1 W, 2.2 Vrms) with 0 dB input 3-27. FRONT-PANEL ADJUSTMENT PROCE-
attenuation DURE
+ 30 dBm (1W, 7.1 Vrms) with 110 dB input
attenuation 3-28. The front-panel adjustment procedure adapts
the H P 8559A Spectrum Analyzer plug-in to a par-
dcorac(<100 Hz): k7.1V ticular display mainframe, and should be performed
daily after instrument warm-up. The step-by-step
Peak Pulse Power: + 50 dBm (100W, >lOpsec adjustment is also an excellent way for new users to
pulse width, 0.01% duty cycle) with L30 dB input become acquainted with the various spectrum ana-
attenuation lyzer controls. Once the procedure is completed, the
MODEL 8559A OPERATION
spectrum analyzer is calibrated for absolute ampli- Press and release the PLOT GRAT push button
tude and frequency measurements. Set the controls four times to step to digital test routine #4, as
as shown in Table 1 before you start the adjustment indicated by the "#4" displayed on the left side
procedure. of the CRT.
TABLE 1. ADJUSTMENT SElllNGS With an adjustment tool, adjust the FOCUS
--
control as necessary to make the characters on
Function Setting
the CRT as clear as possible.
Spectrum Analyzer Plug-In Adjust the X POSN and Y POSN controls the
align the square trace pattern with the outer-
INPUT ATTEN (dB)* 10 dB
most CRT graticule lines.
REFERENCE LEVEL 0 dBm
Option 002 +50 dBmV
Momentarily press the PLOT GRAT and
REF LEVEL FINE 0 dBm
PLOT TRACE push buttons simultaneously to
Amplitude Scale LIN
exit the digital test routines.
FREQ SPANIDIV 10 MHz (uncoupled)
RESOLUTION BW 1 MHz (uncoupled)
SWEEP TIMEIDIV AUTO 3-30. Display Adjustments - HP 180-Series
SWEEP TRIGGER FREE RUN Display Mainframe
START-CENTER CENTER
(8558B, 8557A) 1. With an adjustment tool, adjust the VERTI-
FREQUENCY BAND GHz CAL POSN control to place the CRT trace on
(8559A) a horizontal graticule line near the CRT center.
TUNING >60 MHz
BASELINE CLIPPER OFF 2. Reduce the INTENSITY and set the SWEEP
VIDEO FILTER OFF TIME/DIV control to MAN. Use the MAN
SWEEP knob to center the CRT dot.
*On older plug-ins, set
OPTIMUM INPUT to
-30 dBm.
--
3-31. Frequency and Amplitude Adjustments Connect the 250 MHz CAL OUTPUT to the
spectrum analyzer input, and center the signal
Adjust VERTICAL POSN to align the CRT on the CRT with the TUNING control. The
trace with the bottom graticule line. FREQUENCY MHz readout will indicate 250
MHz -t 3 MHz.
Center the LO feedthrough (i.e., the "signal" at
0 MHz) on the CRT with the TUNING control. Press the LIN Amplitude Scale push button.
Adjust the REF LEVEL FINE control to place
Narrow the FREQ SPAN/DIV to 200 kHz. the signal peak at the top CRT graticule line.
Adjust the REF LEVEL FINE control as neces-
sary to position the signal peak near the top
CRT graticule line. Press the 10 dB/DIV Amplitude Scale push
button. Adjust VERTICAL GAIN to place the
Center the LO feedthrough again, if necessary, signal peak at the top CRT graticule line.
and adjust the FREQ ZERO to calibrate the
FREQUENCY MHz readout at 00.0 MHz. Repeat steps 8 and 9 until the signal peak
remains at the top CRT graticule line when the
Set the FREQ SPAN/DIV control to 1 MHz Amplitude Scale is alternated between 10 dB/
and the REF LEVEL FINE control to 0. DIV and LIN.
Adjust the TUNING control for a FRE-
QUENCY MHz readout of approximately 250 Set the REF LEVEL FINE control to 0, and the
MHz. REFERENCE LEVEL control to - 30 dBm
( + 20 dBmV for Option 002 instruments).
Press the 10 dB/DIV Amplitude Scale push
button, and set the REFERENCE LEVEL con- Press the LIN Amplitude Scale push button,
trol to - 20 dBm ( + 30 dBmV for Option 002 and adjust REF LEVEL CAL to place the sig-
instruments). nal peak at the top CRT graticule line.
MODEL 8559A PERFORMANCE TESTS
SECTION IV
PERFORMANCE TESTS
4-2. The procedures in this section test the electrical 4-4. Since a compatible display mainframe is
performance of the instrument using the specifica- required for operation of the HP Model 8559A Spec-
tions in Section I as the performance standards. The trum Analyzer plug-in, the specifications listed in
performance tests included in this section are listed in Table 1-1 apply when both instruments are function-
Table 4-1. Most of the tests can be performed with- ing together. Consequently, the performance tests in
out access to the interior of the instrument. If a test this section verify the proper operation of both the
measurement is marginal, perform the appropriate HP 8559A and the display mainframe.
adjustment procedures in Section V.
PERFORMANCE TESTS
NOTE
SPECIFICATION:
There are 14 calibrated spans ranging from 10 kHz per division to 200 MHz per division in a 1, 2, 5 sequence.
Frequency error between-any twopoints on the display is within +. 5 percent of the indicated frequency separa-
tion.
DESCRIPTION:
Wide span widths are checked using the 100-, lo-, and 1-MHz outputs of a comb generator. Narrow span widths
are checked using the output of a comb generator modulated by a function generator. Since the comb generator
produces frequency components separated by a precisely determined frequency interval, the resultant spectral
lines displayed on the CRT are evenly spaced when no span error exists in the instrument. Thus, span error is the
cumulative variation of distance among the spectral line intervals displayed across the CRT. The amount of span
error is determined by comparing the distance of the first nine graticule divisions with the displayed distance of
the corresponding spectral line intervals.
SPECTRUM
ANALYZER
QENERATOR
FREQUENCY FUNCT l ON
COUNTER QENERATOR
/ \
000 000
0 0 000
-0'
p -
0 O
0::.oooq
HIGH UODUL
i ------
BNC TEE
EQUIPMENT:
PERFORMANCE TESTS
PROCEDURE:
Spectrum Analyzer:
Comb Generator:
Function Generator:
2. Connect equipment as shown in Figure 4-1 but do not connect function generator to comb generator.
PERFORMANCETESTS MODEL 8559A
PERFORMANCE TESTS
Adjust spectrum analyzer TUNING control to position one spectral line (from comb generator) at first
graticule line (left-hand edge of display). Measure the error between 17th spectral line and 9th graticule line
as shown in Figure 4-2. Error should be no greater than +0.4 division.
110.4 DIVISION
div
COMB SIGNALS
CENTERFREQUENCY
Set FREQ SPAN/DIV to 100 MHz. Adjust TUNING control to position one spectral line on the first
graticule line. Measure the error between ninth spectral line and ninth graticule line. Error should be no
greater than + 0.4 division.
div
Set FREQ SPAN/DIV to 50 MHz. Adjust TUNING control to position one spectral line on the first
graticule line. Measure the error between fifth spectral line and ninth graticule line. Error should be no
greater than k 0.4 division.
div
Set comb generator COMB FREQUENCY - MHz for 10-MHz comb. Set spectrum analyzer FREQ
SPAN/DIV to 20 MHz. Adjust TUNING control to position one spectral line on the first graticule line.
Measure the error between 17th spectral line and ninth graticule line as shown in Figure 4-3. Error should
be no greater than k 0.4 division.
div
Set FREQ SPAN/DIV to 10 MHz. Adjust TUNING control to position one spectral line on the first
graticule line. Measure the error between ninth spectral line and ninth graticule line. Error should be no
greater than k 0.4 division.
div
MODEL 8559A PERFORMANCETESTS
PERFORMANCE TESTS
COMB SIGNALS
CENTERFREQUENCY
Set FREQ SPAN/DIV to 5 MHz. Adjust TUNING control to position one spectral line on the first
graticule line. Measure the error between fifth spectral line and ninth graticule line. Error should be no
greater than +0.4 division.
div
Set comb generator COMB FREQUENCY- MHz for 1-MHz comb and increase OUTPUT AMPLI-
TUDE control to maximum setting. Set spectrum analyzer FREQ SPAN/DIV to 2 MHz. Adjust TUN-
ING control to position one spectral line on the first graticule line. Measure the error between 17th spectral
line and ninth graticule line. Error should be no greater than k 0.4 division.
div
Set FREQ SPAN/DIV to I MHz. Adjust TUNING control to position one spectral line at first graticule
line. Measure the error between ninth spectral line and ninth graticule line. Error should be no greater than
+0.4 division.
div
Set FREQ SPAN/DIV to 500 kHz. Adjust TUNING control to position one spectral line on the first
graticule line. Measure the error between fifth spectral line and ninth graticule line. Error should be no
greater than + 0.4 division.
div
Set comb generator COMB FREQUENCY- MHz for 10-MHz comb. Adjust spectrum analyzer TUN-
ING to position an in-band spectral line on the center graticule line (use SIC IDENT if necessary).
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
NOTE
To obtain a clean comb on the spectrum analyzer display, use either the
LOW or HIGH output of the function generator and readjust the OUTPUT
LEVEL control as necessary.
14. Set spectrum analyzer FREQ SPAN/DIV to 200 kHz. Adjust TUNING control to position one spectral
line on the first graticule line. Measure the error between ninth spectral line and ninth graticule line. Error
should be no greater than k0.4division.
div
15. Using the procedure of NOTE in step 13, vary spectrum analyzer FREQ SPAWDIV and function genera-
tor output frequency in accordance with Table 4-2. Adjust spectrum analyzer TUNING control to position
one spectral line on the first graticule line. Measure the span error between ninth spectral line and ninth
graticule line.
NOTE
PERFORMANCE TESTS
SPECIFICATION:
An external RF source is used to provide a frequency-calibrated input signal to the spectrum analyzer for three
points on each frequency band. The digital FREQUENCY GHz readout is compared with the known test
frequency to find the amount of readout (or tuning) error. The 10 dB attenuator is necessary to reduce LO
emission from the spectrum analyzer to the frequency counter when using the sweep oscillator.
SPECTRUM
ANALYZER
SWEEP RF FREQUENCY
OSCILLATOR PLUG- IN COUVFR
INPUT 1
-
CABLE ASSY
COMB (Re-214fU)
GENERATOR
! - -POWER
. . -- -
S P L I T T E R1
ADAPTER
--------- f7
! CABLE ASSY
~~~~~T~~ (Re-91111''
IbVNNCbI UlnCbILl
I TO A N A L Y Z E R )
I
ADAPTER ADAPTER
NOTE
The HP 8350A Sweep Oscillator may be substituted for the HP 8620C in this
procedure.
EQUIPMENT
PERFORMANCE TESTS
PROCEDURE:
Connect CAL OUTPUT signal of spectrum analyzer to INPUT 5W. Adjust TUNING control to position
signal at center graticule line of display. Adjust FREQ CAL potentiometer for a FREQUENCY GHz
display of 0.035.
Adjust spectrum analyzer TUNING control to center 10-MHz comb tooth. FREQUENCY GHz readout
should indicate:
Set comb generator COMB FREQUENCY - MHz for 100 MHz comb. Set spectrum analyzer FREQ
SPAN/DIV to 1 MHz, and adjust TUNING control to position 1.5-GHz comb tooth at center graticule
line of display. FREQUENCY GHz readout should indicate:
PERFORMANCE TESTS
8. Adjust sweep oscillator for CW output at 3.000 GHz, as measured by frequency counter. Vary POWER
LEVEL control as required for accurate measurement. Adjust spectrum analyzer TUNING control to
center signal on display. FREQUENCY GHz readout should indicate:
Min. Actual Max.
9. Using procedure of step 8, check spectrum analyzer tuning accuracy at remaining frequencies listed in
Table 4-3. Indication on FREQUENCY GHz readout must fall within corresponding test limits at each
frequency.
NOTE
Use SIG IDENT to verify that spectrum analyzer is tuned to desired in-band
signal response whenever tuning error appears excessive.
PERFORMANCE TESTS
4-13. RESIDUAL FM
SPECIFICATION:
Less than 2 kHz peak-to-peak for a time interval 10.1 second; less than 2 kHz peak-to-peak in a 180-series
display mainframe with 220/240 line voltage.
DESCRIPTION:
This test measures the inherent short-term instability (residual FM) of the LO system in the spectrum analyzer.
A stable signal (supplied by a comb generator) is applied to the spectrum analyzer input and slope-detected with
the linear portion of the 10-kHz bandwidth filter in zero span (fixed-tuned receiver - see Figure 4-6). Variations
of the spectrum analyzer's LO frequency (residual FM) can be measured as an amplitude shift on the CRT
display (1 kHz = 0.7 major division with LIN Amplitude Scale).
SPECTRUM
ANALYZER
COMB
GENERATOR
P P
ADAPTER ADAPTER
PROCEDURE:
1. Set equipment controls as follows:
Spectrum Analyzer:
FREQUENCYBANDGHz .................................................. .01-3
TUNING .............................................................. 3.000GHz
FREQUENCY SPAN/DIV .................................................. 100 kHz
RESOLUTIONBW ........................................................ lOkHz
INPUT ATTEN ............................................................. 30 dB
REFERENCELEVEL .................................................... -20dBm
REFLEVELFINE .............................................................. 0
Amplitudescale .............................................................. LIN
SWEEPTIME/DIV ........................................................ AUTO
SWEEPTRIGGER ..................................................... FREERUN
ALTIF ..................................................................... OFF
SIGIDENT ................................................................. OFF
BLCLIP .................................................................... OFF
VIDEOFILTER ............................................................. OFF
MODEL 8559A PERFORMANCETESTS
PERFORMANCE TESTS
Comb Generator:
2. Connect OUTPUT of comb generator to spectrum analyzer INPUT 50Qas shown in Figure 4-5.
NOTE
3. Adjust spectrum analyzer TUNING control to display 3.0 GHz signal produced by comb generator.
Adjust REFERENCE LEVEL and REF LEVEL FINE controls to position peak of signal at top graticule
line.
4. Keep 3.0 GHz signal centered on CRT with TUNING control while reducing FREQ SPAN/DIV to zero.
6. Slightly readjust spectrum analyzer FINE TUNING control until trace appears between fourth and
seventh graticule lines. Peak-to-peak variation of trace should not exceed 1.4 vertical division for each
horizontal division (see Figure 4-7).
div
NOTE
For 2201240 line voltages, peak-to-peak variation of trace should not exceed
1.4 vertical divisions (2 kHz) in a 180-series display mainframe.
AMPLITUDE
VARIATION OF
I F SIGNAL
FREQUENCY VARIATION
OF I F SIGNAL
PERFORMANCE TESTS
SPECIFICATION:
Noise sidebands are at least 70 dB below a CW signal, 30 kHz or more away from the signal with a 1 kHz
resolution bandwidth and full video filtering.
DESCRIPTION:
A stable 1.8 GHz CW signal is applied at a - 20 dBm level to the spectrum analyzer and displayed on the CRT
The amplitudes of noise-associated sidebands and unwanted responses near the signal are measured.
SPECTRUM
ANALYZER
COMB
QENERATOR
I
INPUT 50ll
ADAPTER
P ADAPTER
PROCEDURE:
1. Set equipment controls as follows:
Spectrum Analyzer:
FREQUENCYBANDGHz .................................................. .01-3
TUNING ................................................................ 1.8GHz
FREQSPAN/DIV .......................................................... l M H z
RESOLUTION BW ............................................... 30 kHz, uncoupled
INPUTATTEN .............................................................. OdB
REFERENCELEVEL .................................................... -20dBm
REFLEVELFINE .............................................................. 0
Amplitudescale ........................................................ 10dB/DIV
SWEEPTIME/DIV ........................................................ AUTO
SWEEPTRIGGER ..................................................... FREERUN
ALTIF ..................................................................... OFF
SIG IDENT ................................................................. OFF
BLCLIP .................................................................... OFF
VIDEOFILTER ............................................................. OFF
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
Comb Generator:
Adjust REFERENCE LEVEL and REF LEVEL FINE controls to position peak of 1.8-GHz signal at top
graticule line.
Decrease FREQ SPAN/DIV to 20 kHz and RESOLUTION BW to 1 kHz. Adjust TUNING as necessary
to keep signal centered.
Position signal at center of display. Set VIDEO FILTER control fully clockwise (not in MAX detent
position). Measure noise sidebands existing more than 1.5 divisions (30 kHz) from 1.8-GHz signal. Noise
sidebands should be more than 70 dB (7 divisions) down from top graticule line.
div. down
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
SPECIFICATION:
Individual resolution bandwidth 3-dB points are calibrated to +15% (+ 30% for 3 MHz bandwidth).
DESCRIPTION:
Resolution bandwidth accuracy is measured in the linear mode to eliminate log amplifier errors. Since signal
level at the 3-dB points (half-power points) is related to peak signal level by a voltage ratio of 0.707:1.O, a peak
level of 7.1 vertical divisions on the spectrum analyzer display gives a half-power level of 5 vertical divisions:
X div
-
= (7.1)(0.707)
5 div
In the 30-, lo-, 3-, and l-kHz bandwidths, a 21.4 MHz signal (final IF) is injected directly into Bandwidth Filter
No. 1 Assembly A1 1 to provide the stability required for measurement of narrow resolution bandwidths.
SPECTRUM
ANALYZER
SIGNAL GENERATOR
ADAPTER
P P ADAPTER
FIGURE 4-9. RESOLUTION BANDWIDTH ACCURACY TEST SETUP, 3 MHz TO 100 kHz
EQUIPMENT:
PERFORMANCE TESTS
PROCEDURE:
Part of this test must be performed with power supplied to the instrument
and with protective covers removed. The test should be performed only by
sewice-trained personnel who are aware of the hazards involved.
Spectrum Analyzer:
Signal Generator:
3. Adjust spectrum analyzer TUNING control to locate peak of 35-MHz signal on CRT. Reduce signal
generator output if necessary.
NOTE
4. Adjust signal generator OUTPUT LEVEL to position trace at 7.1 divisions above graticule baseline.
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
5. Tune signal generator frequency until trace drops to 5 divisions above graticule baseline. Record signal
generator frequency.
MHz
6. Tune signal generator frequency in direction opposite to that of step 5 until trace peaks (7.1 divisions above
graticule baseline) and then drops to 5 divisions above graticule baseline. Record signal generator fre-
quency.
MHz
NOTE
The bandwidths recorded in this performance test are required for calcula-
tions in 4-16 Resolution Bandwidth Selectivity performance test.
7. Calculate and record resolution bandwidth at 3-dB points (difference between frequencies recorded in
steps 5 and 6).
Min. Actual Max.
8. Select ALT IF (switch pushed in), leaving FREQ SPAWDIV set to 0. Set signal generator to 35 MHz and
repeat steps 3 through 7.
Min. Actual Max.
3.90 MHz
9. Return ALT IF switch to OFF position. Set RESOLUTION BW to 1 MHz, leaving FREQ SPAN/DIV set
to 0. Set signal generator to 35 MHz and repeat steps 3 through 7.
Min. Actual Max.
10. Set RESOLUTION BW to 300 kHz, leaving FREQ SPAN/DIV set to 0. Set signal generator to 35 MHz
and repeat steps 3 through 7.
Min. Actual Max.
345 kHz
11. Set RESOLUTION BW to 100 kHz, leaving FREQ SPAN/DIV set to 0. Set signal generator to 35 MHz
and repeat steps 3 through 7.
Min. Actual Max.
115 kHz
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
D l SPLAY
SIGNAL GENERATOR
.
RF OUTPUT
In the following procedure, the plug-in must be removed from the display
mainframe and connected through the extender cable assembly. Be very
careful; the energy at some points in the instrument will, if contacted, cause
personal injury. This test should be performed only by a skilled person who
knows the hazard involved.
Spectrum Analyzer:
PERFORMANCE TESTS
Signal Generator:
OUTPUTLEVEL ......................................................
For early instruments that do not feature A16J3, a 21.4-MHz signal can be
injected directly into the 300-MHz output (A1OJ1) of Third Converter Assem-
bly A10. Set the signal generator OUTPUT LEVEL to 0 dBm and use the
spectrum analyzer REFERENCE LEVEL and REF LEVEL FINE controls in
step 14 (=- 40 dBm) to position the trace at 7.1 divisions above the graticule
baseline.
Adjust signal generator frequency until spectrum analyzer trace is at peak. Set signal generator OUTPUT
LEVEL to position trace at 7.1 divisions above graticule baseline. Set COUNTER MODE to EXPAND
XlOO (most significant digit will overflow).
Tune signal generator frequency until trace drops to 5 divisions above graticule baseline. Record signal
generator frequency.
MHz
Tune signal generator frequency in direction opposite to that of step 15 until trace peaks (7.1 divisions
above graticule baseline) and then drops to 5 divisions above graticule baseline. Record signal generator
frequency.
MHz
Calculate and record resolution bandwidth at 3-dB points (difference between frequencies recorded in
steps 15 and 16).
Set RESOLUTION BW to 10 kHz, leaving FREQ SPAWDIV set to 0.Repeat steps 14 through 17.
PERFORMANCE TESTS
19. Set RESOLUTION BW to 3 kHz, leaving FREQ SPAN/DIV set to 0. Repeat steps 14 through 17.
Min. Actual Max.
20. Set RESOLUTION BW to 1 kHz, leaving FREQ SPAN/DIV set to 0. Repeat steps 14 through 17.
21. Leave signal generator connected to A16J3 if continuing on with next performance test.
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
SPECIFICATION:
The 60-dB bandwidth is measured for all resolution bandwidths. The 60- to 3-dB resolution bandwidth ratio
(shape factor) is then computed for each bandwidth by dividing the 3-dB value (from the Resolution Bandwidth
Accuracy test) into the 60-dB value.
In the 30-, lo-, 3-, and 1-kHz bandwidths, a 21.4-MHz signal (final IF) is injected into Bandwidth Filter No. 1
Assembly A l l to provide the stability required for the measurement of narrow resolution bandwidths.
D l SPLAY
S I G N A L GENERATOR
RF OUTPUT
ADAPTER
CABLE ADAPTER
L
In the following procedure, the plug-in must be removed from the display
mainframe and connected through the extender cable assembly. Be very
careful; the energy at some points in the instrument will, if contacted, cause
personal injury. This test should be performed only by a skilled person who
knows the hazard involved.
EQUIPMENT:
SignalGenerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HP8640B
Extender Cable Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H P 5060-0303
Adapter, SMB (f) to BNC (f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H P 1250-1236
Adapter, Type N (m) to BNC (f) (2 required) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H P 1250-0780
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
PROCEDURE:
Spectrum Analyzer:
Signal Generator:
NOTE
For early instruments that do not feature A16J3, a 321.4 MHz, - 25 dBm
signal can be injected directly into the input of Third Converter Assembly
A10 at blue cable A1OW1. Set signal generator COUNTER MODE to EXPAND
XI00 (most significant digit will overflow).
3. Adjust signal generator frequency until spectrum analyzer trace is at peak. Put signal generator OUTPUT
LEVEL to position trace at top graticule line.
4. Tune signal generator until trace drops to 2 divisions above graticule baseline. Record signal generator
frequency.
MHz
4-21
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
5. Tune signal generator in direction opposite to that of step 4 until trace peaks (top graticule line) and then
drops to 2 divisions above graticule baseline. Record signal generator frequency.
MHz
6. Calculate and record resolution bandwidth at 60-dB points (difference between frequencies recorded in
steps 4 and 5).
kHz
7. Set RESOLUTION BW to 3 kHz, leaving FREQ SPAN/DIV set to 0. Repeat steps 3 through 6.
kHz
8. Set RESOLUTION BW to 10 kHz, leaving FREQ SPAN/DIV set to 0. Repeat steps 3 through 6.
kHz
9. Set RESOLUTION BW to 30 kHz, leaving FREQ SPAN/DIV set to 0. Repeat steps 3 through 6.
kHz
10. Disconnect signal generator from A16J3. Set the display's LINE power to OFF and remove extender cable
assembly. Install plug-in in mainframe and set LINE power to ON.
Spectrum Analyzer:
PERFORMANCE TESTS
Signal Generator:
SPECTRUM
ANALYZER
SIGNAL GENERATOR
RF OUTPUT
I I INPUT
ADAPTER
t t ADAPTER
Adjust spectrum analyzer TUNING to locate peak of 35-MHz signal on CRT Reduce signal generator
output if necessary.
Adjust signal generator OUTPUT LEVEL to position trace at top graticule line.
Tune signal generator frequency until trace drops to 2 divisions above graticule baseline. Record signal
generator frequency.
MHz
Tune signal generator frequency in direction opposite to that of step 16 until trace peaks (top graticule line)
and then drops to 2 divisions above graticule baseline. Record signal generator frequency.
MHz
Calculate and record resolution bandwidth at 60-dB points (difference between frequencies recorded in
steps 16 and 17).
kHz
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
Set RESOLUTION BW to 300 kHz, leaving FREQ SPAN/DIV set to 0.Repeat steps 14 through 18.
kHz
Set RESOLUTION BW to 1 MHz, leaving FREQ SPAWDIV set to 0. Repeat steps 14 through 18.
MHz
Select ALT IF (switch pushed in). Set RESOLUTION BW to 3 MHz, leaving FREQ SPAN/DIV set to 0.
Repeat steps 14 through 18.
MHz
Return ALT IF switch to OFF position. With RESOLUTlON BW still in 3 MHz and FREQ SPAN/DIV
set to 0, repeat steps 14 through 18.
MHz
In Table 4-4, record 3-dB bandwidths computed in 4-15 Resolution Bandwidth Accuracy test.
For each resolution bandwidth, divide 60-dB bandwidth by 3-dB bandwidth to obtain Resolution Band-
width Ratio. Each ratio should be less than 15: 1.
3 MHz
3 MHz (ALT IF)
1 MHz
300 kHz
1 1
100 kHz
10 kHz
3;
MODEL 8559A PERFORMANCETESTS
PERFORMANCE TESTS
SPECIFICATION:
The maximum average noise level for each frequency band, with 1 kHz resolution bandwidth and 0 dB attenua-
tion, is given in Table 4-5.
DESCRIPTION:
The average noise level of the spectrum analyzer is checked by observing the average noise power level displayed
on the CRT when no input signal is applied to the instrument.
AVERAGE NOISE
POWER LEVEL
EQUIPMENT:
NOTE
The HP 853A Spectrum Analyzer Display may be substituted for the HP
181T/TR in this procedure.
NOTE
This test can be performed with no input termination if INPUT ATTEN is set
to 20 dB. Note that the input attenuation must then be taken into consider-
ation in establishing the equivalent REFERENCE LEVEL control setting for
the measurement. A REFERENCE LEVEL setting of -40 dBm with 20 dB
INPUT ATTEN is equivalent to a REFERENCE LEVEL setting of - 60 dBm
with 0 dB INPUT ATTEN.
PERFORMANCETESTS MODEL 8559A
PERFORMANCE TESTS
PROCEDURE:
2. With FREQ SPAN/DIV set to F, set VIDEO FILTER fully clockwise, but not in detent. Adjust TUNING
to position marker at frequency where displayed average noise level is highest.
NOTE
Measure average noise level displayed on CRT (see Figure 4-13) and record results in Table 4-5.
Set FREQUENCY BAND GHz to 12.1 -21 and repeat steps 2 through 5 for the frequency range of
12.1 - 18.0 GHz.
MODEL 8559A PERFORMANCETESTS
PERFORMANCE TESTS
NOTE
11. Repeat steps 2 through 5 for the frequency range of 18.0- 21.0 GHz.
PERFORMANCE TESTS
SPECIFICATION:
Residual responses are less than - 90 dBm (0.01 - 3.06 GHz) with 0 dB input attenuation and no signal present
at input. They are less than - 90 dBm (0.025 - 3.06 GHz) with ALT IF selected.
DESCRIPTION:
Signals present on the display without an input signal applied to the spectrum analyzer are residual responses.
The .Ol - 3 GHz frequency band is checked for residual responses greater than - 90 dBm.
EQUIPMENT:
NOTE
The HP 853A Spectrum Analyzer Display may be substituted for the HP
181TKR in this procedure.
NOTE
This test can be performed with no input termination if INPUT ATTEN is set
to 20 dB. Note that the input attenuation must then be taken into consider-
ation in establishing the equivalent REFERENCE LEVEL control setting for
the measurement. A REFERENCE LEVEL setting of - 40 dBm with 20 dB
INPUT ATTEN is equivalent to a REFERENCE LEVEL setting of - 60 dBm
with 0 dB INPUT ATTEN.
PROCEDURE:
PERFORMANCE TESTS
Adjust TUNING control to position LO feedthrough signal on leftmost vertical graticule line.
Set RESOLUTION BW control to 10 kHz, leaving FREQ SPAN/DIV set to 10 MHz. Adjust BL CLIP
control clockwise until just the peaks of the noise are displayed. Set the SWEEP TRIGGER control to
SINGLE and display PERSISTENCE control to MAX.
Set display to WRITE and momentarily press ERASE. Turn SWEEP TRIGGER control clockwise to
trigger a single sweep, adjusting BL CLIP and display INTENSITY controls until just the peaks of the
noise are displayed. Press ERASE and trigger another sweep.
Set display to VIEW and check for residual responses greater than -90 dBm. Record frequency and
amplitude of residual response with the greatest amplitude.
GHz
dBm
NOTE
7. Increase TUNING control setting in 100-MHz increments and use procedure of steps 5 - 7 to check for
residual responses from 10 MHz to 3.060 GHz (25 MHz - 3.060 GHz with ALT IF selected).
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
--
SPECIFICATION:
Frequency response measured with 0 or 10 dB of input attenuation includes input attenuator flatness, mixer
flatness, and band-to-band amplitude variation. Table 4-6 shows the frequency response specifications.
TABLE 48. FREQUENCY RESPONSE SPEClFiCATiONS
Frequency Response
FREQUENCY BAND (GHz)
(*dB Maximum)
DESCRIPTION:
Frequency response is checked in each frequency band. With the spectrum analyzer set to full sweep, an RF
input signal is very slowly swept across the entire frequency band. The resulting display is a series of narrow
signals that vary in height across the CRT. Since the RF source is leveled and held flat across each frequency
band, variations in amplitude on the display represent variations in the frequency response of the spectrum
analyzer. Leveling within reasonable limits becomes difficult from 18 GHz to 21 GHz, so the RF output at the
power splitter is characterized and compensated for when making the measurement of this frequency range.
SPECTRUM RF RF
ANALYZER WEEP Pf.!?-/: PLUO- I N
( 2 TO
OSCILLATOR 2.4QHz) 21 QHzl
POWER
METER
0; ;*=:
O
o o
INPUT 50
ATTENUATOR
SENSOR ! ADAPTER
ADAPTER
SPL l TTER
(CONNECTS
D l RECTLY
TO 20 dB
ATTENUATORI
ADAPTER
t
I
FIGURE 4-14. FREQUENCY RESPONSE TEST SETUP
MODEL 8559A PERFORMANCETESTS
PERFORMANCE TESTS
The HP 853A Spectrum Analyzer Display is not recommended for use in this
procedure.
The HP 8350A Sweep Oscillator may be substituted for the HP 8620C in this
procedure, if necessary.
EQUIPMENT:
PROCEDURE:
Spectrum Analyzer:
PERFORMANCE TESTS
Sweep Oscillator:
2. Center LO feedthrough signal on CRT with spectrum analyzer TUNING control. Adjust FREQ CAL for
a FREQUENCY GHz readout of 0.000.
Using 0.01 - 2.4 GHz sweep oscillator plug-in, connect equipment as shown in Figure 4-14. Connect
output of power splitter, through 20-dB attenuator, to spectrum analyzer input. Turn sweep oscillator RF
power ON and adjust ALC GAIN control for leveled output indication.
NOTE
Use maximum possible ALC GAIN to avoid leveling errors during swept
measurements.
MODEL 8559A PERFORMANCETESTS
PERFORMANCE TESTS
4. Adjust spectrum analyzer TUNING control for a FREQUENCY GHz readout of 0.100. Set sweep oscilla-
tor to CW with frequency of 100 MHz and use CW control to center signal on spectrum analyzer display.
5. Calibrate and zero power sensor and meter. Disconnect power splitter from 20-dB attenuator and connect
to power sensor. Adjust sweep oscillator POWER LEVEL control for a power meter indication of - 8
dBm.
6. Connect output of power splitter through 20-dB attenuator directly (do not use cable) to spectrum analyzer
input. Select Amplitude Scale setting of 1 dB/DIV, and adjust REF LEVEL FINE control as necessary to
place peak of 100 MHz signal at center horizontal graticule line of spectrum analyzer display.
7. Adjust spectrum analyzer TUNING control for a FREQUENCY GHz readout of 0.060. Adjust sweep
oscillator CW control for 60 MHz signal, centered on spectrum analyzer display.
8. Set sweep oscillator AF control for 100 MHz sweep. Adjust spectrum analyzer display PERSISTENCE
control fully clockwise. Adjust sweep oscillator SWEEP TIME vernier for slow sweep (30 seconds or
longer) and trigger a sweep. Record greatest positive and greatest negative deviation of signal peaks from
center horizontal graticule line (10 MHz to 110 MHz).
Maximum divisions
Minimum divisions
9. Adjust spectrum analyzer TUNING control for a FREQUENCY GHz readout of 0.100. Set sweep oscilla-
tor to CW with frequency of 100 MHz and use CW control to center signal on spectrum analyzer display.
10. Set spectrum analyzer FREQ SPAN/DIV control to F (full band) and RESOLUTION BW control to 3
MHz. Adjust TUNING control fully clockwise to position tuning marker at high end of selected frequency
band. Adjust REF LEVEL FINE control as necessary to place peak of 100 MHz signal (near LO feed-
through signal) at center horizontal graticule line of spectrum analyzer display.
11. Set sweep oscillator for FULL BAND (10 MHz to 2.4 GHz) and trigger a sweep. Record greatest positive
and greatest negative deviation of signal peaks from center horizontal graticule line (10 MHz to 2.4 GHz).
Record deviation of signal peak located at 8th vertical graticule line (approximately 2.1 GHz).
Maximum divisions
Minimum divisions
8th graticule line divisions
12. Remove 0.01 - 2.4 GHz RF Plug-in from sweep oscillator mainframe and replace with 2- 22 GHz RF
Plug-in. Select band 4 (2.0 - 22 GHz) on HP 8620C sweep oscillator.
13. Set sweep oscillator to CW with frequency of 2.1 GHz and use CW control to position signal on 8th
vertical graticule line of spectrum analyzer display. Adjust ALC GAIN control for leveled sweep oscillator
output and adjust POWER LEVEL control to place signal peak at same amplitude measured in step 11.
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
Use maximum possible ALC GAIN to avoid leveling errors during swept
measurements.
Do not adjust spectrum analyzer REF LEVEL FINE control or sweep oscillam
tor POWER LEVEL control during the remaining steps of this performance
test.
14. Adjust spectrum analyzer TUNING control fully counterclockwise to position tuning marker at low end
of selected frequency band. Set sweep oscillator CW control to 2.5 GHz and AF control for 1 GHz sweep.
Trigger a sweep, and record greatest positive and greatest negative deviation of signal peaks from center
horizontal graticule line (2 GHz to 3 GHz).
Maximum divisions
Minimum divisions
NOTE
It is normal for the HP 8559A to exhibit baseline lift with an input signal at
approximately 3.0075 GHz(2.9925 with ALT IF selected). Adjust sweep oscil-
lator sweep range as necessary to avoid baseline lift during frequency
response measurements.
If frequency response appears out of specification near a band edge, use a
frequency counter with sweep oscillator in CW to ensure the frequency in
question is within the specified band.
15. Compare values recorded in steps 8, 11, and 14, and record overall greatest positive and greatest negative
deviation from center horizontal graticule line for entire .01- 3 GHz frequency band. Frequency response
(deviation from center horizontal graticule line) should not exceed k 1.0 dB ( k 1.0 division).
16. Calculate mean deviation for .01- 3 GHz frequency band using maximum and minimum values recorded
in step 15. (For example, a maximum of + 0.5 and a minimum of -0.7 results in a mean deviation of
- 0.1)
Maximum + Minimum
Mean deviation = - divisions
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
NOTE
For the higher frequency bands, multiple responses may appear on spec-
trum analyzer display during frequency response measurement. Adjust
INTENSITY control as necessary for optimum display of in-band signal
peaks.
17. Select 6 - 9 GHz frequency band on spectrum analyzer. Set sweep oscillator to CW and frequency to 7.5
GHz. Use CW control to center signal on spectrum analyzer display. Set AF control for 3 GHz and trigger
a sweep. Adjust spectrum analyzer TUNING control clockwise several turns to reposition tuning marker.
Trigger another sweep. Record greatest positive and greatest negative deviation of signal peaks from center
horizontal graticule line (neglect deviations caused by tuning marker).
Maximum divisions
Minimum divisions
18. To calculate frequency response for 6 - 9 GHz frequency band, subtract mean deviation of step 16 from
maximum and minimum values recorded in step 17. Frequency response should not exceed k 1.0 dB
( + 1.0 division).
19. Select 3 - 9 GHz frequency band on spectrum analyzer. Set sweep oscillator to CW and frequency to 6.0
GHz. Use CW control to center signal on spectrum analyzer display. Set AF control for 6 GHq and trigger
a sweep. Adjust spectrum analyzer TUNING control to reposition tuning marker. Trigger another sweep.
Record greatest positive and greatest negative deviation of signal peaks from center horizontal graticule
line (neglect deviations caused by tuning marker).
Maximum divisions
Minimum divisions
20. Subtract mean deviation of step 16 from maximum and minimum values recorded in step 19. Frequency
response for 3 - 9 GHz frequency band should not exceed + 1.5 dB ( + 1.5 divisions).
PERFORMANCE TESTS
--
21. Select 9 - 15 GHz frequency band on spectrum analyzer. Set sweep oscillator to CW and frequency to 12.0
GHz. Use CW control to center signal on spectrum analyzer display. Trigger a 6 GHz sweep. Adjust
spectrum analyzer TUNING control to reposition tuning marker. Trigger another sweep. Record greatest
positive and greatest negative deviation of signal peaks from center horizontal graticule line (neglect devia-
tions caused by tuning marker).
Maximum divisions
Minimum divisions
22. Subtract mean deviation of step 16 from maximum and minimum values recorded in step 21. Frequency
response for 9 - 15 GHz frequency band should not exceed + 1.8 dB (+1.8 divisions).
23. Select 6 - 15 GHz frequency band on spectrum analyzer. Set sweep oscillator to CW and frequency to 10.5
GHz. Use CW control to center signal on spectrum analyzer display. Set AF control for 9 GHz and trigger
a sweep. Adjust spectrum analyzer TUNING control several turns to reposition tuning marker. Trigger
another sweep. Record greatest positive and greatest negative deviation of signal peaks from center hori-
zontal graticule line (neglect deviations caused by tuning marker).
Maximum divisions
Minimum divisions
23. Subtract mean deviation of step 16 from maximum and minimum values recorded in step 23. Frequency
response for 6 - 15 GHz frequency band should not exceed k 2.1 dB (+2.1 divisions).
25. Select 12.1 - 21 GHz frequency band on spectrum analyzer and adjust TUNING control fully clockwise.
Set sweep oscillator to CW and frequency to 15 GHz. Set AF control for 6 GHz and trigger a sweep.
Record greatest positive and greatest negative deviation of signal peaks from center horizontal graticule
line (12.1 GHz to 18 GHz).
Maximum divisions
Minimum divisions
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
26. Subtract mean deviation of step 16 from maximum and minimum values recorded in step 25. Frequency
response for 12.1 - 18 GHz portion of 12.1 - 21 GHz frequency band should not exceed + 2.3 dB ( + 2.3
divisions).
Disconnect power splitter from 20-dB attenuator and connect it to the power sensor. Set sweep oscillator to
CW with frequency of 18.0 GHz and measure output at power splitter with power meter.
Use CW control to slowly tune sweep oscillator from 18 GHz to 21 GHz. Note all peak deviations from
reference power level (recorded in step 27) and the frequencies at which they occur. Record frequencies and
power levels in Table 4-7.
Connect output of power splitter through 20-dB attenuator to spectrum analyzer input. Adjust spectrum
analyzer TUNING control counterclockwise several turns. Use CW control to tune sweep oscillator to
frequencies recorded in step 28 and record deviation of signal peak from center horizontal graticule line.
Set sweep oscillator to CW with frequency of 19.5 GHz. Set AF control for 3 GHz and trigger a sweep.
Note greatest positive and greatest negative deviation of signal peaks (18 GHz to 21 GHz). Use sweep
oscillator CW control to tune to points of greatest deviation. Record frequencies and deviations from
center horizontal graticule line in Table 4-7.
Disconnect power splitter from 20-dB attenuator and connect it to the power sensor. Use CW control to
tune sweep oscillator to frequencies recorded in step 30 and record power levels in Table 4-7.
Algebraically subtract reference power level recorded in step 27 from each power meter indicated recorded
in Table 4-7. Record results in Power Deviation column (see example). Add corresponding deviation from
center horizontal graticule line to each power deviation and record results in Sum of Deviations column.
Subtract mean deviation of step 16 from each value in Sum of Deviations column and record results in
Deviation from Mean column. Frequency response for 18 - 21 GHz portion of 12.1 - 21 GHz frequency
band should not exceed k 3.0 dB ( k 3 divisions).
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
Deviation from
Power Meter Power Sum of Deviation
Frequency Center Graticule
lndication Deviation* Deviations from Mean
(G Hz) Line (divisions
(d Bm) (dB) (dB) (dB)
or dB)
18.0 0 (Ref .)
*deviation relative to power meter indication at 18.0 GHz, recorded in step 27.
-8.0 0 (Ref .)
-9.0 -1 O
.
-8.5 -0.5
-7 .o +1 .o
-9 .o -1 .o
-8.5 -0.5
-7.5 +0.5
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
SPECIFICATION:
Gain compression is less than 0.5 dB for a - 10 dBm input level with 0 dB attenuation.
DESCRIPTION:
Gain compression is measured by changing the power level at the spectrum analyzer input from -20 dBm to
- 10 dBm. The displayed signal level will change by less than 10 dB, indicating gain compression in the input
mixer. Since a 10-dB change in IF gain is used to keep the signal trace near the same point on the display when
the input power is increased, the error due to this IF gain change is first measured, then subtracted from the
displayed deviation to give the deviation due only to gain compression.
SPECTRUM
ANALYZER
POWER
SIGNAL GENERATOR METER
O
o o
l RF
$
OUTPUT
ADAPTER
POWER
20 dB SPL l TTER
(CONNECTS DIRECTLY
ATTENUATOR TO 2OdE ATTENUATOR
D J
ADAPTER
EQUIPMENT:
PERFORMANCE TESTS
Spectrum Analyzer:
Signal Generator:
2. Connect equipment as shown in Figure 4-16. Note that the 10-dB attenuator is placed between the power
splitter and spectrum analyzer INPUT 5(M2connector.
3. Adjust signal generator OUTPUT LEVEL control for a power meter reading of - 10 dBm (-20 dBm at
spectrum analyzer INPUT 5(X2connector).
4. Adjust spectrum analyzer TUNING control to center 50 MHz signal on CRT. Set Amplitude Scale control
to 1 dB/DIV and adjust REF LEVEL FINE control to place peak of signal at a convenient horizontal
graticule line other than top graticule line.
5. Adjust signal generator OUTPUT LEVEL control for a power meter reading of 0 dBm (- 10 dBm at
spectrum analyzer INPUT 5(M2connector).
6. Set spectrum analyzer REFERENCE LEVEL control to 0 dBm, leaving REF LEVEL FINE control at
setting established in step 4. Record deviation of signal peak from reference graticule line of step 4 (step-
gain error). Values above reference line are positive ( + ); those below are negative ( - ).
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
Adjust signal generator OUTPUT LEVEL control for a power meter reading of - 10 dBm ( - 20 dBm at
spectrum analyzer 50Q connector).
Set spectrum analyzer INPUT ATTEN control to 0 dBm, REFERENCE LEVEL control to - 20 dBm,
and REF LEVEL FINE control to 0. Adjust REF LEVEL CAL control to place peak of signal at refer-
ence graticule line of step 4.
Adjust signal generator OUTPUT LEVEL control for a power meter reading of 0 dBm (- 10 dBm at
spectrum analyzer 50Q connector).
Set spectrum analyzer REFERENCE LEVEL control to - 10 dBm. Record deviation of signal peak from
reference graticule line of step 4.
dB
Calculate gain compression by algebraically subtracting step-gain error (step 4) from deviation of signal
peak (step 7). Gain compression should be less than 0.5 dB,
dB
Set spectrum analyzer INPUT AmEN control to 10 dB and REFERENCE LEVEL control to - 10 dBm.
Connect CAL OUTPUT to INPUT 5(M2 connector and recalibrate REF LEVEL CAL control setting.
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
SPECIFICATION:
DESCRIPTION:
The CAL OUTPUT signal is applied to INPUT 50Q connector and displayed on CRT. The peak of displayed
35-MHz signal is centered on CRT and adjusted for a vertical deflection of several divisions. The amplitude
variation of the signal is measured for each RESOLUTION BW control setting. The overall variation between
RESOLUTION BW settings of 3 MHz through 300 kHz should be less than 1.0 dB (k0.5 dB). The overall
variation between RESOLUTION BW settings of 3 MHz through 1 kHz should be less than 2.0 dB (k 1.0 dB).
PROCEDURE:
Adjust REF LEVEL FINE control to position peak of signal seven divisions above graticule baseline.
Set RESOLUTION BW and FREQ SPAN/DIV controls to settings indicated in Table 4-8. Record devia-
tion of signal peak from reference graticule line for each RESOLUTION BW control setting. Values above
reference line set in step 4 are positive ( + ); values below reference line are negative ( - ).
To find overall variation in Table 4-8, algebraically subtract greatest negative amplitude deviation from
greatest positive amplitude deviation. If all changes in amplitude are of the same sign, overall variation is
largest positive or largest negative change in amplitude. Overall variation between 3 MHz and 300 kHz
RESOLUTION BW setting should be <1.0 dB (k0.5 dB). Overall variation between 3 MHz and 1 kHz
RESOLUTION BW settings should be <2.0 dB ( +1.0 dB).
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
Overall Variation
RESOLUTION FREQ Amplitude Overall Variation Between
Between 3 MHz and
BW SPANIDIV Deviation 3 MHz and 300 kHz
1 kHz RESOLUTION
Setting Setting (dB) RESOLUTION BW Settings (dB)
Bw (dB,
PERFORMANCE TESTS
SPECIFICATION:
Step Accuracy (0 dB to 60 dB): < k 1.0 dB per 10-dB step, 0.01 to 18.0 GHz
Maximum Cumulative Step Error (0 dB to 60 dB): < 2.4 dB, 0.01 to 18.0 GHz
DESCRIPTION:
The input attenuator accuracy is tested over the range of 0 to 60 dB using an RF substitution method. A step
attenuator that has been calibrated at 30 MHz by a Standards Laboratory is used for substitution. The known
error of the calibrated attenuator is taken into account when computing the input attenuator accuracy.
SPECTRUM
ANALYZER
SIQNAL QENERATOR
R F OUTPUT (
(j
ADAPTER
Q 10 dB
ATTENUATOR
STEP
ATTENUATOR
EQUIPMENT:
PERFORMANCE TESTS
PROCEDURE:
Spectrum Analyzer:
Signal Generator:
Set step attenuator to 0 dB and use spectrum analyzer TUNING control to center 30 MHz signal from
signal generator on CRT display. Set FREQ SPAN/DIV to 20 kHz, RESOLUTION BW to 10 kHz, and
Amplitude Scale to 1 dB/DIV.
Adjust signal generator OUTPUT LEVEL control to position peak of signal seven divisions above grati-
cule baseline.
Set step attenuator and INPUT A m E N control to settings indicated in Table 4-9. For each setting, record
deviation of signal peak from reference graticule line set in step 3.
NOTE
PERFORMANCE TESTS
I *Attenuations > dial settings are positive (+). Attenuations < dial settings are negative (-). For example, 9.99 dB
calibration for a 10 dB attenuator setting represents an error of -0.01 dB. I
To compute corrected deviation for each setting, add step attenuator error to amplitude deviation. Cor-
rected deviation should not exceed 5 1.0 dB between any two adjacent INPUT ATTEN setting.
Record maximum positive and maximum negative corrected deviation values. Difference between these
two values (maximum cumulative step error) should not exceed 2.4 dB.
dB Maximum Positive Corrected Deviation
dB Maximum Negative Corrected Deviation
dB Maximum Cumulative Step Error
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
SPECIFICATION:
DESCRIPTION:
The reference level accuracy is tested over the range of - 10 dBm to - 100 dBm by checking the IF gain steps in
1 dB/DIV (Log) and in LIN. The resulting maximum deviation in each case must be less than k0.5 dB from
- 10 dBm to - 80 dBm and less than k 1.0 dB from - 10 dBm to - 100 dBm.
SPECTRUM
ANALYZER
SIQNAL QENERATOR
STEP
ATTENUATOR
3550
OPT H82
A
ADAPTER
t !
STEP
ATTENUATOR
!
S55C
OPT H8O
EQUIPMENT:
PERFORMANCE TESTS
PROCEDURE:
Spectrum Analyzer:
Connect equipment as shown in Figure 4-18 using 10-dB step attenuator. Set step attenuator to 0 dB and
adjust spectrum analyzer TUNING control to center 30 MHz signal on CRT Set FREQ SPAN/DIV
control to 10 kHz and RESOLUTION BW control to 3 kHz, adjusting TUNING control as necessary to
keep signal centered on CRT
Adjust signal generator OUTPUT LEVEL control to position peak of signal 6 divisions above graticule
baseline. Set step attenuator and spectrum analyzer REFERENCE LEVEL control to settings indicated in
Table 4-10. Record deviation of signal peak from 6th division for each setting.
To calculate Corrected Deviation, add Step Attenuator Error (calibration data at 30 MHz) to Deviation
from 6th Division for each setting. Corrected Deviation should not exceed + 0.5 dB from - 10 dBm to
- 80 dBm, and should not exceed k 1.0 dB from - 10 dBm to - 100 dBm. Record maximum values.
MODEL 8559A PERFORMANCE TESTS
PERFORMANCE TESTS
o 0 (Ref) (Ref)
10
20
30
40
50
60
70
80
90
>
*Attenuations dial settings are positive (+). Attenuations < dial settings are negative (-). For example, 9.99 dB
calibration for a 10 dB attenuator setting represents an error of -0.01 dB.
Set spectrum analyzer Amplitude Scale switch to LIN and REFERENCE LEVEL control to - 10 dBm.
Set step attenuator to 0 dB. Readjust signal generator OUTPUT LEVEL control to position peak of signal
6 divisions above graticule baseline.
Set step attenuator and spectrum analyzer REFERENCE LEVEL control to settings indicated in Table
4-11. Record deviation of signal peak from 6th division for each setting.
Using Table 4-12, convert Deviation from 6th Division in Linear Mode to Deviation in dB for each setting.
Record dB values in Table 4-11.
To calculate Corrected Deviation, add Step Attenuator Error to Deviation from 6th Division in dB for
each setting. Corrected Deviation should not exceed +0.5 dB from - 10 dBm to - 80 dBm and + 1.0 dB
from - 10 dBm to - 100 dBm. Record maximum values.
PERFORMANCETESTS MODEL 8559A
PERFORMANCE TESTS
REFERENCE Step Attenuator Deviation from Deviation from Step Attenuator Corrected
LEVEL Setting 6th Division 6th Division Error Deviation
Setting (d Bm) (dB) Linear Mode (div.) in dB* :Calibration)**(dB) (dB)
PERFORMANCE TESTS
9. Replace 10-dB step attenuator with 1-dB step attenuator. Set spectrum analyzer controls as follows:
FREQUENCY BAND GHz .................................................. .01- 3
TUNING .............................................................. 0.030GHz
FREQSPAN/DIV .......................................................... 50kHz
RESOLUTION BW .............................................. 300 kHz, uncoupled
INPUTATTEN .............................................................. OdB
REFERENCE LEVEL .................................................... - 10 dBm
REFLEVELFINE .............................................................. 0
Amplitude Scale ......................................................... 1 dB/DIV
SWEEPTIME/DIV ........................................................ AUTO
SWEEPTRIGGER ..................................................... FREERUN
ALT IF ..................................................................... OFF
SIGIDENT ................................................................. OFF
BLCLIP .................................................................... OFF
VIDEOFILTER .......................................................... 2o'clock
10. Set step attenuator to 0 dB. Center signal on CRT and adjust signal generator OUTPUT LEVEL control
to position peak of signal 6 divisions above graticule baseline. Set step attenuator and spectrum analyzer
REFERENCE LEVEL FINE control to settings indicated in Table 4-13. Record deviation of signal peak
from 6th division for each setting.
11. To compute Corrected Deviation, add Step Attenuator Error to Deviation from 6th Division for each
setting. Corrected Deviation should not exceed k 0.5 dB for each setting. Record maximum value.
0 (Ref)
*Attenuations > dial settings are positive (t). Attenuations < diaI settings are negative (-).
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
SPECIFICATION:
There are 20 selectable and calibrated sweep times in a 1-2-5 sequence from 2 pec/DIV to 10 sec/DIV
(excluding 2 sec/DIV).
I
I
BNC
TEE SPECTRUM
ANALYZER i
I
SIGNAL GENERATOR I
AUX
PEN1Bl F T l
BLANK l NG
I lNPUT
AM
IRF
OUTPUT
RQ 2141U CABLE
EQUIPMENT:
PERFORMANCE TESTS
PROCEDURE:
Spectrum Analyzer:
Signal Generator:
Function Generator:
PERFORMANCE TESTS
2. Connect equipment as shown in Figure 4-19. Connect counter's B 10 MHz input to the function generator
low output and the signal generator's AM input.
3. Adjust spectrum analyzer TUNING control to center 100-MHz signal on CRT Set FREQ SPAWDIV
control to 0, leaving RESOLUTION BW control at 3 MHz setting. Set SWEEP TIME/DIV control to 2
psec.
4. Set AM switch of HP 8640B to AC position. Adjust function generator AMPLITUDE control and signal
generator AM MODULATION control for 50 percent modulation as indicated on the signal generator
meter.
5. Set spectrum analyzer SWEEP TRIGGER control to VIDEO. Adjust REFERENCE LEVEL and REF
LEVEL FINE controls to center waveform on CRT
6. Adjust function generator Frequency vernier to display exactly five cycles of triangle wave modulation on
CRT, as shown in Figure 4-20a. Counter should indicate an average period of 4.00 + 0.04 ps.
5 cycles 10 cycles
7. Calculate actual sweep time per division by dividing average period from step 6 by 2. Record value in Table
4-14.
8. For spectrum analyzer SWEEP TIME/DIV control settings of 5 psec through 10 msec, adjust function
generator RANGE and frequency controls to display exactly 10 cycles of triangle wave modulation on
CRT, as shown in Figure 4-20b. Average period readings displayed on counter correspond to actual sweep
time per division. Record values in Table 4-14.
MODEL 8559A PERFORMANCETESTS
PERFORMANCE TESTS
9. Connect display rear-panel AUX B PENLIFT/BLANKING output to BNC tee at counter's B 10 MHz
input. Connect other side of tee to counter's A 50 MHz input.
11. Set spectrum analyzer SWEEP TIME/DIV to 20 msec. Adjust counter's SENSITIVITY controls for a
time interval reading of 0.2000 +0.0200 sec. Record sweep time value in Table 4-15.
12. Verify remaining spectrum analyzer SWEEP TIME/DIV control settings of 50 msec through 10 sec,
recording sweep time values in Table 4-15.
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
PERFORMANCE TESTS
SPECIFICATION:
DESCRIPTION:
The frequency of the calibrator output signal is measured with a microwave counter. The calibrator output level
is measured using a power meter.
SPECTRUM
ANALYZER
FREQUENCY POWER
COUNTER METER
0 y:;;
@.a@@
1-I
I INPUT
0
..... 0
I OUTPUT
0
EQUIPMENT:
PROCEDURE:
1. Connect spectrum analyzer CAL OUTPUT to frequency counter's 10 Hz - 500 MHz (5m) input as shown
in Figure 4-20. Measured output frequency should be 35 MHz k 400 kHz.
2. Zero and calibrate power meter. Connect power sensor, through adapter, to spectrum analyzer's CAL
OUTPUT and measure power level. Calibrator output level should be - 10 dBm +0.3 dB.
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
,
4-26. DISPLAY FIDELITY
SPECIFICATION:
DESCRIPTION:
The amplitude of the log display amplifier is tested by connecting a DVM to the display (AUX A) VERTICAL
OUTPUT connector. A wide resolution bandwidth setting is selected so the signal appears as a straight horizon-
tal line on the CRT The DVM is used to provide good resolution when checking for + 1 dB per 10 dB step (0.1
dB/dB).
SIONAL GENERATOR
D I O I T A L VOLTMETER
SPECTRL
ADAPTER
1 STEP
ATTENUATOR ADAPTER A
-
FIGURE 4-22. DISPLAY FIDELITY TEST SETUP
EQUIPMENT
PROCEDURE:
Spectrum Analyzer:
PERFORMANCE TESTS
Digital Voltmeter:
Signal Generator:
2. With no signal at spectrum analyzer's INPUT 5052, measure and record offset voltage at (AUX A) VERTI-
CAL OUTPUT connector.
4. Set spectrum analyzer's Amplitude Scale to 10 dB/DIV and adjust TUNING control to center signal on
CRT display.
5. Set spectrum analyzer's FREQ SPAN/DIV control to zero (0), VIDEO FILTER full CW (not in detent),
and RESOLUTION BW control to 1 MHz. Adjust TUNING control for maximum reading on DVM.
6. Set signal generator OUTPUT LEVEL control for DVM reading of (+ 800 mV + offset (step 2) f0.5
mV). Trace should be approximately at top CRT graticule line.
7. Record DVM readings for step attenuator settings, from 0 dB through 70 dB, in Table 4-16.
PERFORMANCE TESTS MODEL 8559A
PERFORMANCE TESTS
Theoretical Difference
Corrected
Attenuator DVM Theoretical Reading Subtracted Between
DVM
Setting Reading Reading From Corrected Adjacent
Reading*
(dB) (mV) (mV) D V M Reading Readings
(mV)
(m V) (m V)
0 +800 (Ref.)
10
20
30
40
50
60
70
EXAMPLETABLE OF 4-16
Theoretical Difference
Corrected
Attenuator DVM Theoretical Reading Subtracted Between
DVM
Setting Reading Reading From Corrected Adjacent
Reading*
(dB) (mV) (mV) D V M Reading Readings
(mV)
(mV) (mV)
8. After recording DVM readings for step attenuator settings from 0 dB through 70 dB, calculate each
Corrected DVM Reading by algebraically subtracting offset recorded in step 2. Record results in Table
4-16 (see sample computations).
9. Algebraically subtract corresponding Theoretical Reading from each Corrected DVM Reading, recording
results in Table 4-16. Maximum value should not exceed + 15 mV, corresponding to + 1.5 dB. Divide
maximum value by 10 to calculate Log Maximum Cumulative Error (in dB).
PERFORMANCE TESTS
Algebraically subtract each converted reading (Theoretical Reading Subtracted from Corrected DVM
Reading) from previous converted reading. Record results in Table 4-16 (see sample computations). Maxi-
mum difference between adjacent readings should not exceed + 10 mV, corresponding to f1 dB/10 dB or
+0.1 dB/dB. Divide maximum value by 100 to calculate Log Incremental Error (in dB/dB).
dB/dB Log Incremental Error
Replace 10-dB step attenuator with 1-dB step attenuator. Set step attenuator to 0 dB.
Set spectrum analyzer Amplitude Scale to LIN and adjust TUNING control for maximum reading on
DVM.
Adjust signal generator OUTPUT LEVEL for DVM reading of 800 mV + offset (step 2) +0.5 mV. Trace
should be approximately at top CRT graticule line.
Record DVM reading for step attenuator settings of 6 dB and 12 dB in Table 4-17.
Calculate each Corrected DVM Reading by algebraically subtracting offset recorded in step 2. Record
results in Table 4-17.
Algebraically subtract corresponding Theoretical Reading from each Corrected DVM Reading, recording
results in Table 4-17. Maximum value should not exceed +24 mV, corresponding to + 3% of 800 mV
Reference Level. Divide maximum value by 8 to calculate Percent Linear Error.
Theoretical
Attenuator DVM Theoretical Reading Subtracted
DVM
Setting Reading Reading From Corrected
Reading*
(dB) (mV) (mV) D V M Reading
(mV)
(mV)
Para. Results
Test Description
No.
Min Actual Max
Tuning Accuracy
Results
Para.
Test Description
No.
Min Actual Max
4.13. Residual FM
1.4 div
6. Peak-to-Peak Variation of Trace
(2 kHz1O.l sec)
4-14. Noise Sidebands
7.0 div down
6. Noise Sidebands
(-70 dB)
4-15. Resolution Bandwidth Accuracy
Para. Results
Test Description
No.
Min. Actual Max.
Residual Responses
Frequency Response
Gain Compression
1 1. Gain Compression
Results
Para.
Test Description
No.
Min. Actual Max.
Display Fidelity
SECTION V
ADJUSTMENTS
TABLE5-1. ADJUSTABLECOMPONENTS(1 OF 3)
-
I Adjustment
Name
Reference
Designator
Adjustment
Paragraph
Description
r-
TABLE 53. FACTORY SELECTED COMPONENTS IN ALPHA-NUMERICALORDER
Reference Reference
Basis of Selection Basis of Selection
Designator Designator
CAPACITORS
R A N G E : 1 t o 24 pF
TYPE: Tubular R A N G E : 27 t o 680 pF
TOLERANCE: T Y P E : Dipped Mica
1 to 9.1 pF = k.25 pF T O L E R A N C E : ?5%
Value Value
HP Part Number HP Part Number
(PF) (PF)
MODEL 8559A ADJUSTMENTS
RESISTORS
RESISTORS
4.64K
5.11K
5.62K
6.19K
6.8 1K
7.50K
8.25K
9.09K
10.OK
12.1K
13.3K
14.7K
16.2K
17.8K
l9.6K
21.5K
23.7K
26.1K
28.7K
31.6K
34.8K
38.3K
42.2K
46.4K
51.1K
56.2K
61.9K
68.1K
75 .OK
82.5K
90.9K
l OOK
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
-
-
REFERENCE:
DESCRIPTION:
The + 14.5V and - 10V regulated power supplies on Frequency Control Assembly A7 are adjusted. The
(dependent) - 12V power supply is then checked for proper dc output (with less than +50 mV variation) while
the spectrum analyzer is tuned from 10 MHz to 3 GHz. The + 10V power supply on Sweep Generator/Band-
width Control Assembly A9 and the VO (Varactor Offset) voltage on Marker Assembly A8 are then adjusted.
Both the + 10V power supply voltage and the VO voltage are temperature-dependent and must be adjusted
during the first five minutes after the spectrum analyzer is turned on (cold instrument).
D I G I T A L VOLTMETER
CABLE
ASSEMBLY
D l SPLAY
EQUIPMENT:
ADJUSTMENTS
--
PROCEDURE:
NOTE
2. Connect equipment as shown in Figure 5-1. Install Frequency Control Assembly A7 on extender board
and connect digital voltmeter to + 14.W test points A7TP3.
3. Adjust + 14.5V potentiometer A7R41 for a voltmeter indication of + 14.500 k0.002 Vdc.
4. Connect digital voltmeter to - 10V test point A7TP2 and adjust - 10V potentiometer A7R29 for a volt-
meter indication of - 10.000 -t 0.005 Vdc.
5. Use digital voltmeter to check for - 12.0 + 0. I Vdc at collector (case) of transistor A7Q7, located near
center of Frequency Control Assembly A7. Vary MAN SWEEP control over entire range and verify that
voltage indication varies no more than t0.05 Vdc.
ADJUSTMENTS
NOTE
7. Connect digital voltmeter to + 10V test point A9TP7 and adjust + 10V potentiometer A9R2 for a voltme-
ter indication of + 10.000 + 0.100 Vdc.
8. Connect digital voltmeter to VO test point A8TP2. Set spectrum analyzer SWEEP TIME/DIV control to
10 ms and SWEEP TRIGGER control to SINGLE. Turn ALT IF and SIG IDENT on (pushbuttons
depressed).
9. Voltage at A8TP2 will alternate between two values each time a sweep is triggered. Trigger sweep a few
times until voltmeter indicates least negative VO voltage. Adjust VO potentiometer A8R62 for a voltmeter
indication of - 2.00 & 0.10 Vdc.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
REFERENCE:
A9 Schematic
DESCRIPTION:
A counter is used to adjust the time interval of the 1 millisecond per division and 5 milliseconds per division
sweep times. Calibrated sweep times from 0.1 milliseconds through 50 milliseconds are then checked using the
counter time-interval (T.I.) function.
D l SPLAY
COUNTER
0 MHz
SPECTRUM
ANALYZER
EQUIPMENT:
PROCEDURE:
NOTE
Since the calibrated sweep time adjustments are dependent on the + 14.5V
and - 10V power supplies, the Power Supply Checks and Adjustments (par-
agraph 5-17) should be performed before starting this procedure.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
NOTE
Spectrum Analyzer:
3. Adjust counter SENSITIVITY controls (both channels) as necessary until counter triggers and indicates a
time interval of approximately 10.00 ms.
4. Adjust 1 ms potentiometer A9R10 for a time interval indication of 10.00 + 0.80 ms.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
NOTE
5. Set spectrum analyzer SWEEP TIME/DIV control to 5 msec. Readjust counter SENSITIVITY controls
as necessary and adjust 5 ms potentiometer A9R13 for a time interval indication of 50.00 + 4.00 ms.
6. Check time interval for each SWEEP TIME/DIV control setting listed in Table 5-5. Readjust 1 ms potenti-
ometer A9R10 and 5 ms potentiometer A9R13 as necessary if test limits are exceeded.
.I ms
.2 ms
.5 ms
1 ms
2 ms
5 ms
10 ms
2 0 ms
5 0 ms
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
REFERENCE:
DESCRIPTION:
Step attenuators are used to change the level of the input signal to the spectrum analyzer in calibrated steps. The
output of Vertical Driver and Blanking Assembly A15 is monitored, and adjustments are performed to calibrate
Log Amplifier Assembly A14.
SIGNAL QENERATOR
D l Q l T A L VOLTMETER
RF OUTPUT I
1 CABLE ADAPTER
A SS EM B L Y
D l SPLAY ADAPTER
STEP
ATTENUATORS
ADAPTER 65 1
AtOWl
EXTENDER
CABLE - ' O Z ~ ~
@@@ I SPECTRUM
ANALYZER
EQUIPMENT:
ADJUSTMENTS
PROCEDURE:
Spectrum Analyzer:
Signal Generator:
2. Set 1-dB step attenuator to 10 dB and 10-dB step attenuator to 0 dB. Remove AlOWl (blue cable) from
A5J2 and connect equipment as shown in Figure 5-3, using adapter to connect step attenuator to AlOWl.
NOTE
3. Set TEST-NORM switch on Step Gain Assembly A12 to TEST position. Adjust signal generator FRE-
QUENCY TUNE control for maximum signal amplitude on display with 10-dB step attenuator set to 0 dB
(reduce signal generator OUTPUT LEVEL control setting as necessary to bring signal on-screen).
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
Disconnect signal generator output from step attenuator. Adjust spectrum analyzer VERTICAL POSN
control to position signal trace at bottom CRT graticule line. Measure dc offset voltage at Al5TP1 and
record.
Connect signal generator to step attenuator and adjust signal generator FINE TUNE control to peak
signal on CRT display.
Adjust signal generator OUTPUT LEVEL for digital voltmeter (DVM) reading ( t 1 mV) of 800 mV plus
offset recorded in step 4, as measured at AlSTPl. Adjust spectrum analyzer VERTICAL GAIN control
to position signal trace at top graticule line.
Set 10-dB step attenuator to 0 dB and adjust SLOPE potentiometer A14R23 for DVM reading (k1 mV)
of 800 mV plus offset recorded in step 4, as measured at Al5TPl.
Set 10-dB step attenuator to 60 dB and adjust OFFSET potentiometer A14R10 for DVM reading (+ 1 mV)
of 200 mV plus offset recorded in step 4, as measured at A15TP1.
Set 10-dB step attenuator to 30 dB and adjust SLOPE potentiometer A14R23 for DVM reading (k1 mV)
of 500 mV plus offset recorded in step 4, as measured at Al5TPl.
Set 10-dB step attenuator to 60 dB and adjust OFFSET potentiometer A14R10 for DVM reading ( + 1 mV)
of 200 mV plus offset recorded in step 4.
Set 10-dB step attenuator to 10 dB and adjust - 30 dB potentiometer A14R69 for DVM reading ( t 1 mV)
of 700 mV plus offset recorded in step 4.
Set 10-dB step attenuator to 0 dB and adjust - 10 dB potentiometer A14R39 for DVM reading ( t 1 mV)
of 800 mV plus offset recorded in step 4.
Set 10-dB step attenuator to 60 dB and adjust OFFSET potentiometer A14RlO for DVM reading ( t 1 mV)
of 200 mV plus offset recorded in step 4.
Set 10-dB step attenuator to 0 dB and adjust SLOPE potentiometer A14R23 for DVM reading ( t 1 mV)
of 800 mV plus offset recorded in step 4.
Check log fidelity per Table 5-6. If test limits are not met, repeat steps 8 through 18.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
Theoretical Difference
Step Corrected Between
DVM Test Theoretical Reading Subtracted
Attenuator DVM Adjacent
Reading Limits Reading from Corrected
Setting Reading* Readings*"
(mV) (mV) (mV) DVM Reading
(dB) (mV)
(mV) (mv)
Example ( + 5 mV offset):
Theoretical Difference
Step Corrected Between
DVM Theoretical Reading Subtracted
Attenuator DVM Adjacent
Reading Reading from Corrected
Setting Reading* Readings*"
(mv) (mV) DVM Reading
(dB) (mV) (mV)
(mV)
ADJUSTMENTS
21. Remove adapter from step attenuator and connect step attenuator to spectrum analyzer input. Adjust the
signal generator OUTPUT LEVEL for a DVM reading ( k 1 mV) of 800 mV plus offset recorded in step 4
(measured at A 15TPI).
22. Set spectrum analyzer amplitude scale for Linear display (LIN) and adjust LIN control A14R34 for DVM
reading ( k 1 mV) of 800 mV plus offset recorded in step 4.
23. Make adjustments indicated in Table 5-8, then recheck that all steps meet the DVM test limits. Between
adjustments, recheck tuning of spectrum analyzer to be certain signal remains peaked.
ADJUSTMENTS
Log Gain
25. Set 10-dB step attenuator to 0 dB. Retune spectrum analyzer to peak signal. Adjust signal generator
OUTPUT LEVEL for DVM reading (+ 1 mV) of 800 mV plus offset recorded in step 4, as measured at
Al5TP1.
26. Set 10-dB step attenuator to 40 dB. Set REFERENCE LEVEL to -90 dBm and adjust LOG GAIN
control A14R121 for DVM reading of 800 mV plus offset recorded in step 4, as measured at Al5TP1.
27. Check log gain steps according to Table 5-9. If limits are not met, repeat steps 25 through 27. If limits still
are not met, return to step 1.
0 -5 0 *
Ref: 800 1 mV
10 -60 800 +30 mV
20 -7 0 800 +30 mV
30 -80 800 +30 mV
40 -9 0 800 +30 mV
29. Set both step attenuators to 0 dB. Reduce signal generator OUTPUT LEVEL until signal appears at top of
display. Adjust spectrum analyzer FINE TUNE to peak trace on display and adjust signal generator
OUTPUT LEVEL for DVM reading (k 1 mV) of 800 mV plus offset recorded in step 4, as measured at
Al5TPl. Increase attenuation in 1-dB steps as shown in Table 5-10 and take DVM readings to check log
amplifier output.
ADJUSTMENTS
Theoretical Difference
Step Corrected
DVM Test Theoretical Reading Subtracted Between
Attenuator DVM
Reading Limits Reading from Corrected Adjacent
Setting Reading*
(mV) (mV) (mV) D V M Reading Readings**
(dB) (mV)
(mv) (mV)
ADJUSTMENTS
REFERENCE:
A 15 Schematic
DESCRIPTION:
Reference is set in 10 dB/DIV amplitude scale and 1 dB offset is adjusted in 1 dB/DIV for the same full display
reference.
D l SPLAY
SPECTRUM
ANALYZER
EXTENDER
CABLE
ASSEMBLY
0.0 o...
l NPUT
OUTPUT
ADAPTER
PROCEDURE:
1. Set spectrum analyzer controls as follows:
FREQUENCYBANDGHz .................................................. .01-3
TUNING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >60MHz
FREQ SPAN/DIV .......................................................... 1 MHz
RESOLUTION BW ............................................... 1 MHz, uncoupled
INPUTATTEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10dB
REFERENCE LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 dBm
REFLEVELFINE .............................................................. 0
Amplitudescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIN
SWEEPTIME/DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUTO
SWEEP TRIGGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FREE RUN
ALTIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF
SIC IDENT ................................................................. OFF
BLCLIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF
VIDEOFILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
4. Set tuning to 35 MHz. Set TUNING control to center the trace on the display. Set REF LEVEL FINE for a
full-screen trace (signal at top graticule line).
5. Set Amplitude Scale to 10 dB/DIY Adjust VERT GAIN if necessary for full screen trace.
6 . Repeat steps 3 and 4 until the trace is full screen in both LIN and 10 dB/DIY
NOTE
1 dBlDlV will read approximately 0.5 dB (0.5 division) low when using
extender cable assembly. Adjusting A15R1 1 dB OFFSET for a trace 0.5 divi-
sion down from top graticule line should place signal at top graticule line
when HP 8559A is properly installed in display mainframe.
7. Set Amplitude Scale to 1 dB/DIV. Adjust A15R1 1 dB OFFSET for a trace 0.5 division down from top
graticule line.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
REFERENCE:
DESCRIPTION:
The crystal and LC bandwidth filter circuits are adjusted for symmetry, center, and peak. The 3-dB bandwidths
are adjusted with Sweep Generator/Bandwidth Control Assembly A9 (paragraph 5-22).
DISPLAY
SPECTRUM
ANALYZER
EXTENDER
CABLE
ASSEMBLY
.0
. o...
l NPUT
OUTPUT
ADAPTER
EQUIPMENT:
NOTE
ADJUSTMENTS
TERMINAL CONNECTORS
PROCEDURE:
NOTE
Crystal Alignment
NOTE
If Sweep Generator A9 has been replaced or adjusted, perform steps 3
through 8. If not, proceed to step 9.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
Center the signal with TUNING control. Using REF LEVEL FINE control, place signal peak at 7.1
divisions (0.9 division from top graticule line).
Adjust A9R85 LC until signal is five divisions wide at the fifth graticule line (1 MHz wide at 3-dB points).
Using REF LEVEL FINE control, place signal peak at 7.1 divisions.
Adjust A9R72 XTL until signal is one division wide at the fifth graticule line (10 kHz wide at 3-dB points).
Adjust REF LEVEL FINE control to place signal at sixth graticule line.
Remove top guide rail. Connect crystal shorts (through cover access holes) across the following pairs of
test points: A13TPl/TP2, A1 1TPl/TP2, and A1 lTP4/TP5.
NOTE
Keep crystal spike centered during adjustments. The SYM and CTR adjust-
ments for each crystal interact (the signal also drifts in this narrow span).
13. Adjust front-panel TUNING control to center bandpass spike (Figure 5-7) on the CRT display.
NOTE
14. Adjust A13C54 CTR for minimum signal amplitude. Then adjust A13C38 SYM and A13C54 CTR for a
centered and symmetrical bandpass as shown in Figure 5-7.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
CHECK CENTERING
HERE (SPIKE IS
CRYSTAL RINGING)
CHECK SYMMETRY
HERE (LOW ON SKIRTS)
Adjust A13C25 CTR for minimum signal amplitude. Then adjust A13C15 SYM and A13C25 CTR for a
centered and symmetrical bandpass.
Adjust A1 1C54 CTR for minimum signal amplitude. Then adjust A1 1C38 SYM and AllC54 CTR for a
centered and symmetrical bandpass.
Adjust A1 1C25 CTR for minimum signal amplitude. Then adjust A1 1C15 SYM and A1 1C25 CTR for a
centered and symmetrical bandpass.
Set FREQ SPAN/DIV to 10 kHz and RESOLUTION BW to 30 kHz. Center signal on CRT with TUN-
ING control.
Switch RESOLUTION BW from 30 kHz to 10 kHz and back several times. Verify that signal shift does
not exceed 3 kHz (0.3 divisions). If signal shift is out of tolerance, return to step 11.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
LC Alignment
Accidentally shorting the case of A9Q1 (directly below A9TP6) to ANY test
point will cause catastrophic failure to Sweep Generator Assembly A9.
24. Set RESOLUTION BW control to 100 kHz. Jumper A9TP6 to A9TP8. This forces the BW7 line to
+ 15Y Set FREQ SPAN/DIV to 100 kHz.
NOTE
When Bandwidth Filter Assemblies A l l and A13 are installed with covers in
place, midget copper alligator clips (HP Part Number 1400-0483)can be used
to short test points to the cover.
NOTE
It might be necessary to adjust the REF LEVEL FINE control to obtain an on-
screen display during the following adjustments.
Short to ground the following test points: A13TP6, A1 1TP3, and A11TP6. (This widens all but one
LC pole).
Center signal on CRT with TUNING control. Adjust A13C73 for minimum signal amplitude.
Adjust A13C74 for minimum signal amplitude. Remove shorts from A13TP3, A1 lTP3, and
A1 1TP6.
Reinstall A13 and cover. Short A13TP3 and A13TP6 to ground. Remove A1 1 cover and install A l l
on extender board.
Disconnect shorts from test points and reinstall A1 1 and cover. Leave jumper from A9TP6 to A9TP8
in place.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
26. Short to ground A1 lTP3, A1 lTP6, and A13TP3. Set RESOLUTION BW to 100 kHz and set FREQ
SPAN/DIV to 20 kHz.
27. Center signal on CRT with TUNING control. Adjust A13C45 LC CTR for symmetrical bandpass display
on CRT Use FINE TUNING control to keep crystal spike centered.
NOTE
The crystal spike represents the center frequency of the crystal poles. In
this procedure we are aligning the LC poles with the crystal poles. On some
instruments, the crystal spike may not be very pronounced, in which case
the center frequency of the 100 kHz RBW will have to be compared to the
center frequency of the 30 kHz RBW.
28. Move short from A13TP3 to A13TP6. Leave other shorts in place. Center signal on CRT with TUNING
control. Adjust A13C23 LC CTR for symmetrical bandpass display on CRT, keeping crystal spike cen-
tered.
29. Move short from A11TP6 to A13TP3. Leave other shorts in place. Center signal on CRT with TUNING
control. Adjust A1 lC45 LC CTR for symmetrical bandpass display on CRT, keeping crystal spike cen-
tered.
30. Move short from A1 1TP3 to A1 1TP6. Leave other shorts in place. Center signal on CRT with TUNING
control. Adjust A1 1C23 LC CTR for symmetrical bandpass display on CRT, keeping crystal spike cen-
tered.
31. Disconnect shorts from A1 1TP6, A13TP3, A13TP6, and from ground. Remove jumper from A9TP6 and
A9TP8.
32. Set FREQ SPAN/DIV to 10 kHz and RESOLUTION BW to 30 kHz. Center signal on ~ R with T TUN-
ING control. Set RESOLUTION BW to 100 kHz and note where signal crosses center vertical graticule
line.
33. Adjust A1 lC23, A1 1C45, A13C23, and A13C45 in succession so that amplitude of signal is peaked where
it crosses center vertical CRT graticule line, repeating step 32 between adjustments as necessary.
34. Repeat steps 32 and 33 until 30 kHz and 100 kHz bandwidths are centered with each other. If signal shift
between 30 kHz and 100 kHz bandwidths is greater than 10 kHz (1 division), repeat steps 24 through 33.
Bandwidth Amplitude
35. Set Amplitude Scale switch to 1 dB/DIV and jumper A9TP6 to A9TP8.
37. Set RESOLUTION BW to 100 kHz and FREQ SPAN/DIV to 200 kHz.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
Adjust FINE TUNING and REF LEVEL FINE controls for a centered signal at 7 divisions from bottom
graticule line.
Remove shorts from A13TP3 and A13TP6 and center signal with FINE TUNING control. Adjust
A13R26 LC for a signal amplitude of 7 divisions. Replace shorts on A13TP3 and A13TP6.
Remove shorts from A1 lTP3 and A1 1TP6. Adjust A1 1R26 LC for a signal amplitude of 7 divisions.
Repeat steps 36 through 40 until no further adjustment is necessary. Remove shorts from AllTP3,
A1 lTP6, A13TP3, and A13TP6.
Set RESOLUTION BW to 1 kHz and FREQ SPAN/DIV to 10 kHz. Center signal with FINE TUNING
control. Adjust A1 lR31 XTL and A13R31 XTL equally for a signal amplitude of 7 divisions. Each
potentiometer should be adjusted to accomplish half the necessary increase in signal amplitude.
Center signal with TUNING control. Adjust REF LEVEL FINE control for a signal amplitude of 7
divisions.
Step down RESOLUTION BW from 3 MHz tp 300 kHz. Variation in signal amplitude should be less than
-t 0.4 dB.
Set FREQ SPAN/DIV to 10 kHz, TIME/DIV to AUTO, and step down RESOLUTION BW from 100
kHz to 1 kHz. Variation of signal amplitude should be less than -t 0.7 dB from the 7th division reference.
NOTE
ADJUSTMENTS
REFERENCE:
A9 Schematic
DESCRIPTION:
The 3-dB bandwidths for the 3 MHz through the 30 kHz RESOLUTION BW settings are adjusted using the
CAL OUTPUT as the signal source. The 3-dB bandwidths for the 10 kHz, 3 kHz, and 1 kHz RESOLUTION
BW settings are adjusted by injecting a stable 321.4 MHz signal into the Third Converter (A10) of the spectrum
analyzer.
MICROWAVE
SIDNAL DENERATOR COUNTER
D l SPLAY
l NPUT
SPECTRUM
ANALYZER
m0
OUTPUT
ADAPTER !EE
ADAPTER
STEP
ATTENUATOR
ADAPTER
P
FIGURE 5-8. 3-dB BANDWIDTH ADJUSTMENTTESTSETUP
EQUIPMENT:
ADJUSTMENTS
PROCEDURE:
Set a 7.1 division signal level on display with REF LEVEL FINE control. Signal will be 0.9 division from
top graticule line.
Adjust A9R85 LC control for a 5 division wide signal at fifth graticule line.
Set RESOLUTION BW to 3 MHz and FREQ SPAN/DIV to 500 kHz. If necessary, reset signal level to 7.1
divisions with REF LEVEL FINE control. The bandwidth at the fifth graticule line should be between 5.4
and 6.6 divisions.
NOTE
A9R85 LC may be further adjusted to bring the 3 MHz and 300 kHz band-
widths within limits; however, the final measurement of the 1 MHz band-
width must be between 4.5 and 5.5 division at the fifth graticule line. (If the 3
MHz bandwidth cannot be brought within limits by adjustment of A9R85 LC,
change the value of factory-selected resistor A9R120*. If the 300 kHz band-
width cannot be brought within limits by adjustment of A9R85 LC, change
the value of A9R116*.)
Set RESOLUTION BW to 300 kHz and FREQ SPAN/DIV to 50 kHz. If necessary, reset signal level to 7.1
divisions with REF LEVEL FINE control. The bandwidth should be between 5.4 and 6.6 divisions at the
fifth graticule line.
Set RESOLUTION BW to 100 kHz and FREQ SPAN/DIV to 20 kHz. If necessary, reset signal level-to 7.1
divisions with REF LEVEL FINE control. The bandwidth should be between 4.3 and 5.7 divisions at the
fifth graticule line.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
NOTE
If the 100 kHz bandwidth is not within the specified limits, change the
values of factory-selected resistors A11R19*, A11R43*, A13R19*, and
A13R43*. If the bandwidth is too wide, increase the value of the resistors; if
the bandwidth is too narrow, decrease the value of the resistors. The fac-
tory-selected resistors need not be of equal value, but each must be within
one standard value of the others.
8. Set RESOLUTION BW to 30 kHz and FREQ SPAN/DIV to 10 kHz. If necessary, reset signal level with
REF LEVEL FINE control. The bandwidth should be between 2.6 and 3.4 divisions at the fifth graticule
line.
NOTE
If the 30 kHz bandwidth is not within the specified limits, change the values
of factory-selected resistors A11R23*, A11 R48*, A13R23*, and A13R48*. If
the bandwidth is too wide, decrease the value of the factory-selected resis-
tors; if the bandwidth is too narrow, increase the value of the resistors. The
factory-selected resistors must be within three standard values of the nomi-
nal value.
9. Connect signal generator as shown in Figure 5-8. Tune signal generator to approximately 21.4 MHz. Set
the signal generator to approximately 0 dBm and the step attenuator to 10 dB. Set COUNTER MODE to
EXPAND X 100.
10. Place spectrum analyLeron right side and connect test cable to Third Converter 21.4 MHz output connec-
tor A16J3. If connector is not present (some early instruments were not so supplied), remove AlOWl from
A5J2 and connect AlOWl through a 10 dB step attenuator set to 30 dB and the signal generator set for a
- 10 dBm output level. The 10 dB step attenuator between BNC tee and frequency counter can be elirni-
nated.
11. Set H P 8559A RESOLUTION BW to 1 MHz. Tune signal generator to peak signal on CRT display (near
21.4 MHz) (321.4 MHz if injecting into AlOWl). Adjust the output level of signal generator to place the
signal at 7.1 divisions.
12. Set RESOLUTION BW to 3 kHz. Tune signal generator to peak signal on CRT display.
14. Note the counter frequency and tune the signal generator 1500 Hz below the center frequency noted.
Record the new counter frequency.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
Adjust A9R72 XTL to bring signal level to the fifth graticule line (three divisions from the top graticule
line).
Increase signal generator frequency until signal on CRT display peaks and then decreases to the fifth
graticule line. Record counter frequency.
Compare new frequency with frequency recorded in step 14. The difference between the two frequencies
should be 2800 to 3200 Hz. If the bandwidth is not within limits, repeat steps 12 through 17, slightly
readjusting A9R72 XTL, until the specified limits are achieved.
Set RESOLUTION BW to 10 kHz. Tune signal generator to peak signal on CRT display.
Decrease signal generator frequency until the signal on the CRT display is at the fifth graticule line. Record
this frequency.
Increase the signal generator frequency until the signal on the CRT display peaks and then decreases t o the
fifth graticule line. Record this frequency.
Compare new frequency with frequency recorded in step 20. The difference between the two frequencies
should be 9.000 kHz to 11.000 kHz.
NOTE
A9R72 XTL may be further adjusted to bring the 10 kHz and 1 kHz band-
widths within limits; however, the final measurement of the 3 kHz bandwidth
must be between 2700 Hz and 3300 Hz. (If the 10 kHz bandwidth cannot be
brought within limits by adjusting A9R72 XTL, change the value of factory-
selected resistor A9R111*. If the 1 kHz bandwidth cannot be brought within
limits by adjusting A9R72 XTL, change the value of A9R109*.)
Set RESOLUTION BW to 1 kHz. Tune signal generator to peak signal on CRT display.
ADJUSTMENTS
Increase signal generator frequency until signal on CRT display decreases to the fifth graticule line. Record
the counter frequency.
Compare new frequency with frequency originally noted in step 25. The difference between the two fre-
quencies should be 450 Hz to 550 Hz.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
REFERENCE:
A12 Schematic
DESCRIPTION:
The RF gain (sensitivity) of Step Gain Assembly A12 is adjusted by injecting a 21.4 MHz signal at XAlOPl.
Third Converter Assembly A10 is removed and replaced with a special extender board for applying the 21.4
MHz signal from the signal generator.
D l SPLAY
(BLACK LEAD
EXTENDER BOARD
WITH 5 1 . 1 RESISTER
I N XAlOPI
EQUIPMENT:
ADJUSTMENTS
NOTE
To make special extender board, solder 51.1 ohm resistor from pin 18 to pin
22 of standard 24 pin extender board, HP Part No. 5060-0258. Leave resistor
leads long for easy connection of clip leads.
PROCEDURE:
2. Connect equipment as shown in Figure 5-9. Resistor on extender board should be toward rear of HP
8559A.
3. Set signal generator frequency to 21.4 MHz. Set output level for approximately - 5 dBm.
NOTE
4. Connect output of signal generator across 51.1 ohm resistor on special board using BNC to clip-lead
adapter. The red lead (center conductor) should be connected to pin 18 of extender board.
5. Set signal generator frequency for peak amplitude on CRT display. Connect output of signal generator to
power meter through a power sensor and set output level to - 3 dBm. Reconnect signal generator output
to clip-lead adapter.
6 . Adjust A12R5 GAIN adjustment for signal one division from top graticule line. DVM should indicate
+ 700 mV + 30 mV. Remove special extender board and replace Third Converter Assembly A10.
NOTE
ADJUSTMENTS
NOTE
Front panel VERTICAL GAlN and POSN control settings can affect the volt-
age measured at A15TP1. Vertical calibration should be checked after
adjusting A12R5 for 700 mV (Refer to Section Ill).
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
REFERENCE:
A12 Schematic
DESCRIPTION:
REF LEVEL FINE, 0 dB, and - 12 dB adjustments are properly set and step gains of 10 dB, 20 dB, and 40 dB
are adjusted.
D I G I T A L VOLTMETER
SIGNAL GENERATOR
.
ATTENUATOR
lNPUT RF OUTPUT
D l SPLAY
STEP
ATTENUATOR
EQUIPMENT:
ADJUSTMENTS
PROCEDURE:
Connect equipment as shown in Figure 5-10. Connect signal generator tuned to 321.4 MHz with approxi-
mately - 30 dBm output to one side of a 1 dB/step attenuator. Connect step attenuator output to AlOWl
through adapter. Tune signal generator frequency for peak amplitude on display.
Set step attenuator to 12 dB and REF LEVEL FINE to - 12. Set signal generator level for a signal one
division down from top graticule line.
Adjust A12R39 - 12 D until signal stops rising on display, then adjust A12R39 counterclockwise until
signal drops approximately one third to one half of a division.
Set signal generator level so signal is one division down from top graticule line on display.
Adjust A12R35 0 D adjustment for a signal level one division from top graticule line.
Set step attenuator to 12 dB and REF LEVEL FINE to - 12. DVM indication should be 700 + 30 mV
(offset). If offset is greater than + 30 mV, repeat steps 3 through 8 until DVM indication is within limits.
Replace 1 dB/step attenuator with 10 dB/step attenuator set to 0 dB. Set REF LEVEL FINE control to 0.
Tune signal generator frequency for peak amplitude on the display (near 321.4 MHz).
Set signal generator level for a signal one division down from top graticule line. Set step attenuator to 10
dB and REF LEVEL dBm to - 10.
Adjust A12R6 10 D adjustment for signal level one division from top graticule line.
Adjust A12R21 20 D adjustment for signal level one division from top graticule line.
ADJUSTMENTS
NOTE
Some video filtering might help reduce noise. Set VIDEO FILTER control so
noise is reduced, but the signal amplitude remains unchanged.
16. Adjust A12R29 40 D adjustment for signal level one division from top graticule line.
17. Check REF LEVEL dBm control from 0 to - 50 as shown in Table 5-11.
0 0 Reference mV
1 0 10 Reference +40 mV
2 0 20 Reference 240 mV
-30 30 Reference +40 mV
-40 40 Reference +40 mV
-50 50 Reference 240 mV
ADJUSTMENTS
REFERENCE:
DESCRIPTION:
The First LO (A6 YTO) is adjusted by monitoring the YTO output at the RF input connector (LO emission) and
the tuning voltage (TUNE) output of the A7 Frequency Control board, and adjusting the YTO low-end fre-
quency for 3 GHz at OV tuning voltage and 6 GHz at - 10V tuning voltage.
COMB
QENERATOR
MICROWAVE / \
COUNTER
DIGITAL VOLTMETER 1111
D l SPLAY
OUTPUT
CABLE
ASSEMBLY
n A7TP4
.
A16TPl TUNE
EXTENDER LOCATED THROUGH \
CABLE HOLE I N S I D E
ASSEMBLY FRAME HERE --C ' O : z SPECTRUM
L
@.@@@
..no O...Q
ANALYZER
CABLE
--
RQ214lU I
EQUIPMENT:
PROCEDURE:
1. Allow one-half hour warmup time of equipment with spectrum analyzer connected to mainframe with
extender cable.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
First LO Adjustments
5. Jumper A16TPl DIODE BIAS to ground. A16TP1 is located on the motherboard through a hole in the
analyzer left side gusset.
6. Adjust front-panel TUNING control for DVM indication of 0.000 Vdc (fully counterclockwise).
+
7. Adjust A7R8 (3 GHz) for frequency counter indication of 3.000 GHz 1 MHz. (If this adjustment cannot
be achieved, factory select resistor A7R3* can be added - if it is not installed - or decreased to provide the
proper range. Select a value of 147K ohms for A7R3*, initially, and decrease this value to no less than
56.2K ohms.)
10. Adjust A7R47 6 GHz C (coarse) for a frequency counter indication of 6.000 GHz + 2 MHz.
11. Retune front-panel TUNING control for 0.000 Vdc DVM indication and readjust A7R8 3 GHz if neces-
*
sary for frequency counter indication of 3.000 GHz 1 MHz.
13. Lightly tap the top edge of the A7 Frequency Control board with the handle of a small screwdriver to seat
controls.
14. Adjust A7R75 6 GHz F (fine) for frequency counter indication of 6.000 GHz *1 MHz.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
18. Disconnect frequency counter from spectrum analyzer RF Input and connect comb generator to RF Input.
21. Tbne front-panel TUNING control for approximately 1.5 GHz indication on front-panel FREQUENCY
GHz display.
22. Adjust A7R83 DC (Delay Compensation) until the comb teeth on the left half of the mainframe CRT
display have the same approximate spacing as those on the right half.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
Adjust front-panel TUNING FINE control to place a comb tooth on the first vertical graticule line of the
CRT display.
Adjust A7R92 FM to place a comb tooth on the ninth vertical graticule line of the CRT display.
Switch to 10 kHz RES BW and adjust A7R83 DC for even spacing of the comb teeth on the first two
graticule lines.
Readjust TUNING FINE control to place a comb tooth on the first vertical graticule line. Adjust A7R92
FM to place a comb tooth on each of the graticule lines while keeping the first comb tooth aligned using
the TUNING FINE control.
NOTE
Switch to 30 kHz RES BW. The comb tooth spacing should not change. If there is a shift of the comb
teeth, repeat steps 22 through 27 for best compromise in span linearity.
Tune to approximately 100 MHz and verify that a comb tooth placed on the first vertical graticule line,
using the TUNING FINE control, will align the ninth comb tooth with the ninth vertical graticule line +1
minor division.
Select the 10 kHz RES BW and verify that a comb tooth on the first vertical graticule line will align the
ninth comb tooth with the ninth graticule line + 1 minor division.
Select the 30 kHz RES BW and repeat step 29 for a frequency of approximately 2.5 GHz.
If necessary, A7R83 (DC) and A7R92 (FM) may be compromise adjusted for best span linearity at the
three frequencies indicated.
Adjust front-panel TUNING control for 0.10 GHz indication on FREQUENCY display.
ADJUSTMENTS
Adjust A7R81 (MO) to place comb tooth midway between position noted in step 38 and center graticule
line.
Set FREQ SPAN/DIV to 1 MHz. Note displacement of comb tooth from center graticule line.
Repeat steps 36 through 42 until displacement of comb tooth is less than 0.2 major division when FREQ
SPAN/DIV is switched from 2 MHz to 1 MHz.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
REFERENCE:
DESCRIPTION:
First, the Second LO is adjusted for proper frequency using a frequency counter. Next, the signal identifier (SIG
ID) and alternate IF (ALT IF) signals are adjusted so that the displayed signal appears in the same location in
both regular and alternate IF and the signal identifier is always 1 MHz away from this signal in either regular or
alternate IF. Last, the first IF bandpass filter is aligned for a bandpass wide enough to allow for the first LO
shift and amplitude characteristics such that there will be a minimal shift in displayed signal amplitude when the
analyzer is switched from regular to alternate IF.
[q!
FUNCT ION M I CRWAVE
QENERATOR COUNTER
D l SPLAY
:
0:. 0 0 0
OUTPUT
000 000 -
0 0 000 0
TER
ADAPTER TEST
A5A2Pl A5J9
ADAPTER
VARACTOR 2ND L O
\
' O = r i SPECTRUM
@.@a@
ANALYZER
OUTPUT
u
FIGURE 5-12. SECOND CONVERTER ADJUSTMENTSTEST SETUP
EQUIPMENT:
ADJUSTMENTS
PROCEDURE:
Allow one-half hour warm-up time of equipment with analyzer connected to mainframe with extender
cable.
Connect frequency counter input to A5J3 2nd LO output using the test cable and two SMB adapters.
Select Band 1 (.01-3) and Alternate IF on spectrum analyzer front-panel by depressing these pushbut-
tons.
Using the special Allen driverhut driver tuning tool, adjust A5Z4 2nd LO FREQUENCY for a frequency
counter indication of 2671.1 MHz k 0.5 MHz.
Connect spectrum analyzer CAL OUTPUT to RF INPUT and adjust front-panel TUNING controls to
center the calibrator signal on the CRT display.
Turn SIG IDENT off and on while monitoring the display. The signal traces which appear when SIG
IDENT is switched on are the signal identifier signals. The others are the alternate IF signals.
Adjust TUNING to place one of the signal identifier signals on a graticule line. This will be the reference
graticule line.
Turn ALT IF off. Adjust A8R34 REG to center the signal identifier signal on the reference graticule line.
Turn ALT IF on. Verify that the signal identifier signal appears on reference graticule line. If not, repeat
step 10.
Adjust A8R40 SIG ID to place the alternate IF signal 1 MHz (1 division) higher than the signal identifier
signal.
Turn ALT IF off. Adjust A8R39 OFF to center the signal on the same graticule line as the alternate IF
signal (1 MHz higher than reference graticule line).
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
n r n ALT IF on and verify that the two signals do not appear to move.
Repeat steps 7 through 14 if necessary to align both signal identifier signals and both alternate IF signals
and spaced 1 MHz (2 divisions) apart on the CRT display.
Adjust A5Z4 2nd LO FREQUENCY if necessary for a frequency counter indication of 2671.1 MHz +0.5
MHz.
If second LO frequency is readjusted, recheck second LO shift adjustments, steps 5 through 16.
FREQSPAN/DIV ..........................................................2MHz
RESBW ..................................................................3MHz
REFLEVELdBm ............................................................ -10
INPUTATTEN ............................................................. 10dB
Amplitudescale .........................................................ldB/DIV
TIME/DIV ................................................................AUTO
FREQUENCYBANDGHz ........................................... Band1 (.01-3)
ALTIF ......................................................................ON
SIG IDENT .................................................................OFF
Adjust front-panel REF LEVEL dBm and REF LEVEL FINE controls to place signal peak in upper half
of CRT display for convenient viewing.
Adjust front-panel TUNING control to place signal peak 3.75 divisions to the left of center screen on the
CRT.
Connect the HIGH output of the function generator to an oscilloscope and adjust function generator
output for a OV to + 20V ramp and frequency to 500 Hz.
Disconnect the function generator from the oscilloscope and connect it to A5A2TP1 VARACTOR by
using the 8 120-1292adapter.
The following adjustments refer to aligning the Second Converter after internal repair of the converter. If
the entire converter has been replaced, it will probably not be necessary to perform all of the adjustments.
Adjustments A5Z1, A5Z2, A5Z3, and A5L2 are used to align the bandpass filter and output match of the
Second Converter. Z1 and L2 are used to adjust amplitude and 22 and 23 are used to center the response
about the center frequency.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
The requirements for the converter response are illustrated in Figure 5-13a and are as follows: Bandpass
should be at least 17 MHz, 1 dB down. Amplitude of response at 3.75 divisions to the left and 3.75
divisions to the right of center screen should be as near the same as possible. These are the positions of the
IF signals for regular and alternate IE This is illustrated in composite photo Figure 5-13b. These positions
should be the same distance from the roll-off point at each end of the response curve.
Distance from roll-off points can be checked by centering signal with function generator disconnected then
reconnecting function generator and switching ALT IF on and off. This is illustrated in Figure 5-13c and 5-
13d.
Adjust ASZ1, 22, 23 and L2 to satisfy the requirements of the converter response. If entire converter has
been replaced, try adjusting ASZl and L2 first. Do not adjust A2 and A3 unless it is necessary to meet
requirements. Do not sacrifice amplitude to achieve flatness.
When adjustment is complete, disconnect function generator from ASA2TP1, center signal on display,
and turn ALT IF on and off while monitoring signal.
Amplitude difference between regular and alternate IF should be no more than 0.4 dB.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
r
>17 MHz WIDE 1 dB DOWN AS SHOWN
1
7
ALTERNATE REGULAR
.
-3.75 DIV +3.75 D I V IF IF
ADJUSTMENTS
REFERENCE:
A10 Schematic
DESCRIPTION:
First, the Third LO is adjusted for proper frequency using a frequency counter. Next, the second IF bandpass
filter is aligned by injecting a frequency modulated 321.4 MHz signal at the necessary level and monitoring the
21.4 MHz output signal with another spectrum analyzer. The filter is aligned for a bandpass wide enough to
accommodate any frequency drift occurring in the RF section of the analyzer and the amplitude necessary to
provide the overall gain characteristics required by the analyzer.
OUTPUT
D l SPLAY
ADAPl'ER ADAPTER 6
I
I .
SWEEP
OSCILLATOR
RF
.
PLUG- IN
SPECTRUM
ANALYZER
OUTPUT
ADAPTER
ADAPTER ATTENUATORS
EXTENDER
CABLE
ASSEMBLY
EQUIPMENT
ADJUSTMENTS
PROCEDURE:
1. Allow one-'lalf hour warmup time of equipment with analyzer connected to mainframe with extender
cable.
Third LO Adjustment
2. Connect frequency counter to AlOJl 300 MHz output using the BNC to SMB test cable.
3. Adjust AlOL12 LO ADJ for frequency counter indication of 300.00 MHz +0.1 MHz.
Second IF Bandpass Filter Alignment
5. Set sweep oscillator controls for an output of 321.4 MHz at 0 dBm (measured directly at output of sweep
oscillator). Use the frequency counter and spectrum analyzer to set the output frequency and amplitude.
6 . Connect output through 10 and 20 dB attenuators to cable disconnected in step 4, using the BNC to SMB
test cable and SMB male to SMB male adapter.
7. Place analyzer on right side and connect test cable to Third Converter 21.4 MHz output connector. If
connector is not present (some early instruments were not so supplied), it is necessary to solder a coaxial
cable to XAlOPl pin 18 and ground (center conductor of coaxial cable to XAlOPl and shield to ground).
11. Center the 21.4 MHz signal on the 8569B spectrum analyzer, adjust reference level to place signal within
top division on CRT, then change scale to 1 dB/DIV. Adjust REF LEVEL FINE to place signal peak in
upper half of display.
12. Set function generator controls for a 200 Hz triangle wave output and connect to sweep oscillator RF Plug-
In rear-panel FM input. Set FM/NORM/PL switch to FM.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
Adjust function generator amplitude and frequency for at least 10 MHz deviation (k5 MHz) and an easy-
to-view display on the 8569B spectrum analyzer. Refer to Figure 5-15. Increasing the frequency of the
function generator will increase the swept frequency range of the sweep oscillator.
Adjust second IF bandpass filter adjustments A10C9 through A10C12 for the flattest bandpass response
possible at the greatest amplitude possible centered at 21.4 MHz and at least 6 MHz (6 divisions) wide at 1
dB down from the highest point on the response curve. Do not sacrifice large amounts of amplitude for
flatness. Some early instruments may display ripple on the response. This ripple should be I1 dB peak-to-
+
peak. Peak of adjusted response should be at - 10 dBm 2 dB.
NOTE
The output level of the third converter is actually 0 dBm. Due to the mis-
match error ( ~ 9 . 5dB) encountered in this measurement, the level measured
will be approximately - 10 dBm.
Refer to Figure 5-15 for example of properly adjusted bandpass response and requirements for response.
21.4 MHz
ADJUSTMENTS
REFERENCE:
NOTE
Perform CAL OUTPUT and REF LEVEL CAL adjustments (5-29) before pro-
ceeding with frequency response adjustments.
DESCRIPTION:
Frequency Response (flatness) is adjusted in six parts corresponding to the six harmonic bands of the analyzer.
In each band, the analyzer is swept-tuned with a tracking signal source comprising a sweep oscillator and
synchronizer. The sweep oscillator is tuned with an external sweep ramp generated by scaling the analyzer sweep
output (AUX D) with a special tuning voltage circuit. This provides synchronization of the sweeps of the two
instruments (sweep oscillator and analyzer), thus providing phase-lock of the two instruments. Each of the
bands is adjusted for optimum flatness and all bands are adjusted for equal amplitudes.
SWEEP RF
OSCILLATOR PLUG- IN SYNCHRONIZER
D l SPLAY
1 11 ASSEMBLY
ADAPTER
CRYSTAL
DETECTOR
SPECTRUM
ANALYZER
0000 o...
ADAPTER
METER
I ATTENUATOR '
L- - - - - - - - - - -
4
! ADAPTER
POWER
SENSOR
TUN l NG
VOLTAGE
I
L---- ----- 0------- J
O V TO t 1 0 V -
CIRCUIT
(FIGURE 5-17)
- 5 V TO +5V
ADAPTER POWER
SENSOR
ADJUSTMENTS
FROM
AUX D
ANALYZER { S T P
+5v
>-h
+, 4
+ '
-IOV
+ 20v
J2
IOK
I) TO 8 6 2 0 C
+ 20V PROGRAMMING
CRI
R7
5K
REFERENCE
DESIGNATOR
CRl
HP P A R T NUMBER
I DESCRIPTION
ADJUSTMENTS
EQUIPMENT:
1. Allow one-half hour warmup time of equipment with analyzer connected to mainframe with extender
cable.
2. Connect equipment as shown in Figure 5-16 with power meter/power sensor connected to 20 dB attenua-
tor and H P 86222A/B (.01- 2.4 GHz plug-in) installed in sweep oscillator mainframe.
Mainframe:
Plug-in
POLARITY ................................................................... -
SENSITIVITY ....................................................... 6 MHz/VOLT
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
8. Disconnect power meter/power sensor and connect 20 dB attenuator directly to analyzer RF INPUT as
shown in Figure 5- 16.
10. Adjust Tuning Voltage Circuit GAIN control fully clockwise then adjust OFFSET control to center phase-
locked signal on CRT. Refer to Figure 5-18a.
ADJUSTMENTS
11. Adjust Tuning Voltage Circuit GAIN control to expand the phase-locked display over 8 1/2 divisions on
CRT (.01- 2.4 GHz). Refer to Figure 5-18b. It may be necessary to readjust OFFSET slightly to achieve
phase-lock over entire range.
12. Optimum phase-lock is indicated by a smooth trace over full swept frequency range on CRT and minimum
needle movement on synchronizer phase error meter.
13. Place CRT trace in top division of display using analyzer REF LEVEL FINE control.
14. Change spectrum analyzer Amplitude Scale to 1 dB/DIV and adjust REF LEVEL FINE control to place
trace in upper half of display.
15. Remove CAUTION label (PC Board) from cover of A12 Step Gain by removing two pozi-drive screws.
17. Adjust A12R47 1B (tilt) for best overall flatness of trace on CRT.
NOTE
Remember, you are viewing only a portion (.01-2.4 GHz) of Band 1. The
remainder of Band 1 may have an effect on this adjustment.
18. Note highest and lowest points on CRT trace for reference. Also note level of trace at 2.1 GHz position on
CRT (8th vertical graticule line).
20. Disconnect cables from HP 86222A/B (.01- 2.4 GHz plug-in) and remove plug-in from sweep oscillator
mainframe.
21. Install HP 86290B (2 - 18.6 GHz plug-in) or HP 86290B-H08 (2 - 22 GHz plug-in), if available, in sweep
oscillator mainframe and reconnect cables as shown in Figure 5-16 with 20 dB attenuator connected to
analyzer RF INPUT.
22. Set RF plug-in controls the same as for the pIug-in removed (refer to step 3) and select Band 4 (2 - 18.6 or
2 - 22 GHz) on sweep oscillator mainframe.
23. Place RF plug-in RF OFF/ON switch ON. Change analyzer Amplitude Scale to 10 dB/DIY
25. Adjust spectrum analyzer TUNING controls for FREQUENCY GHz indication of 2.500 and change
FREQ SPAN/DIV to 100 MHz. Make sure RES BW remains at 3 MHz.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
26. Adjust Tuning Voltage Circuit GAIN and OFFSET controls to phase-lock swept signal from 2 to 3 GHz.
27. Adjust RF plug-in POWER LEVEL control to place trace at approximately - 27 dBm on CRT.
29. Adjust RF plug-in POWER LEVEL control to place 2.1 GHz position of CRT trace to same level as that
noted in step 18.
30. Note flatness of trace from 2 to 3 GHz. Total deviation of trace from .O1 to 3 GHz should not exceed 2.0
dB.
31. Center trace about the sixth horizontal graticule line on the CRT using analyzer REF LEVEL FINE
control. Do not change this setting for remainder of procedure. This will be used as amplitude reference
for remaining frequency bands.
NOTE
6 to 9 GHz Adjustment
35. Adjust Tuning Voltage Circuit GAIN and OFFSET controls to phase-lock swept signal from 6 to 9 GHz.
Refer to Figure 5-19b.
37. Adjust A12R58 2A (offset) and A12R48 2B (tilt) for best overall flatness of trace from 6 to 9 GHz with
trace approximately centered about the sixth horizontal graticule line on the CRT.
38. Total deviation of CRT trace from 6 to 9 GHz should not exceed 2.0 dB.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
543
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
3 to 9 GHz Adjustment
40. Change spectrum analyzer Amplitude Scale to 10 dB/DIV and FREQUENCY BAND GHz to 3 - 9.
42. Adjust Tuning Voltage Circuit GAIN and OFFSET controls to phase-lock swept signal from 3 to 9 GHz.
Refer to Figure 5-19c.
44. Adjust A12R83 V2 - (bias), A12R59 3A (offset), and A12R49 3B (tilt) for best overall flatness of trace
from 3 to 9 GHz with trace approximately centered about the sixth horizontal graticule line on the CRT.
45. Total deviation of trace from 3 to 9 GHz should not exceed 3.0 dB.
9 to 15 GHz Adjustment
Adjust Tuning Voltage Circuit GAIN and OFFSET controls to phase-lock swept signal from 9 to 15 GHz.
Refer to Figure 5-19d.
Adjust A12R87 V2 + (bias), A12R60 4A (offset), and A12R51 4B (tilt) for best overall flatness of trace
from 9 to 15 GHz with trace approximately centered about the sixth horizontal graticule line on the CRT.
Total deviation of trace from 9 to 15 GHz should not exceed 3.6 dB.
6 to 16 GHz Adjustment
56. Adjust Thing Voltage Circuit GAIN and OFFSET controls to phase-lock swept signal from 6 to 15 GHz.
Refer to Figure 5-19e.
MODEL 8559A ADJUSTMENTS
ADJUSTMENTS
58. Adjust A12R71 V3 - (bias), A12R61 5A (offset), A12R53 5B (tilt), and A12R54 5C (breakpoint) for best
overall flatness of trace from 6 to 15 GHz with trace approximately centered about the sixth horizontal
graticule line on the CRT.
59. Total deviation of trace from 6 to 15 GHz should not exceed 4.2 dB.
NOTE
Adjust sweep oscillator for swept output from 12 to 18.6 GHz or 12 to 21 GHz, depending on which RF
plug-in is used.
Adjust Tuning Voltage Circuit GAIN and OFFSET controls to phase-lock swept signal from 12 to 18.6
GHz or 12 to 21 GHz. Refer to Figure 5-19f.
Adjust A12R70 V3 + (bias), A12R62 6A (offset), A12R55 6B (tilt), and A12R56 6C (breakpoint) for best
overall flatness of trace from 12.1 to 18.6 GHz or 12.1 to 21 GHz with trace approximately centered about
the sixth horizontal graticule line on the CRT.
Total deviation of trace from 12.1 to 18 GHz should not exceed 4.6 dB and from 18 to 21 GHz should not
exceed 6.0 dB.
If unable to achieve flatness specifications, it may be necessary to plot a characterization curve of the
sweep oscillator output from 12 to 21 GHz. This can be done by measuring the power output of the sweep
oscillator (at the 20 dB attenuator) every 500 MHz from 12 to 21 GHz using a power meter. The values
obtained can then be plotted on the CRT and flatness adjusted to this corrected curve. Total deviation then
becomes the difference between the largest positive and largest negative deviation from the plotted curve.
This characterization will require the use of an 18 - 21 GHz thermistor mount and K-Band waveguide
adapter in addition to equipment previously used. Recommended equipment is listed under EQUIPMENT
in this procedure along with previously used equipment.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
NOTE
REFERENCE:
DESCRIPTION:
The 35 MHz CAL OUTPUT signal is adjusted for proper amplitude and frequency using a power meter and
frequency counter. Adjustment range of the front-panel REF LEVEL CAL control is set using the CAL OUT-
PUT signal as a reference.
D l SPLAY
M I CROWAVE
POWER COUNTER
METER
SPECTRUM
ANALYZER ;;;;;; 0
-.
1
000 000
0 0 a00 0
l NPUT
@.@@6
'-jnlPuT OUTPUT !Kk
ADAPTER
I-
FIGURE 5-20. CAL OUTPUT AND REF LEVEL CAL ADJUSTMENTSTEST SETUP
EQUIPMENT:
ADJUSTMENTS
PROCEDURE:
1. Allow one-half hour warmup time of equipment with spectrum analyzer connected to mainframe with
extender cable.
2. Connect power meter/power sensor to front-panel CAL OUTPUT connector as shown in Figure 5-20.
3. Place spectrum analyzer on its right side. Adjust A10R13 CAL AMPL for power meter indication of
- 10.0 dBm k 0.1 dB. A10R13 is accessed through motherboard.
4. Disconnect power meter/power sensor and connect frequency counter to CAL OUTPUT connector.
5. Adjust A10C46 CAL FREQ for frequency counter indication of 35.00 MHz +0.01 MHz. A10C46 is
accessed through motherboard.
6. Repeat steps 2 through 5 until CAL OUTPUT signal is properly adjusted for both amplitude and fre-
quency.
8. If not already removed, remove CAUTION label (PC Board) from A12 Step Gain.
12. Change Amplitude Scale to 1 dB/DIV and adjust REF LEVEL FINE if necessary to place signal peak on
first horizontal graticule line above bottom reference line of CRT
13. Adjust front-panel REF LEVEL CAL to raise signal peak three divisions (3 dB) on CRT (to fourth
graticule line above bottom reference line on CRT).
14. Change Amplitude Scale to 10 dB/DIV, REF LEVEL dBm to - 10, and set REF LEVEL FINE to 0 dBm.
ADJUSTMENTS MODEL 8559A
ADJUSTMENTS
15. Signal peak should now be approximately at top graticule line (Reference Level) on CRT.
16. Switch between 10 dB/DIV and LIN while adjusting A12R57 1A (offset) to place signal peak at same level
in both 10 dB/DIV and LIN.
17. Level at which signal peaks are coincident should be at top graticule line (Reference Level). If not, adjust
front-panel VERTICAL GAIN to place signal peak at Reference Level line. Be sure VERTICAL POSN is
properly adjusted for baseline on bottom graticule line.
ADJUSTMENTS
REFERENCE:
A1 and A8 Schematics
DESCRIPTION:
The Digital Panel Meter (DPM) OFFSET and GAIN controls are adjusted for proper FREQUENCY display
indication at corresponding tuning voltage (DPMA) levels.
D I Q I T A L VOLTMETER
INPUT V
D l SPLAY
EQUIPMENT:
ADJUSTMENTS
PROCEDURE:
Allow one-half hour warmup time of equipment with analyzer connected to mainframe with extender
cable.
Connect DVM to AlA2TPl DPMA. AlA2TPl is located below the board and is accessible through cut-
out in left side gusset.
SECTION VI
REPLACEABLE PARTS
REFERENCE DESIGNATIONS
. . . . . . . . . . . . . . . . . . . . . . . . Assembly F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fuse RT . . . . . . . . . . . . . . . . . . . . . . Thermistor
. . . . . . . . . . . . . . Attenuator, Isolator, FL ........................... Filter S ........................... Switch
Limiter, Termination HY . . . . . . . . . . . . . . . . . . . . . Circulator T . . . . . . . . . . . . . . . . . . . . . . Transformer
. . . . . . . . . . . . . . . . . . . . . . Fan,Motor J ................ Electrical Connector TB . . . . . . . . . . . . . . . . . . Terminal Board
. . . . . . . . . . . . . . . . . . . . . . . . . Battery (Stationary Portion), Jack TC . . . . . . . . . . . . . . . . . . . Thermocouple
. . . . . . . . . . . . . . . . . . . . . . . Capacitor K ............................ Relay TP . . . . . . . . . . . . . . . . . . . . . . . Test Point
........................ Coupler L ..................... Coil, Inductor U ...... Integrated Circuit, Microcircuit
. . . . . . . . . . . Diode, Diode Thyristor, M ........................... Meter V . . . . . . . . . . . . . . . . . . . . . Electron Tube
Step Recovery Diode, Varactor MP . . . . . Miscellaneous Mechanical Part VR . . . . . . . . . Breakdown Diode (Zener),
.............. Directional Coupler P ............... Electrical Connector Voltage Regulator
...................... Delay Line (Movable Portion), Plug W . . . . . . . . . . . . . . Cable, Wire, Jumper
......... Annunc~ator,Lamp, Light Q . . . . . . . . . Silicon Controlled Rectifier X ........................... Socket
Emitting Diode (LED), (SCR), Transistor, Y .......... Crystal Unit (Piezoelectric,
Signaling Device (Visible) Triode Thyristor Quartz)
. . . . . . . MiscellaneousElectrical Part R .......................... Resistor Z ......... Tuned Cavity, Tuned Circuit
ABBREVIATIONS
CPRSN . . . . . . . . . . . . . . . . Compression FDTHRU . . . . . . . . . . . . . . Feed Through
CUP-PT . . . . . . . . . . . . . . . . . . Cup Point F E M . . . . . . . . . . . . . . . . . . . . . . . . Female
A . . . . . . . . . . . Across Flats, Acrylic, Air CW . . . . . . . . . . . . . . . . . . . . . Clockwise, FIL-HD ................ Fillister Head
(Dry Method), Ampere Continuous Wave FL ................. Flash, Flat, Fluid
ADJ ............. Adjust, Adjustment FLAT-PT ................. Flat Point
ANSI ............. American National FR ........................... Front
Standards Institute FREQ .................... Frequency
(formerly USASI-ASA) D ............ Deep, Depletion, Depth, FT . . . . . . . . . . . Current Gain Bandwidth
ASSY ..................... Assembly Diameter, Direct Current Product (Transition Frequency),
AWG ............ American Wire Gage DA ...................... Darlington Feet, Foot
DAP-GL ....... Diallyl Phthalate Glass FXD . . . . . . . . . . . . . . . . . . . . . . . . . Fixed
DBL ........................ Double
DCDR ..................... Decoder
BCD ........... Binary Coded Decimal DEO . . . . . . . . . . . . . . . . . . . . . . . . Degree
BD . . . . . . . . . . . . . . . . . . . Board, Bundle D-HOLE ............. D-Shaped Hole
DIA . . . . . . . . . . . . . . . . . . . . . . Diameter GEN ............. General, Generator
BE-CU ............. Beryllium Copper GND . . . . . . . . . . . . . . . . . . . . . . . Ground
BNC .............. Type of Connector DIP ............ Dual In-Line Package
DIP-SLDR ................ Dip Solder GP . . . . . . . . . . . General Purpose, Group
BRG ................ Bearing, Boring
BRS.. ........................ Brass D-MODE ............ Depletion Mode
BSC .......................... Basic DO ......... Package Type Designation
BTN ........................ Button DP ........... Deep, Depth, Diametric
Pitch, Dip H . . . . . . . . . . . . . . . . . . . . . . Henry,High
DP3T ............. Double Pole Three HDW . . . . . . . . . . . . . . . . . . . . Hardware
Throw HEX . . . . . . . . . Hexadecimal, Hexagon,
C ............ Capacitance, Capacitor, DPDT ........... Double Pole Double Hexagonal
Center Tapped, Cermet, Throw HLCL . . . . . . . . . . . . . . . . . . . . . . Helical
Cold, Compression DWL ........................ Dowel HP ........ Hewlett-Packard Company,
CCP ...... Carbon Composition Plastic High Pass
CD ............ Cadmium, Card, Cord
CER ....................... Ceramic E-R . . . . . . . . . . . . . . . . . . . . . . . . . E-Ring
CHAM .................... Chamfer EXT . . . . . . . . . . . . Extended, Extension,
CHAR ................... Character, External, Extinguish 1C . . . . . . . . . . . . . . . . Collector Current,
Characteristic, Charcoal Integrated Circuit
CMOS ......... Complementary Metal ID . . . . . . . . . . . . . . Identification, Inside
Oxide Semiconductor Diameter
CNDCT . . . . . . Conducting, Conductive, F . . . . . . . . . . Fahrenheit, Farad, Female, IF . . . . . . . . . . . . . . . . . Forward Current,
Conductivity, Conductor Film (Resistor), Fixed, Intermediate Frequency
CONT .......... Contact, Continuous, Flange, Frequency IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inch
Control, Controller FC . . . . . . . . Carbon Film/Composition, INCL . . . . . . . . . . . . . . . . . . . . . Including
CONV.. .................. Converter Edge of Cutoff Frequency, Face INT . . . . . . . . Integral, Intensity, Internal
MODEL 8559A REPLACEABLEPARTS
MULTIPLIERS
ALLEN-BRADLEY CO MILWAUKEE, WI
TEXAS INSTR INC SEMICOND CMPNT DIV DALLAS, TX
SPECTROL ELECTRONICS CORP CITY O F IND, CA
BUNKER RAM0 C O W AMPHENOL CONN DIV BROADVILLE, IL
ILLINOIS TOOL WORKS INC FASTEX DIV DES PLAINES, IL
K D I PYROFILM C O W WHIPPANY, NJ
MOTOROLA SEMICONDUCTOR PRODUCTS PHOENIX, AZ
PANDUIT CORP TINLEY PARK, IL
PRECISION MONOLITHICS INC SANTA CLARA, CA
KELVIN ELECTRIC CO VAN N W S , CA
FAIRCHILD SEMICONDUCTOR DIV MOUNTAIN VIEW, CA
CTS O F BERNE INC BERNE, IN
SILICONIX INC SANTA CLARA, CA
MEPCOIELECTRA CORP MINERAL WELLS, TX
MICRO-OHM CORP EL MONTE, CA
TRANSITRON ELECTRONIC C O W WAKEFIELD, MA
CORNING GLASS WORKS (BRADFORD) BRADFORD, PA
NATIONAL SEMICONDUCTOR CORP SANTA CLARA, CA
HEWLETT-PACKARD CO CORPORATE HQ PAL0 ALTO, CA
RCA CORP SOLID STATE DIV SOMERVILLE, NJ
AAVID ENGINEERING INC LACONIA, NH
MEPCOIELECTRA CORP SAN DIEGO, CA
BOURNS INC TRIMPOT PROD DIV RIVERSIDE, CA
SPECTRUM CONTROL INC FAIRVIEW, PA
MALLORY P R AND CO INC INDIANAPOLIS, IN
EXAR INTEGRATED SYSTEMS INC SUNNYVALE, CA
STETTNER ELECTRONICS INC CHATTANOOGA, TN
SPRAGUE ELECTRIC CO NORTH ADAMS, MA
BOSTON GEAR WKS DIV O F NA ROCKWE QUINCY, MA
ELECTRO MOTIVE C O W FLORENCE, SC
ERIE TECHNOLOGICAL PRODUCTS INC ERIE, PA
BECKMAN INSTRUMENTS INC HELIPOT DIV FULLERTON, CA
JOHNSON E F CO WASECA, MN
TEK BEARING CO INC NEW YORK, NY
MODEL 8559A REPLACEABLE PARTS
ACCESSORIES S U P P L I E D
S I D E STOP K I T
ADAPTER, T Y P E N M A L E T O
BNC FEMALE
C R T -O V E R L A Y , H P 1 8 0 SERIES
DISPLAYS
C R T -O V E R L A Y . H P 1 8 1 SERIES
DISPLAYS
C R T -O V E R L A Y . H P 1 8 2 SERIES
DISPLAYS
E C O N O M Y S.A. O P E R A T I O N B O O K L E T
MODEL 8559A REPLACEABLE PARTS
ELECTRICAL
C A B L E ASSEMBLY, R F INPUT T O
ATTENUATO R
C A B L E ASSEMBLY, A T T E N T O F I R
MIXER
C A B L E ASSEMBLY, Y T O T O FIRST
MIXER
C A B L E ASSEMBLY, C A L OUTPUT
C A B L E ASSEMBLY, V E R T O U T
MECHANICAL
PANEL, F R O N T 0 8 5 5 9 -0 0 0 3 0
GUSSET, L E F T S I D E 0 8 5 5 9 -0 0 0 3 8
GUSSET, R I G H T S I D E 08559-00037
PANEL, R E A R 0 8 5 5 9 -0 0 0 0 3
RAIL. G U I D E TOP 5061-5426
EXTRUSION, C I R C U I T ENCLOSURE,
TAPPED
EXTRUSION. E N D P L A T E ENCLOSURE
EXTRUSION, C I R C U I T ENCLOSURE,
TAPPED
EXTRUSION, CIRCUIT ENCLOSURE
WINDOW, FREQ. D I S P L A Y
RAIL, GUIDE BOTTOM
C A B L E ASSY (W5) V E R T I C A L O U T P U T
SCREW. M A C H 4 -4 0 . 2 5 I N L G 8 2 D E G
SCREW, M A C H 6 -3 2 . 3 1 2 I N L G
F L - H D-POZI
SCREW, M A C H 6 -3 2 .25 I N L G
F L - H D-POZI
SCREW. M A C H 6 -3 2 .5 I N L G
P A N -H D -P O Z I
SCREW. TPG 4 - 4 0 . 3 7 5 I N L G
P A N -H D -P O Z I
SCREW, M A C H 4 - 4 0 . 2 5 I N L G
P A N - H D -P O Z I
SCREW. M A C H 4 -4 0 .625 I N L G 8 2 D E G
SPACER, R N D . 3 1 2 I N L G . 1 8 - I N - I D
NUT. H E X PLSTC L K G 4-40 T H D . I 4 1
IN THK
SCREW. M A C H 4-40 . I 8 8 I N L G U N C T
82 DEG
SCREW, M A C H 4 -4 0 .438 I N L G
PAN-HD-POZI
COVER. T H I R D C O N V E R T E R
C O V E R . B A N D W I D T H F I L T E R NO. 1
COVER, STEP G A I N
C O V E R , B A N D W I D T H F I L T E R NO. 2
COVER, L O G A M P
W A S H E R . F L - M T L C NO. 4 . I 2 5 I N I D
N U T . H E X - W / L K W R 6-32 T H D . l o 9
IN THK
WASHER. F I B E R
WASHER. L K I N T L 7/16 I N .439 I N I D
N U T . H E X D B L - C H A M 7/16 - 2 8 T H D
,125 I N T H K
B E Z E L , PB ,330 I N SQ: J A D E G R A Y
PUSHBUTTON, S Q U A R E : W I L L O W
GREEN
POINTER, INPUT A T T E N U A T O R
SPRING. C O N I C A L
K N O B ASSY, R E F E R E N C E L E V E L
I N D E X DISK, REFERENCE L E V E L
R E T A I N E R , R I N G E X T ,188 I N D I A ,
BE CU
K N O B ASSY, R E F L E V E L F I N E
K N O B ASSV, R E S O L U T I O N B W
K N O B ASSY. F R E Q S P A N / D I V
KNOB, L O C K
R F I N P U T ASSY
CABLE. R F INPUT
SECTION VII
MANUAL BACKDATING CHANGES
2320A & Below Under Para. No. 4-13. Residual FM, change the maximum Peak-to-
Peak Variation of Trace in test 6 to 0.7 div ( 1 kHdO.1 sec).
- Pages 5-11 through 5-13:
2236A & Below Replace Paragraph 5-17 w i t h new Paragraph 5-17 (SERIAL PREFIX
2236A) included i n t h i s Manual Backdating supplement.
ADJUSTMENTS
/--
DESCRIPTION:
The + 14.5V and - 10V supplies on Frequency Control Assembly A7 are adjusted. The - 12.OV supply on A7
is checked for proper dc output with less than +50 mV variation when tuning the HP 8559A from 0 to 3 GHz.
The + 10.OV supply on Sweep Generator/Bandwidth Control Assembly A9 is adjusted and the VO (Varactor
Offset) voltage on Marker Assembly A8 is adjusted. The + 10.OV supply and VO voltage must be adjusted
during the first five minutes after the spectrum analyzer is turned on (cold instrument). However, the + 14.5V
and - 10.OV supplies must be adjusted first.
DISPLAY
. DIGITAL VOLTMETER
.
SPECTRUM
EXTENDER
ASSEMBLY
EQUIPMENT:
Digital Voltmeter .... . ... . . . . . ........ . . . . .. . ..................... ,...... HP 349OA
PROCEDURE:
1. Connect equipment as shown in Figure 5-1. Install Frequency Control Assembly A7 on extender board
and connect digital voltmeter to A7TP3 + 14.5y
2. Adjust A7R52 + 14.5V adjustment for a voltmeter indication of + 14.500 k 0.002 volts.
3. Connect digital voltmeter to A7TP2 and adjust A7R55 - 10V adjustment for a voltmeter indication of
*
- 10.000 0.005 volts.
NOTE
7. Connect digital voltmeter to A9TP6 + 10V and adjust A9R2 + 10V adjustment for a vokmeter indication
of + 10.000 Zk 0.100V.
9. The voltage at A8TP2 will change (between two values) each time a sweep is triggered. l'kigger the sweep a
few times and select the sweep that yields the least negative VO voltage. Adjust A8R62 VO adjustment for
a voltmeter indication of - 2.00 +_ 0.10V.
Pages 5-17 through 5-23:
2208A & Below Replace Paragraph 5-19 with new Paragraph 5-19 (SERIAL PREFIX
2208A) included i n t h i s Manual Backdating supplement.
ADJUSTMENTS
5.19. LOG AMPLIFIER LOG AND LINEAR ADJUSTMENT (SERIAL PREFIX 2208A)
REFERENCE:
DESCRIPTION:
10 dB/DIV and LIN are adjusted for correct steps and full-screen display translations.
F
UTPUT
ATTENUATOR
EQUIPMENT:
PROCEDURE:
1. Set spectrum analyzer controls as follows:
5-19. LOG AMPLIFIER LOG AND LINEAR ADJUSTMENT (SERIAL PREFIX 22O8A) (Cont'd)
Connect equipment as shown in Figure 5-3. Set signal generator frequency to 321.4 MHz and output level
to - 40 dBm. Remove AlOW 1from A5J2 2nd CONV OUT. Connect signal generator output through step
attenuator and adapters to AlOWl.
Set the TEST-NORM switch A12S1 to the TEST position. T h e signal generator frequency for maximum
signal amplitude on oscilloscope display with step attenuator set at 0 dB.
Set output level of signal generator for a digital voltmeter reading of 700 mV, with step attenuator set at 0
dB and REF LEVEL dBm set to - 50.
Set HP 8559A REF LEVEL dBm to - 80 and set step attenuator to 30 dB. Observe digital voltmeter
reading.
Adjust A14R3 GAIN LIN for a digital voltmeter reading of 700 mV.
Repeat steps 4,5, and 6 until the DVM reading in step 5 is 700 +2 mV.
Set HP 8559A REF LEVEL dBm to - 50 and set step attenuator to 0 dB. Change REF LEVEL dBm and
step attenuator settings as shown in Table 5-6. If Deviation from Reference is not within the given limits,
readjust Al4R3.
TABLE 5-6. LINEAR GAIN ADJUSTMENT LIMITS
I Reference Level
hJB4
-50
Step Attenuator
Setting (dB)
Deviation From
Reference
0 Reference(700 mV)
-60 10 *lo mV
-70 20 k20 mV
-80 30 k20 mV
-90 40 k30 mV
d
Set HP 8559A REF LEVEL dBm to 0 and disconnect signal generator from step attenuator. Record offset
reading (DVM). The offset should be less than +30 mY
Offset mV
Reconnect signal generator as shown in Figure 5-3. Set Amplitude Scale to 10 dB/DIV and set step
attenuator to 40 dB.
Set output level of signal generator for a digital voltmeter reading of 400 mV plus offset recorded in step
9 (algebraic sum). (Example: if offset if - 23 mV, set output levelof signal generator for a DVM reading of
377 my)
ADJUSTMENTS
5-19. LOG AMPLIFIER LOG AND LINEAR ADJUSTMENT (SERIAL PREFIX 22O8A) (Cont'd)
*
12. Set step attenuator to 0 dB. Digital voltmeter should indicate 800 mV, plus offset (algebraic sum) 1 mV.
If DVM reading is not within limits, adjust A14R2 LOG LIN adjustment for a digital voltmeter reading of
800 mV, plus offset minus 50 percent of overshoot. (Example: if DVM indicates 767 mV and should be
indicating 777 mV (- 10 mV overshoot), adjust A14R2 for a DVM reading of 777 mV minus - 5 mV, or
782 m l )
13. Repeat steps 10, 11, and 12 until the digital voltmeter indicates 800 mV plus offset f1 mV with no further
adjustment of Al4R2 in step 12.
14. Set the step attenuator to the positions shown in Table 5-7 and record DVM reading for each setting.
Correct the DVM readings by algebraically adding the offset (recorded in step 9).
TABLE 5-7. LOG FIDELITY CHECK
17. Set Amplitude Scale to LIN. The digital voltmeter should indicate the reading set in step 16 *25 mV. If it
does, go to step 19. If it does not, or if log fidelity is not within limits, go to step 18 and select A14R16*.
18. Select A14R16* to obtain an output in step 17 within f 25 mV of the reading set in step 16. Decreasing
A14R16* 10 percent will increase the DVM reading approximately 30 mV in step 17.
NOTE
Log fidelity must be considered when selecting A14R16*. That is, if the
DVM READING CORRECTED FOR OFFSET in Table 5-7 is greater than 100
mV for a STEP ATTENUATOR SETTING of 70 dB, A14R16* should be
selected for a DVM reading greater than the reading set in step 16. If the
READING CORRECTED FOR OFFSET is less than 100 mV, A14R16* should
be selected for DVM reading less than the reading set in step 16.
ADJUSTMENTS
519. LOG AMPLIFIER LOG AND LINEAR ADJUSTMENT(SERIAL PREFIX 22O8A) (Cont'd)
Set output level of signal generator for a digital voltmeter reading of 800 mV plus offset (algebraic sum)
f lmY
Set Amplitude Scale to 10 dB/DIV and adjust A14R2 LOG LIN adjustment for a digital voltmeter reading
of 800 mV plus offset.
Set the step attenuator to 0 dB and set output level of signal generator for a digital voltmeter reading of 700
mV (do not include offset).
Set the REF LEVEL dBm control to - 90 and the step attenuator to 40 dB. Adjust A14R1,LOG GAIN
adjustment for a digital voltmeter reading of 700 mY
Change REFERENCE LEVEL and step attenuator settings as shown in Table 5-8. Deviation from Refer-
ence should not exceed the given limits.
1909A & Below Replace Paragraph 5-21 w i t h new Paragraph 5-21 (SERIAL PREFIX
1909A) included i n t h i s Manual Backdating supplement.
ADJUSTMENTS
REFERENCE:
DESCRIPTION:
The crystal and LC bandwidth filter circuits are adjusted for symmetry, center, and peak. ThreedB bandwidths
are adjusted in Sweep Generator/Bandwidth Control Assembly A9 (paragraph 5-22).
SPECTRUM
DISPLAY ANALYZER
0 0 0 00.0
INPUT
OUTPUT
ADAPTER
6" BNC
EXTENDER CABLE
CABLE
ASSEMBLY
EQUIPMENT:
Adapter, Type N Male to BNC Female .................................... HP 12504780
BNC Cable, 6-Inch ...................................................... HP 10502A
Crystal Short (3 required) .............................................. See Figure 5-6
NOTE
A crystal short consists of a .O1 pF capacitor (HP Part Number 0160-0161)
and a 90.9 ohm resistor (HP Part Number 0757.0400) connected in series.
Two square terminal connectors (HP Part Number 03624265) are used to
connect the crystal short across the test points.
CAPACITOR RESISTOR
TERMINAL CONNECTORS
FIGURE 56. CRYSTAL SHORT CONFIGURATION
ADJUSTMENTS
,
5-21. BANDWIDTH FILTER ADJUSTMENTS(SERIAL PREFIX 1909A)(Cont'd)
PROCEDURE:
NOTE
Crystal Alignment
Center the signal with TUNING control. Using REF LEVEL FINE control, place signal at 7.1 divisions
(0.9 division from top graticule line).
Adjust A9R85 LC until signal is two divisions wide at the fifth graticule line (1 MHz wide at 3-dB points).
Adjust A9R72 XTL until signal is one division wide at the fifth graticule line (10 kHz wide at 3 d B points).
Center signal with TUNING control. (It might be necessary to increase FREQ SPAN/DIV temporarily to
find the signal.) Set REF LEVEL FINE control to place signal at sixth gratiwle line.
NOTE
Do not readjust REF LEVEL FINE control until all crystal and LC bandwidth
filter adjustments have been performed.
ADJUSTMENTS
12. Connect crystal shorts (through cover access holes) across A13TPWTP2, A1 lTPl/TP2, and A1 1TP4/
TP5.
NOTE
Keep crystal spike centered during adjustments. The SYM and CTR adjust-
ments for each crystal are interacting.
13. Adjust front-panel TUNING control to center bandpass spike (Figure 5-7) on the CRT display.
CHECK CENTERING
HERE (SPIKE IS
CRYSTAL RINGING)
CHECK SYMMETRY
HERE (LOW ON SKIRTS)
14. Adjust A13C38 SYM and A13C54 CTR for a centered and symmetrical bandpass as shown in Figure 5-7.
Adjust A13C54 CTR for minimum signal amplitude.
18. Adjust A11C38 SYM and AllC54 CTR for a centered and symmetrical bandpass. Adjust AllC54 for
minimum signal amplitude.
20. Adjust AllC15 SYM and AllC25 CTR for a centered and symmetrical bandpass. Adjust AllC25 for
minimum signal amplitude.
LC Alignment
NOTE
When Bandwidth Filter Assemblies A11 and A13 are installed with covers in
place, midget copper alligator clips (HP Part Number 1400-0483)can be used
to short test points to the cover.
a. Install A13 on extender board.
b. Short to ground the following test points: A13TP6, AllTP3, and AllTP6. Jumper A9TPl to
A9TP2.
23. Carefully center signal on CRT in 30 kHz RESOLUTION BW; then switch RESOLUTION BW to 100
kHz. Note where signal intersects the center vertical graticule line.
24. Adjust A13C45 LC CTR for maximum signal amplitude where the signal intersects the center vertical
graticule line.
25. Switch RESOLUTION BW to 30 kHz and center signal; then switch to 100 kHz. Note where signal
intersects the center vertical graticule line.
26. Adjust A13C23 LC CTR for maximum signal amplitude where the signal intersects the center vertical
graticule line.
27. Switch RESOLUTION BW to 30 kHz and center signal; then switch to 100 kHz. Note where signal
intersects the center vertical graticule line.
28. Adjust A1 lC45 LC CTR for maximum signal where the signal intersects the center vertical graticule line.
29. Switch RESOLUTION BW to 30 kHz and center signal; then switch to 100 kHz. Note where signal
intersects the center vertical graticule line.
30. Adjust AllC23 LC CTR for maximum signal amplitude where the signal intersects the center vertical
graticule line.
3l. Switch RESOLUTION BW between 100 kHz and 30 kHz to be sure the signal is centered at both band-
width settings.
Bandwidth Amplitude
32. Set Amplitude Scale to 1 dB/DIV and SWEEP TIMWDIV to AUTO.
34. Adjust fine TUNING and REF LEVEL FINE for a centered signal at 7 divisions.
35. Set RESOLUTION BW to 100 kHz and center signal with fine TUNING control. Adjust A13R26 LC and
A1 1R26LC equally to obtain a signal amplitude of 7 divisions.
36. Set RESOLUTION BW to 1 kHz and FREQ SPAN/DIV to 10 kHz. Center signal with fine TUNING
control. Adjust A1 1R31XTL and A13R31 XTL equally for a signal amplitude of 7 divisions.
NOTE
Each potentiometer should be adjusted to accomplish half the necessary
increase in signal amplitude.
ADJUSTMENTS
,
5-21. BANDWIDTH FILTER ADJUSTMENTS (SERIAL PREFIX 1909A)(Cont'd)
37. Set FREQ SPAN/DIV to 10 kHz and RESOLUTION BW to 1 kHz with arrows aligned (OPTIMUM).
Push in to couple the two controls.
40. If variation in signal amplitude is not within limits, repeat steps 32 through 39.
Pages 5-33 through 5-37:
Paragraph 5-22. 3 dB Bandwidth Adjustslent
1909A & Below Replace Paragraph 5-22 with new Paragraph 5-22 (SERIAL PREFIX
1909A) included i n t h i s Manual Backdating supplement.
ADJUSTMENTS
/--
A9 Schematic
DESCRIPTION:
The 3-dB bandwidths for the 3 MHz, 1 MHz and 300 kHz RESOLUTION BW settings are adjusted using the
CAL OUTPUT as the signal source. The 3-dB bandwidths for the 10 kHz, 3 kHz, and 1 kHz RESOLUTION
BW settings are adjusted by injecting a stable 321.4 MHz signal into the third converter of the spectrum
analyzer.
DISPLAY SIGNAL GENERATOR FREQUENCY COUNTER
CABLE
-3
1
EXTENDER
ASSEMBLY
(2 I
),
3 ,
11111, ,111,
1) ( 3
SPECTRUM
ANALYZER
OUTPUT
PROCEDURE:
2. Connect equipment as shown in Figure 5-8 except for signal input to AlOW1. Connect CAL OUTPUT to
spectrum analyzer INPUT 5(X1.
ADJUSTMENTS
3. Set signal level of 7.1 divisions on display with REF LEVEL FINE control. (Signal should be 0.9 division
from top graticule line.)
4. Set RESOLUTION BW to 1 MHz and FREQ SPAN/DIV to 200 kHz. Adjust A9R85 LC to set band-
width of 5 divisions at the fifth graticule line.
5. Set RESOLUTION BW to 3 MHz and FREQ SPAN/DIV to 500 kHz. The bandwidth at the fifth grati-
cule line should be between 5.4 and 6.6 divisions.
NOTE
A9R85 LC may be further adjusted to bring the 3 MHz and 300 kHz band-
widths within limits; however, the final measurement of the 1 MHz band.
width must be between 4.5 and 5.5 divisions at the fifth graticule line. (If the
3 MHz bandwidth cannot be brought within limits by adjustment of A9R85
LC, change the value of factory-selected resistor A9R95*.)
6. Set RESOLUTION BW to 300 kHz and FREQ SPAN/DIV to 50 kHz. The bandwidth should be between
5.4 and 6.6 divisions at the fifth graticule line. (If the bandwidth cannot be adjusted within the specified
limits, change the value of factory-selected resistor AgR89*.)
7. Set RESOLUTION BW to 100 kHz and FREQ SPAN/DIV to 20 kHz. The bandwidth should be between
4.3 and 5.7 divisions at the fifth graticule line.
NOTE
If the 100 kHz bandwidth is not within the specified limits, change the
values of factory-selectedresistors A13R19*, A13R43*, and A11R43*. If the
bandwidth is too wide, increase the value of the resistors; if the bandwidth
is too narrow, decrease the value of the resistors. The three factory-selected
resistors need not be of equal value, but each must be within one standard
value of the others.
8. Set RESOLUTION BW to 30 kHz and FREQ SPAN/DIV to 10 kHz. The bandwidth should be between
2.6 and 3.4 divisions at the fifth graticule line.
NOTE
If the 30 kHz bandwidth is not within the specified limits, change the values
of factory-selected resistors A11R23*, A11 R48*, A13R23*, and A13R48*. If
the bandwidth is too wide, decrease the value of the factory-selected resis-
tors; if the bandwidth is too narrow, increase the value of the resistors. The
four factory-selectedresistors need not be of equal value, but each must be
within one standard value of the others.
9. Connect signal generator through the BNC Tee connector to the step attenuator and to the frequency
counter as shown in Figure 5-8. Set the signal generator to approximately 0 dBm and the step attenuator to
30 dB.
ADJUSTMENTS
/-
10. Remove AlOWl from A5J2 2nd CONV OUT Connect step attenuator through adapter to A1OW1.
11. Set HP 8559A RESOLUTION BW to 1 MHz. Adjust the output level of signal generator to place the
signal near center graticule line. Tune signal generator frequency to peak signal on oscillo~copedisplay
(near 321.4 MHz).
12. Set RESOLUTION BW to 3 kHz. Tune signal generator to peak signal on oscilloscope display.
13, Adjust output level of signal generator to place signal at 7.1 divisions.
14. Note the counter frequency and tune the signal generator 1500 Hz below the center frequency noted.
Record the new counter frequency.
MHz
15. Adjust A9R72 XTL to bring signal level to the fifth graticule line (three divisions from the top graticule
line).
16. Increase signal generator frequency until signal on oscilloscope display peaks and then decreases to the
fifth graticule line. Record counter frequency.
MHz
17. Compare new frequency with frequency recorded in step 14. The difference between the two frequencies
should be 2800 to 3200 Hz. If the bandwidth is not within limits, repeat steps 12 through 17, slightly
readjusting A9R72 XTL, until the specified limits are achieved.
18. Set RESOLUTION BW to 10 kHz. Tune signal generator to peak signal on oscilloscope display.
24). Decrease the signal generator frequency until the signal on the oscilloscope display drops to the fifth
graticule line. Record counter frequency.
MHz
21. Increase the signal generator frequency until the signal on the oscilloscope display peaks and then
decreases to the fifth graticule line. Record counter frequency.
MHz
ADJUSTMENTS
*
Compare new frequency with frequency recorded in step 20. The difference between the two frequencies
should be 9.000 kHz to 11.000 kHz.
NOTE
A9R72 XTL may be further adjusted to bring the 10 kHz and 1 kHz band-
widths within limits; however, the final measurement of the 3 kHz bandwidth
must be between 2700 Hz and 3300 Hz. (If the 10 kHz bandwidth cannot be
brought within limits by adjustment of A9R72 XTL, change the value of fac-
tory-selected resistor A9R78*.)
Set RESOLUTION BW to 1 kHz. n n e signal generator to peak signal on oscilloscope display.
Adjust REF LEVEL FINE to place signal at 7.1 divisions. Record counter frequency.
MHz
Increase signal generator frequency until signal on oscilloscope display drops to the fifth graticule line.
Record new counter frequency.
MHz
The difference between the two frequencies recorded in steps 24 and 25 should be 450 Hz to 550 Hz.
2236A & Below Replace Paragraph 5-25 with new Paragraph 5-25 (SERIAL PREFIX
2236A) included i n t h i s Manual Backdating supplement.
DESCRIPTION:
The First LO (A6 YTO) is adjusted by monitoring the YTO output at the RF input connector (LO feedthrough)
and the tuning voltage(TUNE)output of the A7 Frequency Control board and adjusting the YTO low-end
frequency for 3 GHz at OV tuning voltage and 6 GHz at - 10V tuning voltage.
The FM Driver is adjusted by inputting comb signals to the analyzer and adjusting for proper spacing (span
linearity) of displayed signals on the CRT display.
COMB
DISPLAY DIGITAL VOLTMETER FREQUENCYCOUNTER GENERATOR
I
INPUT
P OUTPUT
Al6TPl
-
EXTENDER LOCATED A7TP4
CABLE THROUGH TUNE
ASSEMBLY
HOLEIN / \
SIDE FRAME .fq :%?: SPECTRUM
HERE
;
((9 , ,.,-
io)'(i3fd
,,,,or, *
ANALYZER
INPUT
PROCEDURE:
1. Allow one-half hour warmup time of equipment with analyzer connected to mainframe with extender
cable.
First LO Adjustments
Jumper A16TP1 DIODE BIAS to Ground. A16TP1 is located on the Motherboard through a hole in the
analyzer side frame.
Adjust front-panel TUNING control for DVM indication of 0.000 Vdc (fully counterclockwise).
Adjust A7R74 3 GHz for frequency counter indication of 3.000 GHz +1 MHz. If this adjustment cannot
be achieved, selectable resistor A7R94* can be changed to provide the proper range necessary.
Adjust A8R28 6 GHz C (coarse) for a frequency counter indication of 6.000 GHz *2 MHz.
Retune front-panel TUNING control for 0.000 Vdc DVM indication and readjust A7R74 3 GHz if neces-
sary for frequency counter indication of 3.000 GHz +1 MHz.
Lightly tap the top edge of the A7 Frequency Control board with the handle of a small screwdriver to seat
controls.
Adjust A7R95 6 GHz F (fine) for frequency counter indication of 6.000 GHz +1 MHz.
Alternate IF First LO Shift Check
15. Press front-panel ALT IF pushbutton IN to activate alternate IE
18. Disconnect frequency counter from analyzer RF Input and connect comb generator to RF Input,
21. T h e front-panel TUNING control for approximately 1500 MHz indication on front-panel FREQUENCY
display.
22. Adjust front-panel TUNING FINE control to place a comb tooth on the first graticule line on the main-
frame CRT display.
23. Adjust A7R38 FM to place a comb tooth on the ninth graticule line.
24. Readjust TUNING FINE control to place a comb tooth on the first graticule line and adjust A7R38 FM to
place a comb tooth on each of the graticule lines while keeping the first comb tooth aligned using the
TUNING FINE control.
25. T h e to approximatel./ 100 MHz and verify that when a comb tooth is placed on the first graticule line
using the TUNING FINE control that the ninth comb tooth is aligned with the ninth graticule line 1 *
minor division.
29. Adjust front-panel TUNING control for 100 MHz indication on FREQUENCY display
31. Adjust TUNING to place 100-MHz comb tooth on center graticule line.
ADJUSTMENTS
,
5-25. FIRST CONVERTER ADJUSTMENTS(SERIAL PREFIX 2236A)(Cont'd)
32. Set FREQ SPAN/DIV to 1 MHz. Note position of comb tooth.
33. Adjust A7R99 MO to place comb tooth midway between position noted in step 32 and center graticule
line.
34. Set FREQ SPAN/DIV to 2 MHz.
36. Set FREQ SPAN/DIV to 1 MHz. Note displacement of comb tooth from center graticule line.
37. Repeat steps 30 through 36 until displacement of comb tooth is less than 0.2 major division when FREQ
SPAN/DIV is switched from 2 MHz to 1 MHz.
/-
Page 6-7:
2236A & Below Change item (21, GUSSET, LEFT, t o HP P a r t Number 08559-60032,
Check Digit 4.
Change item ( 3 ) , GUSSET, RIGHT, t o HP P a r t Number 08559-60031,
Check Digit 3.
2218A & Below Replace Table 8-1 with new Table 8-1 (SERIAL PREFIX 2218A)
included i n t h i s Manual Backdating supplement.
2218A & Below Replace Figure 8-5 with new Figure 8-5 (SERIAL PREFIX 2218A)
included i n t h i s Manual Backdating supplement.
2218A & Below Replace Figure 8-6 with new Figure 8-6 (SERIAL PREFIX 2218A)
included i n t h i s Manual Backdating supplement.
DPH D I S P L A Y PA480
C O I L , 540UH 28400
INDIICTOR R F - C I I HLD 27OUH 5 %
INDUCTOR RF- CH HL D 240UH 5 % .. 1 bhOX. 3851 G
l b h D X .3E5LG
713480
20480
01121
OFFSET
AlAl
DPM DISPLAY
FIGURE 85. DIGITAL PANEL METER ASSEMBLY Al, COMPONENT LOCATIONS(SERIAL PREFIX 2218A)
/-
Pages 8-25 through 8-49/8-50: FROtiI WITCH JBSEllBLY A2
2208A & Below Replace Table 8-2 with new Table 8-2 (SERIAL PREFIX 2208A)
included i n t h i s Manual Backdating supplement.
TABLE 8-2. FRONT SWITCH BOARD ASSEMBLY A2, REPLACEABLEPARTS (2 OF 2) (SERIAL PREFIX 2218A)
Reference
-
HP Part Mfr
Designation Description Mfr Part Number
Number
-
Code
2R4:\0
:!I1400
,'04110
?I14110
:'84110
X~IXI
704::n
7114110
7R.III0
34no
2H4l7O
28400
4 7 HIlilTI..LANEOU(i PARTS
2240A & Below Add A5MP3, HP P a r t Number 08559-20041, Check D i g i t 7, COVER, 2ND
L.O.
Under Miscellaneous P a r t s :
Change t h e q u a n t i t y of HP P a r t Number 2200-0119 from 7 t o 9.
Delete HP P a r t Number 2200-0156.
1951A00285 NOTE
& Below The following components have preferred replacements; A5C4 and
A5L2. I f t h e instrument does n o t contain t h e preferred
replacement values, a s shown i n t h i s Replaceable P a r t s l i s t and
Schematic i n t h e Manual, then both components should be changed
a t t h e same time.
2236A & Below Replace appropriate s e c t i o n s of Figure 8-25 with new P/O Figure
8-25 (SERIAL PREFIX 22361) included i n t h i s Manual Backdating
supplement .
1,
-I-
I A6 YIG-TUNED
YC -
FROM A7PI-21
YC+
FROM A7PI-20
YDR+ (+I5V)
I
FROM A7PI-24
+I4 5V
FROM A7PI-I0
I
-IOV I
FROM A7PI-32
YFM-
FROM A7Pl-15.37
I
YFM+
(GND) 3 >I 0
2236A & Below Replace Table 8-4 w i t h new Table 8-4 (SERIAL PREFIX 2236A)
i n c l u d e d i n t h i s Manual Backdating supplement.
2208A & Below Make t h e f o l l o w i n g changes t o new Table 8-4 (SERIAL PREFIX
22368 :
Change A7 t o HP P a r t Number 08559-60021, Check D i g i t 7.
Add A7C1 and A7C2, HP P a r t Number 0180-2208, Check D i g i t 6 ,
CAPACITOR-FXD 220UF +-lo% lOVDC TA.
Add A7Cl1, HP P a r t Number 0160-2055, Check D i g i t 9 , CAPACITOR-
.
FXD O1UF +80-20% 100VDC CER.
Delete t h e following:
A7C13, A7C14, A7CR8, A7CR9, A7Q19, and A7Q20.
Change A7R30 t o HP P a r t Number 0698-3428, Check D i g i t 1,
RESISTOR 14.7 1% .125W F TC=O+-100.
Change A7R31 t o HP P a r t Number 0757-0199, Check D i g i t 3,
RESISTOR 21.5K 1% .125W F TC=O+-100.
Add A7R98, HP P a r t Number 0757-0465, Check D i g i t 6, RESISTOR
lOOK 1% .125W F TC=O+-100.
Delete t h e following:
A7R100, A7R101, A7R102, A7U12, and A7VR1.
Add A7W1, HP P a r t Number 8159-0005, Check D i g i t 0 , WIRE 22AWG W
PVC 1x22 80C.
2236A & Below Replace F i g u r e 8-28 with new F i g u r e 8-28 (SERIAL PREFIX 2236A)
included i n t h i s Manual Backdating supplement.
2208A & Below Replace F i g u r e 8-28 with new F i g u r e 8-28 (SERIAL PREFIX 2208A)
included i n t h i s Manual Backdating supplement.
Add t h e f o l l o w i n g t o F i g u r e 8-28 (SERIAL PREFIX 2208A):
Add C12 between TP2 and t h e n e g a t i v e (-1 s i d e o f C8.
Add R99 t o t h e l e f t o f TP7.
HP Part
-
-
See introduction to this section for ordering information
*Indicates factory selected value
TABLE 84. FREQUENCY CONTROL ASSEMBLY A7, REPLACEABLE PARTS (3OF 3) (SERIALPREFIX 2236A)
FIGURE 828. FREQUENCY CONTROL ASSEMBLY A7, COMPONENT LOCATIONS (SERIAi PREFIX =A)
GND
YTO %
TUNE
+14.5V d
FIGURE 828. FREQUENCY CONTROL ASSEMBLY A7, COMPONENT LOCATIONS(SERIAL PREFIX 2208A)
YC +
4 0 2h5K
R30
14.7
I
PI-ISIOUTI
,,
FM FILTER
jLC.3
+lCl +LC2
220 220 PI-21 (OUT)
-
PI0 FIGURE 829. FREQUENCY CONTROL ASSEMBLY A7, SCHEMATICDIAGRAM (SERIAL PREFIX 22084
J
D
F
J
B
C
C
A
H
I
J
I
E
B
E
C
J
A
Table 8-5. Harker Assembly 88, Replaceable Parts
2309A & Below Replace Figure 8-32 with new Figure 8-32 (SERIAL PREFIX 2309A)
included i n t h i s Manual Backdating supplement.
2152A & Below Make t h e following changes t o new Figure 8-32 (SERIAL PREFIX
23OgA :
Delete A8CR21, A8R108, and A8R109.
Figure 8-33. Marker Assembly A8, Schematic Diagram (1 of 2)
Q R61
DPM ZERO '
PI0 FIGURE 8-33. MARKER ASSEMBLY A8, SCHEMATIC DIAGRAM (1OF 2) (SERIAL PREFIX 2309A)
SIC I D
9
R40
SOOK
U2B,C 3.10
OFF
4.11
,
R39
IY
PI0 FIGURE 8-33. MARKER ASSEMBLY A8, SCHEMATIC DIAGRAM (2 OF 2) (SERIAL PREFIX 2309A)
Pages 8-97 through 8-115/8-116: WEEP GEIlERATOR/BIWI[IYIDM C O m O L ASSEHBLY A9
21 07A01633 Replace Table 8-6 with new Table 8-6 (SERIAL PREFIX
& Below 2107A01633) included i n t h i s Manual Backdating supplement.
2203A & Below Replace Figure 8-39 with new Figure 8-39 (SERIAL PREFIX 2203A)
included i n t h i s Manual Backdating supplement.
2107A01633 Replace Figure 8-39 with new Figure 8-39 (SERIAL PREFIX
& Below 2107A01633) included i n t h i s Manual Backdating supplement.
.
CAPACITOR-FXD .O33UF + - l o % ZOOVDC POLYE
CAPACITOR-+FXD OIUF +8O--20% 1 ODVDC CER
CAPACITOR-FXD 3300PF + - l o % EOOVDC POLYE
28480
28480
28480
CAPACITOR-FXD 1OOOPF + - l o % 200VDC POLYE 28480
CAPACITOR-FXD 220PF +-5% 300VDC MICA 28480
OSCILLATOR S H I E L D 28480
THERMAL L I N K DUAL TO-18-CS 28480
PLUG-HOLE BDR-HD FOR ,187-D-HOLE NYL 02768
74546
2fl41i0
2454i,
15'101
;1!400
197111
01 l ? l
01121
24546
74596
2 1546
1')?01
74546
078fi8
:111:'1
2454b
24546
I C UP AMP L P T f l - 9 9 P K G 31.505
IC OP AMP CP DllAL TO - 9 9 PKI: TR 480
I C DP AMP bP 0 - T O 9 9 PKG ?04BO
-
See introduction to this section for ordering information
*Indicates factory selected value
A9
SWEEP GENERATOR/BANDWIDTH CONTROL
FIGURE 839. SWEEP GENERATORIBANDWIDTHCONTROL ASSEMBLY A9, COMPONENT LOCATIONS (SERIAL PREFIX 2107A01633)
I
RETRACE OUT BUFFER
+I4 5V
AMPLIFIER
R 39
10% k
PI- l (OUT1
PE
@ PULSE SHAPER
+ 15v
--
PI- 2 I I N )
SYNC
-2411N)
I TRIGGER
SWITCH
I L
SINGLE
221 8 A & Below Replace Figure 8-43 with new Figure 8-43 (SERIAL PREFIX 2218A)
included i n t h i s Manual Backdating supplement.
2218A & Below Replace funcbion block (J) of Figure 8-44 w i t h new P/O F i g u r e 8-
44 (SERIAL PREFIX 2218A) included i n t h i s Manual Backdating
supplement .
Make t h e following changes i n f u n c t i o n block (Dl.
Change R6 t o 1000.
Cliange R8 t o 750.
Change R11 t o 162.
Change -10.6 VF t o -12.6 VF i n two places.
"4 THIRD CONVERTER
8
AlOWl
321.4 MHz
IF IN
Q
321.4 MHz
BPF
C10 -
ADJUST
Cll ,R13
Q
CAL AMPL
c 1 2 H CAL FREO
J1
300 MHz
LO OUT
(TEST CONNECTOR)
?J
LO ADJ
PI- 24
5.11v
PI-23
- 12 6VF
R19 *
NOTE
6 BpF
C I ~R 3 2 R4
220pF 4 6 4 K IOK
R26
+ IOVF IOOK
+ IOVF
LC
(FEEDBACK)
PI0 FIGURE 856. BANDWIDTH FILTER NO. 1 ASSEMBLY All, SCHEMATIC DIAGRAM (SERIAL PREFIX 1909A)
Pages 8-143 through 8-155/8-156: STEP GAIIY ASSJ9lBLY A12
I FEEDBACK)
PI0 FlGURE8-63. BANDWIDTH FILTER NO. 2ASSEMBLY A13, SCHEMATIC DIAGRAM (SERIAL PREFIX 1909A)
/
-
'
Pages 8-167 through 8-179/8-180: LOG MPLIFIER ASSEHBLY A14
Table 8-12. Log Amplifier Assembly A14, Replaceable Parts
2208A & Below Replace Table 8-12 w i t h new Table 8-12 (SERIAL PREFIX 2208A)
included i n t h i s Manual Backdating supplement.
2208A & Below Replace F i g u r e 8-68 with new F i g u r e 8-68 (SERIAL PREFIX 2208A)
included i n t h i s Manual Backdating supplement.
LOG A M P L I F I E R 28480
CAPACITOR- FXD
CAPACITOR- FXD
..O2UF
O1UF t 8 0 - 2 0 % OOVDC CCR
I
+- 20% 1OOVDC CER
20480
20400
CAPACITOR- FXD , 0 2 U F +- 20% lOOVDC CER 28480
CAPACITOR- FXD . O I U F + 0 O - 2 0 % lOOVDC CER 28480
CAPACITOR- FXD . O I U F + 8 0 - 2 0 % lOOVDC CER 30480
CAPACITOR- FXD
CAPACITOR- FXD
..O1UF
OIUF m o - 2 0 % IOOVDC CER
+ 8 0 - 2 0 % IOOVDC CFR
20480
2D4RO
CAPACITOR- FXD . 5 1 P F + - . 2 5 P T 5OOVDC CER 28480
CAPACITOR-FXD .OIUF + 8 0 - 2 0 ~ IOOVDC c r R 28480
CAPACITOR- FXD 1 P F +- . 2 5 P F 5OOVDC CER 20480
.
CAPACITOR -FXD OIUF + 8 0 - 2 0 % IOOVDC CER 28480
CAPACITOR- FXD . O l U F + 8 0 - 2 0 % IOOVDC C€R 28480
.
CAPACITOR- FXD OIUF + 8 0 - 2 0 % 1 OOVDC CER
CAPACITOR- FXD . O l U F + 8 0 - 2 0 % I O O V D C T E R
20480
28480
CAPACITOR- FXD I P F + - . 2 5 P F 5OOVDC CER 20480
.
CAPACITOR- FXD . O I U F +8O-20%
CAPACITOR- FXD O1UF t 8 0 - 2 0 %
CAPACITOR- FXD . O I U F +8O-20%
IOOVDC
1 OOVDC
IOOVDC
CFR
CER
CER
20480
28480
20480
CAPACITOR -FXD .
OlUF t 8 0 - 2 0 %
CAPACITOR- FXD 9 . 1 P F + - . 2 5 P F
IOOVDC
SOOVDC
CER
CCR
28480
28480
CAPACITOR- FXD .
O1UF + 8 0 - 2 0 % IOOVDC
IOOVDC
CER
CER
28480
28480
.
CAPACITOR- FXD . O l U F + 8 0 - 2 0 %
CAPACITOR--FXD OIUF + 8 0 - 2 0 % IOOVDC CER 28480
.
CAPACITOR- FXD OIUF + 8 0 - 2 0 % 100VDC CER 28480
28480
.
CAPACITOR- FXD I P F +-.25PF SOOVDC CER
CAPACITOR- FXD OIUF + 8 0 - 2 0 % lOOVDC CER
CAPACITOR- FXD .O1UF +80-20% 10OVDC CFR
28480
28480
CAPACITOR- FXD . O I U F 4 0 - 2 0 % IOOVDC CER 28480
Mfr
Reference HP Part Description Mfr Part Number
Designation Number -
Code
TRANSISTOR NPN S I TO-18 PD-360HU 28480
TRANSISTOR PNP S I PD=300HU FT=lSOHHZ 28480
TRANSISTOR NPN 9 1 PD-300W FT=EOOHHZ 28480
TRANSISTOR NPN S I PD=SOOHU FT=200HHZ 28480
TRANSISTOR NPN 2N2219A S I TO-5 PD40OhU 01295
-
See introduction to this a t i o n for ordering inforination
*Indiutm CrctDry teloctd value
TABLE 812. LOG AMPLIFIER ASSEMBLY A14, REPLACEABLE PARTS (4 OF4) (SERIAL PREFIX 220814)
-
I Reference
Designation
HP Part
Number Description Mfr
-
Code Mfr Part Number
RESISTOR 3 1 6 1% ,125U F TC=O+--100 24546
RESISTOR 6 . 1 9 1 1% ,125U F TC-0+-100 19701
NOT ASSIGNED
RESISTOR 2 . 8 7 1 1% .125U F TC=O+-100 24546
RESI9TOR IOK 1% ,125U F TC=Ot-100 24546
NOT LSSICNED
RESISTOR 13.3K 1% .125U F TC=O+-100 19701
RESISTOR 5 1 1 1% .125W F TC=O+-100 24546
RESISTOR 10 1% .125U F TC=O+-100 24546
RESISTOR 3 1 6 1% .125U F TC=O+-100 24546
h 1 4 HISCELLANEOUS PART8
R2
@ LOGILIN-
-7v
~ l /
LOG GAIN
--
FIGURE 8-68. LOG AMPLIFIER ASSEMBLY A14, COMPONENT LOCATIONS (SERIAL PREFIX 2208A)
Pages 8-191 and 8-199/8-200: MOTHERBOARD ASSEMBLY A16
2236A & Below Replace F i g u r e 8-77 with new F i g u r e 8-77 (SERIAL PREFIX 2236A)
i n c l u d e d i n t h i s Manual Backdating supplement.
.. XAll r - 7
'J41
h - 4
'I-?
0
I XAlOPl I
DIODE
BIAS
SECTION Vlll
SERVICE
Dampen the cloth with the alcohol and water Do not use paper of any kind to clean
solution and scrub the edge connector contacts the edge connector contacts. Paper
vigorously, using a circular motion. Polish one or lint particles left on the edge con-
side of the board at a time until the contacts tact surface can cause intermittent
shine, keeping the cloth damp to dissolve con- electrical connections.
taminants and reduce static electricity.
Using a clean cloth, dry the contacts by wiping Do not touch contact or trace sur-
from their inside to outside edge. This prevents faces with bare hands. Always handle
particles from building up on the contact edges. the board by its edges.
MODEL 8559A SERVICE
Variable capacitor
Transistor, NPN
Slide, toggle, or rocker
switch
Pushbutton switch
Surface Acoustic Wave
Resonator (SAWR)
fP Relay
Crystal
Indicates a factory-select
component
-03 Speaker
Indicates a plug-in
connection
Pin Diode
-6 Indicates a soldered or
Breakdown (zener) diode
6- mechanical connection
Varactor Diode
6- Indicates a single pin of
P C board edge connector
%- Schottky diode
for measurement. No
terminal provided for test Q, Front-panel control
probe. \
Jumper wire
0 Oscillator
@- Mixer
Distinctive-Shape Symbols
ACTIVE PERIOD
ACTIVE PERIOD
ACTIVE PERIOD
Nominal power levels, voltages, and waveforms shown on schematic diagrams were measured using
the test setup shown below. Note that signal characteristics shown on schematic diagrams are pro-
vided as a troubleshooting aid only. They should not be used for making instrument adjustments.
- D l SPLAY
MA l NFRAME
1,
l NPUT
L
BLANK I NO
EXTENDER
CABLE
EQUIPMENT:
PROCEDURE:
Connect equipment as shown. Set signal generator for a 35 MHz, - 10 dBm output signal.
Center the Cal signal on the display and adjust for top graticule.
Using board extenders when necessary, check voltages and waveforms indicated on schematic
diagrams. Trigger oscilloscope on negative transition of AUX B PENLIFT/BLANKING signal
from rear of display mainframe.
To measure RF power levels, set RESOLUTION BW control to 3 MHz and FREQ SPAN/DIV
to 0 (zero span). The first LO is not swept in zero span, allowing signal levels to be checked with
a second spectrum analyzer (use adapter cables as necessary). DO NOT use a power meter
(harmonics and LO signals will contribute to give erroneous levels).
General Information
The HP 8559A is a wideband spectrum analyzer plug-in module for use with either the H P 180 series or H P
853A display mainframes. It tunes from 10 MHz to 21 GHz and displays frequency spans as wide as 9 GHz (in
bands 5 and 6) and as narrow as 100 kHz (in band 1). A zero span feature enables the analyzer to operate as a
tunable, fixed-frequency receiver. Resolution bandwidths of 3 MHz to 1 kHz are selectable in a 1-3-10 sequence.
CRT display calibration can be maintained by coupling the frequency span, resolution bandwidth, and video
filter to an automatic sweep time control. A five-LED numerical display allows direct readout of the display
center frequency or the tunable marker frequency.
The adjustable reference-level control is calibrated to allow direct readout of amplitudes ranging from - 111 to
+ 30 dBm. Continuous wave (CW) signals at or below the Reference Level, the top display graticule, are
automatically below the analyzer's gain compression specification. Dynamic range is greater than 70 dB.
The resolution bandwidth and frequency span controls can be locked together to function as a "zoom" control.
Signal identification, in spans from 100 kHz to 10 MHz per division, and an alternate IF are also available. This
latter feature eliminates problems caused by IF feedthrough (baseline lift) and allows measurement of all signals
within the frequency range of the analyzer.
The typical spectrum analyzer comprises three main sections (see Figure 8-3): the RF section, the IF section, and
the display section. Since it is a plug-in designed to work with a display mainframe, the H P 8559A houses only
the RF and IF sections. The display and power supply are contained in the mainframe.
RF Section
The H P 8559A RF section resembles a triple-conversion superheterodyne receiver; input signal frequencies are
converted three times before processing for display. Triple conversion makes possible wide frequency coverage
and permits filtering and amplification at more easily controlled frequencies.
RF Attenuator. The stepped RF Input Attenuator Assembly A3, at the input to the RF section, attenuates
the input in precise 10 dB steps from 0 to 70 dB. Precise and repeatable attenuation and gain in the signal path
are necessary to preserve amplitude calibration and direct reading of signal amplitudes on the CRT. RF attenua-
tor adjustment establishes the optimum signal level applied to the First Mixer Assembly A4.
First Mixer. Within the First Mixer Assembly A6, the incoming signal mixes with the first local oscillator,
generating the first IE The first converter consists of a single microwave diode, a 4.8 GHz Low-Pass Filter
Assembly FLl contained in a short RF cable, and - housed in the Second Converter Assembly A5 - a 3 GHz
bandpass filter with a 17 to 23 MHz bandwidth.
First LO. A YIG-Tuned Oscillator Assembly A6, or YTO, is used as the first LO. YIG, yttrium-iron-garnet,
is a ferro-magnetic material which is polished into a small sphere and precisely oriented in a magnetic field.
Changes in this magnetic field alter the frequency generated by the YTO. For the YTO in the H P 8559A, a
frequency range of 3.01 GHz to 6.04 GHz is used. Voltage control of the magnetic fieId surrounding the YIG
sphere allows the analyzer to be swept or tuned within these frequency limits. A control voltage, derived from
the sweep generator, tunes the YTO in sync with the horizontal deflection of the CRT beam. A tuning voltage
offsets the sweep to establish the center frequency. Voltage control of the analyzer's frequency is convenient,
since low frequency circuits, like operational amplifiers and transistors, can generate and modify the control
voltage.
Second Converter. The Second Converter Assembly A5 houses the 3 GHz bandpass filter, the second mixer,
and the second LO. The 3 GHz filter uses the resonant characteristics of three precisely machined cavities, or
8-9
SERVICE MODEL 8559A
holes, in the aluminum block housing to filter the first IF. A fourth cavity is used as the resonant circuit for the
second LO, which operates at one of two fixed frequencies. After mixing with the first IF, the second LO
produces the second IF at 321.4 MHz.
The need for operating the second LO at two separate frequencies becomes apparent when measuring a signal at
or near the first IF frequency, 3 GHz. The signal passes through the first mixer and first IF unaffected by first
LO tuning and appears as an equally strong signal at all frequencies. This response is called IF feedthrough or
baseline lift. Changing the frequency of the second LO shifts the feedthrough response away from the fre-
quency being measured by effectively altering the first IE Two LO frequencies may be selected with the ALT IF
control, 2.6861 GHz (regular IF) and 2.6711 GHz (alternate IF). The LO shift (15 MHz) is reflected in the first
IF and fits within the 17 MHz to 23 MHz 1 dB passband of the 3 GHz bandpass filter.
Third Converter. The Third Converter Assembly A10 contains the second IF amplifier, the second IF band-
pass filters, the third mixer, the third LO, and the third IF filters and compensation amplifiers. The second IF
amplifier consists of a single-transistor amplifier with a 321.4 MHz bandpass filter at its input. It provides
about 15 dB of gain before passing the signal to a second 321.4 MHz bandpass filter at its output. The net 1 dB
bandwidth is 6 MHz to 9 MHz, narrow enough to reject the second mixer's image frequency. The double-
balanced third mixer produces sum and difference frequencies, as do other mixers, but rejects input and LO
frequencies, simplifying subsequent filtering. Two transistors form the third LO, fixed at 300 MHz, which,
when mixed with the 321.4 MHz second IF, produces a difference frequency at the final IF, 21.4 MHz.
Three conversions or frequency translations are necessary before the input signal reaches the final IF, where the
analyzer's major bandpass filtering and calibrated gains occur. The circuits used in the final IF are more easily
controlled at 21.4 MHz than they would be at the higher input frequencies. The RF section's function is to
down-convert the input signal accurately so the analyzer can control and display it.
Harmonic Mixing. To extend the frequency range of the H P 8559A, harmonic mixing is employed. Instead
of limiting the first mixer input to the fundamental range of the first LO (3.01 GHz to 6.04 GHz), harmonics of
the LO are allowed to mix with the incoming signal. Each of the six FREQUENCY BAND GHz buttons on the
front panel selects a different mixing mode. A mixing mode is characterized by the number of the LO harmonic
used and the relationship of the incoming signal frequency to the LO frequency. For example, in the first band
(.01 to 3 GHz) the incoming signal is below the frequency of the LO. If the incoming signal is 2 GHz, the LO
must tune to 5 GHz to produce a difference frequency at the required IF, 3 GHz. This band is characterized as
the "1 - " mixing mode. This relationship is expressed by the fundamental mixing equation:
Band two (6 to 9 GHz) uses the "1 + " mixing mode. In this band, the incoming signal frequency is higher than
the first LO frequency. Now an 8 GHz incoming signal mixes with the 5 GHz first LO, producing an IF
response at 3 GHz. The mixing equation also reflects this change by becoming:
Higher frequency bands are realized by using the second harmonic (6 to 12 GHz) or the third harmonic (9 to 18
GHz) of the first LO. Adjusting the dc bias of the first mixer diode enhances operation at these frequencies. As
with the fundamental mixing mode, each harmonic mode has two possible frequency bands creating a total of
six bands: 1+ , 1- , 2 + , 2 - , 3 + , and 3 - . Section 3, Figure 17 shows the tuning curves for the six mixing
modes and the LO fundamental. The mixing equations for the harmonic mixing modes are:
and
Regardless of which harmonic is used for mixing, image frequencies can create problems. Image frequencies
occur when a signal not in the band being viewed mixes with the LO to produce a response. It is possible to be in
the 1 - band and have a signal at 5 GHz produce a response at 2 GHz; the opposite can occur in the 1 + band.
As can be seen, it is necessary to be able to differentiate these signals. In the H P 8559A, this is the function of
the signal identifier.
Signal Identifier. Several methods of eliminating image responses are used in spectrum analyzers: low-pass
filters, preselectors, and signal identifiers. Low-pass filters eliminate all upper out-of-band frequencies from the
mixer; this works well for single band analyzers. A preselector (a YIG-tuned bandpass filter) tracks the LO
frequency; this allows multi-band operation, but can degrade input sensitivity. The signal identifier allows
identification of in-band signals without losses in sensitivity. This is the scheme used in the H P 8559A.
Signal identification simultaneously shifts the display frequency down 1 MHz and decreases the display ampli-
tude about 5 dB. If the signal is an image, it will do something other than shift down 1 MHz. The SIG IDENT
button on the front panel activates this function by simultaneously shifting the frequency of the second LO and
varying the level of the video signal during alternate sweeps.
IF Section
The IF section comprises the third IF filters and amplifiers, and the step gain and logarithmic amplifiers. It also
includes the video detector, video filters, and video amplifiers. The IF section processes the 21.4 MHz output of
the Third Converter Assembly A10 and applies it to the vertical deflection circuitry in the display mainframe.
The 21.4 MHz third converter output is processed by the Bandwidth Filter No. 1 Assembly A1 1, the Step Gain
Assembly A12, the Bandwidth Filter No. 2 Assembly A13, and, finally, the Log Amplifier Assembly A14. Each
assembly occupies a separate printed circuit board, which is shielded by extrusions mounted on the Mother-
board Assembly A16.
Bandwidth Filters. Bandwidth Filter No. 1 Assembly A1 1 and Bandwidth Filter No. 2 Assembly A13 are
identical; each contains two synchronously-tuned filter poles isolated by buffer amplifiers. Synchronously-
tuned filter poles have identical center frequencies, unlike stagger-tuned poles. The bandwidth of these poles,
varying from 3 MHz to 1 kHz, is changed simultaneously by the front panel RESOLUTION BW control.
Because the variable bandwidths are so much narrower than any of the RF section bandpass filters, the RESO-
LUTION BW control setting determines the analyzer's overall bandwidth. Parallel LC filters provide band-
widths from 3 MHz to 100 kHz. Crystal filters provide the narrow, 30 kHz to 1 kHz, bandwidths.
Step Gain Amplifier. Located between the bandwidth filter assemblies, the Step Gain Assembly A12 pro-
vides precise and selectable gain in three stages, a 10 dB stage followed by two 20 dB stages. Each stage can be
turned "on" for full gain or "off" for unity gain. By turning on the amplifiers in combination, gains of 0 to 50
dB may be selected. This action is performed by the REFERENCE LEVEL control. Concentric with the
REFERENCE LEVEL knob is the REF LEVEL FINE potentiometer, which controls the 0 to 12 dB PIN diode
attenuator. In addition to the gain circuits described, circuitry providing biasing to the first mixer diode and
flatness compensation to the third converter is included on the Step Gain Assembly A12.
Logarithmic Amplifier. The second bandwidth filter is followed by the Log Amplifier Assembly A14. The
gain of this amplifier is a logarithmic function of the input signal, which allows a greater range of signal
amp!itudes to be simultaneously displayed on the CRT. This logarithmic amplification of the signal before
detection results in the vertical display axis being calibrated in decibels (relative to a milliwatt), rather than volts.
Linear amplification from 0 dB to 40 dB may also be selected from the front panel.
The video detector, located on the Log Amplifier Assembly A14, is basically a half-wave rectifier and a filter.
This circuit produces a voltage proportional to the signal level, called the video signal. This signal passes
through a video filter and a vertical deflection amplifier before leaving the H P 8559A.
MODEL 8559A
TROUBLESHOOTING HINTS
Begin troubleshooting by measuring the mainframe-supplied voltages as close to the H P 8559A as possible. The
Vertical Driver/Blanking Assembly A15 offers three test points (A15TP6, A15TP7, A15TP8) to make the
measurements. The + l00V supply is available at A15TP6, the + 15V supply at A15TP7, and the - 12.6V
supply at A15TP8. If any of these voltages are low, refer to the mainframe Operation and Service manual and
make the necessary adjustments before continuing. Common symptoms caused by low mainframe-supplied
voltages include: increased residual FM (caused by a low + 15V supply) and poor frequency accuracy or inter-
mittent lockup of the frequency display LED'S (also caused by a low power supply).
Residual FM
Residual FM is a short-term jitter or an undesired frequency modulation of a local oscillator (LO). It appears as
noise riding on the displayed trace and may be random or cyclical (usually as a function of the line frequency).
The following procedure is a guide for isolating a source of residual FM. Further troubleshooting hints concern-
ing residual FM are included following the circuit descriptions of the indicated assemblies.
Verify that the mainframe supply voltages are correct at the Vertical Driver/Blanking Assembly A15 of the
H P 8559A by checking the voltages at A15TP6, A15TP7, and A15TP8.
Use a second spectrum analyzer to check each LO of the H P 8559A for FM.
First LO: check at the H P 86559A front-panel RF input jack with test analyzer tuned to about 3 GHz
(LO power is - 8 dBm + 3 dBm).
Second LO: check at A5J3 on Second Converter Assembly AS.
Third LO: check at AlOJ1, the 300 MHz output on Third Converter Assembly A10.
If the source of FM is the first LO, check the Frequency Control Assembly A7 and the YIG-Tuned
Oscillator Assembly A6.
If the source of the FM is the second LO, short A5A2TPl to ground while observing the second LO with
the second spectrum analyzer. This isolates the possible source of FM to the Second Converter Assembly
A5 by removing the varactor bias voltage. Note that removing this bias voltage will cause the second LO
frequency to shift. If FM is still present, check the Second Converter Assembly A5 as the source. If the FM
disappears, check the bias voltage source on the Marker Board Assembly A8.
If the source of the FM is the third LO, check the Third Converter Assembly AlO.
MODEL 8559A SERVICE
DPM Accuracy
The following is a guide to troubleshooting poor DPM accuracy. Further information is included following the
circuit descriptions of the indicated assemblies.
The Digital Panel Meter (DPM) Assembly AlAl/AlA2 is a dc voltmeter that measures a tuning voltage from
Marker Assembly A8, and converts it to a front-panel frequency readout. The DPM electronics are contained
on two assemblies: the DPM Display Assembly A l A l and the DPM Driver Assembly A I M .
The DPM Display Assembly comprises five seven-segment displays with Darlington-transistor switches, Q l
through Q5. The seven-segment displays (DSl through DS5) are the common-cathode type. The cathode of a
display is pulled negative (to about - 10.5V) when the Darlington-transistor switch associated with it is turned
on. With the cathode at a negative potential, the output of AlA2U4 can light the display segments. The
transistor switches are strobed so the displays light sequentially. The refresh rate is determined by the clock
(block C) and is fast enough (about 300 Hz) that the displays appear to be lit simultaneously.
Contained on the DPM Driver Assembly AlA2 are the analog-to-digital converter, power supplies, and display
interface circuits. Analog processor IC (U2) and digital processor IC (U3) are each one-half of an analog-to-
digital converter (ADC). Analog comparator circuits in U2 control counter logic in U3. To accomplish the
analog-to-digital conversion, U2 and U3 interact on three control lines: the M/Z (measure/zero logic) line, the
COMP (comparator) line, and the U/D (up/down) line. The ADC, U3, produces two outputs. The first com-
prises five sequential four-line BCD outputs that are fed to BCD-to-seven-segment converter U4. The second
consists of five sequential digit strobes that are fed to Darlington-transistor switches AlAlQl through AlAIQ5
on the DPM Display Assembly A1A1.
The input signal applied across connector pins 51-3 and 51-6 of the DPM Driver Assembly A1A2 is a dc level of
OV to -4V, representing an instrument tuning-range of 0 to 20 GHz (a 1V change of the input level represents a
tune frequency change of 5 GHz). This OV to - 4V input signal is divided by precision resistors R33 and R27,
providing a OV to - 2 . 0 V signal across pins 2 and 15 of the analog processor IC, U2.
Transistors Q1, 42, and Q9 interface the "sign/or/urV (sigdover-rangehnder-range) output of U3 with seg-
ment "g" of numeric display AlAlDS5. Transistor 4 2 and CR2 provides a "wired AND" function so that the
minus sign is shown only in the most-significant-digit position (when both "D5" and "sign/or/ur" are high).
Transistor Q1 serves to shift the signal level and Q9 supplies drive to the segment when a minus sign is displayed.
Field-effect transistor Q8 and its associated circuitry form a Colpitts oscillator that provides a clock of about
225 kHz. Inductor L1 and the series combination of C1 and C2 determine the nominal clock frequency.
The power supply circuitry provides the necessary voltage reduction, protection, and filtering for the dc supply
voltages: + 12V, - 12.6V, and + 5V. The supply voltages are filtered as they enter the board to reduce interfer-
ence between the DPM and the rest of the instrument. The + 15V supply is used to derive the + 12V supply and
the + 5V supply. Zener diode VRl is used to reduce the + 15V supply to + 12V, while regulator U8 reduces the
+ 15V supply to + 5V. The - 12.6V supply is filtered to offer two supply lines: - 12.6VF, and - 12.6VF2.
Operational amplifier U7 and its associated circuitry provide a constant dc voltage reference of approximately
+ 6.2V to the analog IC, U2.
SERVICE MODEL 8559A
During the period the DPM drive input is being converted, the BCD output circuitry in U3 is shut off. Once the
conversion in U2 and U3 is complete, the four-line BCD is sent to U4 where it is converted to a seven-line
(segment) drive. This seven-line output from U4 is fed in parallel to the displays on the Display Assembly A1A1.
Coincident with the BCD-to-seven-segment conversion, U3 supplies a digit strobe drive that, by turning on one
of the DPM Display Assembly A1A1 transistors (AlAlQl- A1AlQS), activates one of the seven-segment
displays.
Multiplexed BCD data from the digital processor IC (U3) are level shifted by transistors 43, 4 4 , Q5, and 4 6
and decoded by the BCD-to-seven-segment decoder-driver IC, U4. The decoder-driver sinks the current that
drives the paralleled LED display segments on the DPM Display Assembly AlAl. The digit strobe outputs from
U3 are level shifted by 4 7 , A1 1, A12, 413, and 414 and subsequently drive the Darlington-transistor switches
A1AlQl through A1Al Q5 on the DPM Display Assembly A1A 1.
Display digits freeze intermittently: Be sure the clock oscillator signal goes at least -7V negative and
appears as in Figure 8-4. Low gain (Gm) of AlA2Q8 is the most probable cause for failure. Resistor AlA2Rl is
factory selectable; increasing its value increases the amplitude of the clock output,
Least Significant Digit (LSD) dithers: AlA2U2 is the most probable cause; however, noise from
AlA2R24, AlA2R25, or AlA2C5 also causes this symptom.
The same segment in each digit does not light: AlA2U4 failure.
CONNFCTOR PC EDCC 1 0 - C O N T I R O W 2 R W . ;
A1A2
DPM DRIVER ASSEMBLY
DPM INPUT
SIGNAL
(This test point is located
on the trace side of the
circuit board.)
A1 A1
DPM DISPLAY ASSEMBLY
Functions of the switches and potentiometers on the Front Switch Assembly A2 are covered in the circuit
descriptions for the electronic assemblies they control.
SERVICE MODEL 8559A
NOTE
Use a 9/16-inch nut driver (drilled out, if necessary, to fit over front panel BNC connectors, and covered
with heatshrink tubing or tape to avoid scratching enameled front panel) to remove dress nut holding CAL
OUTPUT connector to front panel.
Remove bottom guide rail. Use a 5/16-inch open-end wrench to carefully disconnect semi-rigid CabIe W2
from Input Attenuator Assembly A3 to First Mixer Assembly A4.
Disconnect two 40-conductor Ribbon Cables, A2AlWl (46) and A2AlW2 (47) from Motherboard
Assembly A16.
Remove screw holding cable clamp to Second Converter Filter Assembly A5A2. Remove screw located
below cable clamp that was removed.
Remove the four screws attaching Front Switch Diecast (1) to left and right side gussets. Remove Front
Switch Assembly A2, with Front Panel and RF Input Attenuator Assembly A3, from H P 8559A chassis
and set chassis to one side.
Remove the following front panel knobs: FINE TUNE, COARSE TUNE, RESOLUTION BW, FREQ
SPAN/DIV, REF LEVEL FINE, and REFERENCE LEVEL (including Index Disc, Retaining Cup,
Nylon Spacer Washer(s), Conical Spring, and Input Attenuator pointer).
Remove SWEEP TRIGGER, MANUAL SWEEP, and SWEEP TIME/DIV knobs using a no. 4 hex
wrench.
Use a no. 4 hex wrench to loosen the two set screws in Lock Knob. Remove Lock Knob.
Remove VIDEO FILTER and BASELINE CLIPPER knobs using a no. 2 spline (Bristol) wrench.
Remove retaining ring on coarse tune shaft. Remove the three flat washers and two wavy washers.
Remove front panel hex nut and lockwasher on Coarse Tune Bushing (36) using a 1/2-inch nut driver
(covered with heatshrink tubing or tape to avoid scratching enameled front panel).
Loosen hex nut attaching RF Input Cable Assembly W1 to Front Switch Assembly A2 using a 5/8-inch
open-end wrench. Carefully disconnect input cable assembly from RF Input Attenuator Assembly A3
using a 5/16-inch open-end wrench. Remove input cable assembly from Front Switch Assembly A2.
MODEL 8559A SERVICE
14. Disconnect 10-conductor ribbon cable connected to DPM Driver Assembly AlA2. Remove screw holding
DPM Display Assembly AlAl to diecast. DPM window will fall out.
15. Use a 5/16-inch nut driver to remove the two nuts attaching front panel to Front Switch Diecast (1).
Remove front panel from Front Switch Diecast.
16. Place Front Switch Assembly A2 on flat working surface with remaining knobs face-down and lock
mechanism facing you. Prop sides of switch assembly to allow knobs and shafts to clear working surface
(be careful not to scratch front panel enamel).
17. Remove screw and washer attaching Attenuator Bracket (49) to Front Switch Diecast (1). Remove RF
Input Attenuator Assembly A3 from Front Switch Assembly A2.
Cut tiewrap holding REF LEVEL FINE wires to rear switch board.
Remove the three screws (48) attaching Ref Level Fine Pot Plate (68) to Standoffs (62).
Remove Index Disc Locator and Ref Level Fine assembly (30, 31, and 64 through 69) from Front
Switch Assembly A2 (set to one side, without detaching wires).
Remove three standoffs (62) used to support Ref Level Fine Pot Plate (68). Use a no. 6 hex wrench to
loosen the two set screws on Miter Gear (51) attached to Attenuator Shaft Assembly (18); then
remove Miter Gear from shaft.
Use a no. 4 hex wrench to loosen Rotating Lockout (63) attached to Ref Level Shaft (6), and remove
lockout from shaft. Remove Ref Level Detent (61) from Front Switch Assembly A2. Be careful to
keep Ball Bearing (10) and Spring (1 1) with Ref Level Rotor (60).
Remove the three Studs (53) used to support Ref Level Detent (61).
Use a no. 4 hex wrench to loosen the two set screws on front Anticrush Drive Hub Assembly (7)
(between Front Switch Board M A 1 and Front Switch Diecast (1) on Ref Level Shaft (6); accessible
from side of Front Switch Assembly). Remove Ref Level Rotor (60) and Ref Level Shaft (6) with rear
Anticrush Drive Hub Assembly (7) still attached.
NOTE
Rear Anticrush Drive Hub Assembly (7) on Ref Level Shaft (6) is preset at
9.525 mm (0.3 in.) from end of shaft (see Figure 8-7A). Do not remove drive
hub unless necessary for repair.
b. Use a 1/4-inch Nut Driver to remove two Hex Nuts (20) attaching Bandwith Switch Board (59) to
Front Switch Assembly, and set board to one side (without detaching wires).
c. Remove Bandwidth Rotor (56). Be careful to keep Ball Bearings (10) and Springs (23) with rotor.
d. Remove Bandwidth Shaft (55), with rear Drive Hub (15) still attached, from Front Switch Assembly.
827
SERVICE MODEL 8559A
NOTE
Rear Drive Hub (15) on Bandwidth Shaft (55) is preset flush with collar on
shaft (see Figure 8-7B). Do not remove drive hub unless necessary for repair.
e. Use a no. 4 hex wrench to loosen the two screws on Coupling Hub (54) attached to Frequency Span
Shaft (9), and remove hub from shaft.
f. Remove the two Studs (53) used to support Bandwidth Switch Board (59). Remove Bandwidth
Detent (52) from Front Switch Assembly.
20. Remove the remaining Screws (48) attaching Front Switch Board Assembly M A 1 to Front Switch Diecast
(1).
21. Twist the left side of Front Switch Board Assembly M A 1 down approximately l/&inch to provide clear-
ance from Front Switch Diecast support arm (upper left corner). Lift Front Switch Board Assembly A2A1
from Front Switch Diecast (1) and set aside.
a. Remove Attenuator Drive Rotor (8), front Anticrush Drive Hub Assembly (7), and Attenuator Shaft
Assembly (18) from Front Switch Diecast (I), and set these parts aside.
b. Remove Frequency Span Rotor (14) with associated parts (9 - 12, 15 - 17) from Front Switch Diecast
(I), and set aside. Be careful to keep Ball Bearings (10) and Springs (11) with Frequency Span Rotor
(14).
NOTE
Drive Hub (15) on Frequency Span Shaft (9) is preset at 12.954 mm (0.510 in.)
from end of shaft (see Figure 8-7C). Do not remove drive hub from shaft
unless necessary for repair.
c. Remove both remaining rotor assemblies from Front Switch Diecast (I), and set aside. Be careful to
keep Ball Bearings (10) and Springs (11) with their respective rotors.
a. Press Locking Link (5) into Front Switch Diecast (I) to release pressure on Dowel Pin (4). Remove
Dowel Pin through cutout in Front Switch Diecast. (Individual parts are identified in Figure 8-9.)
b. Remove Locking Link ( 9 , Locking Shaft (3), and Lock Spring (2) from Front Switch Diecast.
1. All switch contacts must be totally clean and grease-free for proper operation. Use a 50-50 mixture of
isopropyl alcohol and distilled water to thoroughly clean switch rotor contacts and Front Switch Board
Assembly A2A1. Avoid touching contacts with fingers.
2. Inspect for bent or damaged shafts, worn or broken contacts, weak or broken springs, rough feeling
potentiometers, cracked castings, and damaged PC boards. Check for signs of corrosion or rust. Replace
any suspect parts.
3. A special Instrument Grease (HP Part Number 6040-0584) is recommended exclusively for use during
switch reassembly. Lubrication is essential for proper operation of switches and lock. A small brush is
recommended for applying the Instrument Grease.
8-28
MODEL 8559A SERVICE
1. Assembly of Lock:
a. Lightly grease Locking Shaft (3) and insert into Front Switch Diecast (1). Lightly grease bearing
surfaces of Locking Link (5).
b. Insert Lock Spring (2) into Front Switch Diecast (1). Press Locking Link (5) fully into Front Switch
Diecast and insert Dowel Pin (4) through access cutout (left side of lock boss) to hold lock mecha-
nism in place. Check for correct lock operation.
a. Lightly grease all switch rotor detent holes on back of Front Switch Diecast (1).
b. Place Front Switch Assembly on flat working surface with front panel face-down and lock mecha-
nism facing you. Prop sides of switch assembly to provide clearance for knobs and shafts during
assembly (be careful not to scratch front panel enamel).
c. Inspect SWEEP TRIGGER rotor assembly (10 - 12, 24- 27). Stop Arm (26) and Horseshoe Spring
(27) are held in position by Push-on Retainer (25) and should move smoothly without binding (see
Figure 8-8A). Roll Pins (12) should be positioned in hole 7 and hole 18 on SWEEP TRIGGER Rotor
(24). Check that Spring (1 1) and Ball Bearing (10) are in position.
d. Lightly grease long side of SWEEP TRIGGER Shaft (24) and insert SWEEP TRIGGER rotor
assembly into left-most bushing in Front Switch Diecast (1). Position rotor so that Ball Bearing (10)
aligns with stop boss on left side of Front Switch Diecast.
e. Inspect SWEEP TIME/DIV rotor assembly (10, 11, 21, 22, 24), Figure 8-8B. MANUAL SWEEP
Shaft (22) should be lightly greased and should turn freely inside SWEEP TIME/DIV Shaft (24).
Check that Spring (1 1) and Ball Bearing (10) are in position. Note that there are no roll pins inserted
in the SWEEP TIME/DIV Rotor (24).
f. Lightly grease long side of SWEEP TIME/DIV Shaft (24) and insert SWEEP TIME/DIV rotor
assembly into next bushing in Front Switch Diecast (1).
g. Inspect FREQ SPAN/DIV rotor assembly (9 - 12, 14- 17). If Drive Hub (15) has been loosened or
removed from Frequency Span Shaft (9), refer to Figure 8-8C for correct dimensions for adjustment.
Roll Pins (12) should be positioned in hole 15 and hole 17 on Frequency Span Rotor (14), as shown in
Figure 8-8C. Slotted Bushing (16), Hairpin Spring (17), and Frequency Span Shaft must be lightly
greased where they contact each other for proper operation of push-pull mechanism. Check that
Springs (1 I), Ball Bearings (lo), Slotted Bushing, and Hairpin Spring are in correct position.
h. Lightly grease long side of Frequency Span Shaft (9) and insert FREQ SPAN/DIV rotor assembly
(9- 12, 14 - 17) into next bushing in Front Switch Diecast (1). Position FREQ SPAN/DIV rotor
assembly so that stop boss on Front Switch Diecast does not fall within small span between Roll Pins
(12).
SERVICE MODEL 8559A
i. Inspect Attenuator Drive Rotor (8). Roll Pins (12) should be positioned in hole 1 and hole 9, as
shown in Figure 8-8D.
j. Inspect front Anticrush Drive Hub Assembly (7). Note that pin is offset to one side of drive hub;
place drive hub over right-most bushing in Front Switch Diecast (I) with this side down (i.e., pin as
close as possible to Front Switch Diecast) for proper switch operation.
NOTE
Correct side of front Anticrush Drive Hub (7) must be oriented towards Front
Switch Diecast (1) for proper operation of Front Switch Assembly.
k. Set Attenuator Drive Rotor (8) over Anticrush Drive Hub (7) with Attenuator Drive Rotor gear
facing up. Long pin on Attenuator Drive Rotor should protrude through curved slot in diecast.
1. Lightly grease gear end of Attenuator Shaft Assembly (18) and insert into Front Switch Diecast (1).
Place metal Washer (19) on shaft.
m. Clean contact fingers on all rotors using lint-free cloth and isopropyl alcohol/distilled water mixture.
All rotors should be in proper position.
Inspect Front Switch Board Assembly. Check switch traces for dirt, grease, or wear. Check intercon-
nect wires, solder joints, pushbutton switches, and ribbon cables (46,47).
Clean switch traces using lint-free cloth and isopropyl alcohol/distilled water mixture. No residue
should be visible on traces.
Use a 3/8-inch open-end wrench to tighten Hex Nut (31) and Lockwasher (30) attaching VIDEO
FILTER Potentiometer (33) and metal Washer (32) to Front Switch Board Assembly.
Use a 1/2-inch open-end wrench to tighten inner Hex Nut (28) and Washer (29) attaching Dual Tune
Pot assembly (21,28,29, 34 - 42,44) to Front Switch Board Assembly. Note that Roll Pin (12) aligns
with hole in switch board to locate Dual Pot Bracket (39); Washer (29) between bracket and switch
board is critical to proper switch operation.
Check Dual Tune Pot assembly for smooth operation and proper gear meshing; disassemble and
lightly grease shafts if necessary. Install second Hex Nut (28) mid-way onto Coarse Tune Shaft Bush-
ing (36).
Set Front Switch Board Assembly into place on partially-assembled Front Switch Assembly and use a
Stud (53) on right-most side of switch assembly to loosely fasten switch board to Front Switch
Diecast (1).
With one Stud (53) in place but not tight, twist left side of Front Switch Board Assembly up approxi-
mately 1/8-inch to fasten switch board under Front Switch Diecast support arm (upper left corner)
and align switch shafts.
Loosely install the remaining Screws (48) used to fasten Front Switch Board Assembly to Front
Switch Diecast (1).
Do not overtighten screws and studs into Front Switch Diecast (1).
MODEL 8559A SERVICE
i. Use a no. 4 hex wrench to temporarily install SWEEP TRIGGER, SWEEP TIME/DIV, MANUAL
SWEEP, and FREQ SPAN/DIV knobs.
j. Tighten Stud (53) and left-most Screw (48) attaching Front Switch Board Assembly to Front Switch
Diecast (1). Check all switch rotors for smooth, free switch action. Readjust position of Front Switch
Board Assembly as necessary for proper switch action.
k. Tighten the two remaining Screws (48) attaching Front Switch Board Assembly to Front Switch
Diecast (1).
1. Recheck all switch rotors for smooth, free switch action and readjust Front Switch Assembly as
necessary.
a. Place Coupler Hub (54) on Frequency Span Shaft (9) with pin facing up (away from Front Switch
Assembly). Do not tighten Coupler Hub at this time.
b. Center Bandwidth Detent (52) over Coupler Hub (54) with stop tab towards top of Front Switch
Assembly, and fasten to Front Switch Assembly using two Studs (53).
c. If Drive Hub (15) has been removed or loosened from Bandwidth Shaft (55), refer to Figure 8-7B for
proper adjustment. Lightly grease narrow end of Bandwidth Shaft (55) and detent holes on Band-
width Detent (52). Insert Bandwidth Shaft (55) through Frequency Span Shaft (9).
d. Inspect RESOLUTION BW Rotor (56). Roll Pins (12) should be positioned in hole 16 and hole 17 as
shown in Figure 8-8E. Check that Springs (23) and Ball Bearings (10) are in position.
e. Place RESOLUTION BW Rotor (56) onto Bandwidth Shaft (55). Position RESOLUTION BW
Rotor assembly so that stop tab does not fall within small span between Roll Pins (12).
f. Clean contact fingers on RESOLUTION BW Rotor and switch traces on Bandwidth Switch Board
(59) using lint-free cloth and isopropyl alcohol/distilled water mixture.
g. Use a 1/4-inch nut driver to fasten Bandwidth Switch Board (59) to Front Switch Assembly with two
Hex Nuts (20). End of Bandwidth Shaft (55) must not bind against hole in board. Align MANUAL
SWEEP Shaft (22) with MANUAL SWEEP Potentiometer (58) by turning MANUAL SWEEP
knob clockwise until shaft engages with MANUAL SWEEP Potentiometer.
NOTE
h. Turn Front Switch Assembly over and remove FREQ SPAN/DIV knob using a no. 4 hex wrench.
j. Use a no. 6 hex wrench and a no.4 hex wrench to temporarily install FREQ SPAWDIV and RESO-
LUTION BW knobs.
831
SERVICE MODEL 8559A
k. Pull and turn FREQ SPAN/DIV Knob until a set screw is visible on Coupling Hub (54). Push FREQ
SPAN/DIV knob in and out to align pin on Coupling Hub with slots in Bandwidth Rotor (56). With
FREQ SPAN/DIV knob pushed in and Coupling Hub flush again Bandwidth Rotor (pin aligned),
tighten set screw using a no. 4 hex wrench. Turn FREQ SPAN/DIV knob until second set screw is
visible, and tighten second set screw.
1. Push FREQ SPAN/DIV knob in and out while observing Bandwidth Rotor (56). Bandwidth Rotor
will not move if Coupling Hub (54) is properly aligned. Readjust Coupling Hub as necessary for
proper operation.
a. Install remaining two Studs (53) on Front Switch Assembly. Check that all screws and studs have
been tightened.
b. If rear Anticrush Drive Hub Assembly (7) has been loosened or removed from Ref Level Shaft (6),
refer to Figure 8-7A for correct dimensions for adjustment.
c. Inspect Ref Level Rotor (60). Roll Pins (12) should be positioned in hole 1 and hole 9, as shown in
Figure 8-8E Check that Spring (11) and Ball Bearing (10) are in position. Insert Ref Level Shaft (6)
through Ref Level Rotor so that rear Anticrush Drive Hub (7) seats properly into rotor.
d. Lightly grease long end of Ref Level Shaft (6) and insert through Front Switch Board Assembly
A2A1, Attenuator Drive Rotor (8), front Anticrush Drive Hub (7), and bushing in Front Switch
Diecast (1).
\
e. Lightly grease detent holes on flat side of Ref Level Detent (61). Mount detent on three Studs (53)
and fasten tightly with three Standoffs (62).
Hollow Ref Level Shaft (6) might be damaged if set screws in Rotating Lock-
out (63) are tightened excessively.
f. Place Rotating Lockout (63) on Ref Level Shaft (6) with teeth flat against Ref Level Detent (61).
Lockout teeth should be aligned to miss pin on Ref Level Detent when Ref Level Shaft is pushed in
(switch in any detent position). With Ref Level Shaft fully extended from front panel, use a no. 4 hex
wrench to tighten Rotating Lockout.
g. Push Ref Level Shaft (6) in and out and check for smooth mechanical feel and proper Rotating
Lockout (63) alignment. Rotating Lockout should not bind against Ref Level Detent (61) and should
allow Ref Level Shaft to turn smoothly between detent positions. Adjust Rotating Lockout as neces-
sary for proper operation.
h. Use a no. 4 hex wrench to lightly tighten one set screw in front Anticrush Drive Hub (7) visible
between Attenuator Drive Rotor (8) and Front Switch Diecast (1).
i. Turn Attenuator Drive Rotor (8) so that long pin (for input Attenuator pointer) is at bottom of Front
Switch Diecast (1). Hold Attenuator Drive Rotor in position and push in on Ref Level Shaft (6) to
align front Anticrush Drive Hub (7).
j. Push Ref Level Shaft (6) in and out while observing Ref Level Rotor (60) and Attenuator Drive Rotor
(8). Rotors will not move when front Anticrush Drive Hub (7) is properly adjusted.
MODEL 8559A SERVICE
k. Use a no. 4 hex wrench to firmly tighten both set screws in front Anticrush Drive Hub (7). Recheck
Ref Level Shaft (6) as in step j, and readjust front Anticrush Drive Hub as necessary.
1. Slip Miter Gear (51) over Attenuator Shaft Assembly (18). Do not tighten at this time.
m. Inspect Ref Level Fine Assembly (30, 31, 65 - 69). Ref Level Fine Shaft (65) should turn smoothly.
Check Ref Level Fine Potentiometer (69) and connecting wires for good electrical connections.
Lightly grease Ref Level Fine Shaft and hollow Index Disc Locator (64) shaft.
n. Install Index Disc Locator (64) on Front Switch Assembly. Hole in locator bar rides over left-most
Standoff (62) used to support Ref Level Fine Pot Plate (68). Install Ref Level Fine Assembly (30, 31,
65 - 69) on Front Switch Assembly with three Screws (48). Connecting wires should be routed. Ref
Level Fine Shaft (65) should turn smoothly without binding over its full rotation. Adjust position of
Ref Level Fine Pot Plate as necessary.
o. Use a new tiewrap to attach Ref Level Fine connecting wires to Standoff (62).
a. Mount RF Input Attenuator to Attenuator Bracket (49) using two Screws (48). Check all eight
attenuator positions by hand for proper detent action and smooth operation. Leave attenuator in full
counter-clockwise position.
b. Slide Miter Gear (51) to end of Attenuator Shaft Assembly (18) against Ref Level Fine Pot Plate (68).
Set Attenuator Assembly in place on Front Switch Assembly, with notch in Attenuator Bracket (49)
lightly greased and aligned with Attenuator Shaft Assembly. Use Washer (50) and Screw (45) to fasten
Attenuator Bracket to lower left corner of Front Switch Diecast (1). (Do not tighten Miter Gear at
this time.)
Use a 5/16-inch nut driver and two hex nuts to carefully install front panel (with pushbutton bezels
and DPM window installed) on Front Switch Diecast (1).
Insert RF Input Cable Assembly W1 through front panel and loosely attach with hex nut. Carefully
connect cable assembly to RF Input Attenuator using a 5/16-inch open-end wrench. Tighten cable
assembly to front panel using a 5/8-inch open-end wrench.
Use a no. 4 hex (Allen) wrench to install lock Knob on Locking Shaft (3). Base of Lock Knob should
clear front panel when Locking Shaft is pushed in.
Install front panel nut and washer on Coarse Tune Bushing and tighten with special 1/2-inch nut
driver.
NOTE
Front-panel control knobs and their attaching parts are identified in Figure
6-1. Numbers in parentheses match numerical callouts on Figure 8-10.
SERVICE MODEL 8559A
8. Installation of Knobs:
a. Turn SWEEP TRIGGER Shaft (24) fully clockwise (as seen from front of Front Switch Assembly) to
spring-loaded SINGLE position and release. Use a no. 4 hex wrench to install SWEEP TRIGGER
knob with SINGLE line aligned with painted arrow on front panel. Check for proper switch opera-
tion and alignment.
b. Turn SWEEP TIME/DIV Shaft (24) to align Ball Bearing (10) on SWEEP TIME/DIV Rotor with
left-most edge of stop boss on Front Switch Diecast (1). This positions SWEEP TIME/DIV Rotor
with Ball Bearing slightly right of 12 o'clock position (as seen from front of Front Panel Assembly).
Use a no. 4 hex wrench to lightly tighten SWEEP TIME/DIV knob onto SWEEP TIME/DIV Shaft
with approximately center of green AUTO position aligned with painted arrow on front panel. Turn
SWEEP TIME/DIV knob to any calibrated sweep time position and align knob markings exactly
with painted arrow on front panel. Tighten SWEEP TIME/DIV knob and check for proper switch
operation and alignment.
c. Uncouple RESOLUTION BW Shaft (55) from FREQ SPAWDIV Shaft (9) by pulling both shafts
out. Turn each shaft fully clockwise. Use a no. 6 hex wrench to install FREQ SPAN/DIV knob with
100 MHz indicated, checking that the plastic indicator guide on back of knob does not completely
bottom into hole in Front Switch Diecast (1). Use a no. 4 hex wrench to install RESOLUTION BW
Knob with 3 MHz indicated. Check for proper operation and alignment of both switches. Push-pull
action should be smooth and positive.
d. Set nylon shim washer(s) and Index Disc (see Figure 6-1) in place on REFERENCE LEVEL knob to
check for proper shim width. Nylon washers should shim Index Disc slightly away from labelled ring
on REFERENCE LEVEL knob to prevent rubbing against painted numbers. Add or remove shim
washers as necessary to provide slight clearance.
e. Turn Attenuator Drive Rotor (8) fully counter-clockwise so that Input Attenuator Pointer guide pin
(P/O 8) is at bottom of front panel. Turn Ref Level Shaft (6) fully clockwise. Place plastic Input
Attenuator Pointer over guide pin (pointer should indicate 70 dB). Place large end of conical spring
against Input Attenuator Pointer and slide REFERENCE LEVEL knob, nylon washer(s), and Index
Disc (from step d) onto Ref Level Shaft, securing with retainer clip.
f. Use a no. 6 hex wrench to adjust Miter Gears (51) for alignment of Input Attenuator Pointer with 70
dB front panel label and proper gear mesh (Input Attenuator A3 still in full counter-clockwise posi-
tion).
g. Turn REFERENCE LEVEL knob to indicate level of - 30 dBm signal and tighten knob securely
with a no. 6 hex wrench. Check for proper operation and alignment of REFERENCE LEVEL and
INPUT ATTEN controls, and readjust knob, gears, and Rotating Lockout (70) as necessary. Refer-
ence Level should range from - 10 dBm to - 100 dBm with 0 dB INPUT ATTEN selected.
h. Turn REF LEVEL FINE Shaft (65) fully counter-clockwise and use a no. 4 hex wrench to install REF
LEVEL FINE knob with 0 dB indicated. Check for proper operation and alignment and readjust
knob as necessary.
i. Turn BASELINE CLIPPER Shaft and VIDEO FILTER Shaft (33) fully counter-clockwise and use a
no. 2 spline wrench to install BASELINE CLIPPER and VIDEO FILTER knobs in OFF position.
Check for proper operation and alignment and readjust as necessary.
j. Install flat and wavy washers on coarse tune shaft as indicated in Figure 6-1. Compress these washers
with retaining ring. A torque of about 1 in-oz should be required to turn coarse tune shaft.
k. Use a no. 4 hex wrench to install COARSE TUNE and FINE TUNE knobs. Base of COARSE TUNE
knob should clear front panel. Check for proper operation of TUNING control.
MODEL 8559A SERVICE
9. Set Front Switch Assembly into place in chassis, being careful not to bend semi-rigid cables or pinch wires
or ribbon cables. Attach Front Switch Diecast (1) to left and right side gussets with four screws.
10. Connect four wires (0,916,918,923) to correspondingly-labelled pins in Front Switch Board A2A1.
12. Connect 10-conductor Ribbon Cable (46) to DPM Driver Assembly AlA2.
13. Connect the two 40-conductor Ribbon Cables A2Al W1 (46) and A2A1W2 (47) to Motherboard Assembly
A16.
14. Use a 5/16-inch open-end wrench to carefully connect Semi-rigid Cable W2 from the Input Attenuator to
the First Mixer.
15. Use special 9/16-inch nut driver to install CAL OUTPUT connector to front panel with one dress nut.
16. Slide HP 8559A into display mainframe, turn instrument ON, and verify proper operation of all controls.
SERVICE MODEL B559A
FACTORY PRESET
SHAFT ASSEMBLIES
BANDWIDTH SHAFT
C
FREQUENCY SPAN SHAFT
NOTE
Arrows point toward
rear of HP 8559A
8-36
MODEL 8559A SERVICE
A B
SWEEP TRIGGER ROTOR SWEEP TIMEIDIV ROTOR
HOLE # 1
HOLE #I7
C D
FREQ SPANIDIV ROTOR ATTENUATOR DRIVE ROTOR
HOLE # I
HOLE #9 '
E F
RESOLUTION BW ROTOR REF LEVEL ROTOR
1 : 4 . 1/13 1 0 -It.?;' F
? I or, 366.5
4il'?SD?4S1 Oh117
I IIn 333'
C: 1 / 8 TO- 1 2 1 7 I-
MODEL 8559A
------ A2A1W1 -- -- -
L16 MOTHERBOARD
1 RIBBON CABLE ASSEMBLY OpM 1
A2A1W1
FANOUT RIBBON CABLE ASSEMBLY
A2AlWlP2 AlAPJl
."Om,
2 I
A2AlWlP3 A2AlJ3
."ow* A2AlJ3 PlNS ARE SHOWN AS SEEN FROM TOP OF
I I.
A2AlJ3 (FRONT OF REAR SWITCH BOARD
ASSEMBLY). NOTE THAT A2AlJ3 CONTACTS 1,7,8,
AND 14 ARE NOT USED. ALSO THAT PIN NUMBERS
MOLDED ONTO PLUG A 2 A l W l P 3 DO NOT
NECESSARILY CORRESPOND WITH A2AlJ3
CONTACT NUMBERS.
A2A1W2
RIBBON CABLE ASSEMBLY
---
'10 A16 MOTHERBOARD
Pl RlbBMI O W L
A21112 r--
P/O A2 FRONT
SWITCH ASSEMBLY
PIN ARRANGEMENT
SHOWN FOR A16J2 IS AS
SEEN FROM TOP
(COMPONENT SIDE) OF
MOTHERBOARD.
The H P 8559A Input Attenuator Assembly A3 is a 50 ohm, precision, coaxial step attenuator. Attenuation in
10-dB steps from 0 dB to 70 dB is accomplished by switching the signal path through one or more of three
resistive pads in a predetermined sequence by the INPUT ATTEN control. The Input Attenuator Assembly A3
is not field serviceable.
The First Mixer Assembly A4 is a sealed microcircuit (shown in Figure 8-19), that is not field serviceable and
must be replaced with either a new or factory rebuilt unit. In the mixer assembly, the -01 to 21 GHz input signals
are combined with the first LO signal (3.01 to 6.04 GHz) generated by the YIG-Tuned Oscillator Assembly A6.
Fundamental mixing is used for the two lowest mixing bands, while harmonic mixing is used for the remaining
four bands. Fundamental mixing produces the sum and difference frequencies of the input and the LO fre-
quency. The fundamental mixing equation is:
F, = F,, -t F,,.
Where: F, = signal frequency
F,, = local oscillator frequency
F,, = intermediate frequency
F, = NF,, -t F,,
Where: N = the harmonic number
An alternate first IF is used to eliminate the problem of IF feedthrough (baseline lift) that occurs when a signal
of the same frequency as the IF frequency (3.0075 GHz) is present at the input. The second LO frequency is
lowered by 15 MHz (from 2.6861 GHz to 2.6711 GHz) to establish the alternate first IF at 2.9929 GHz. The
first LO is also shifted to keep the signal on screen. The shift equation is:
15MHz
Frequency Shift = + N
Where: N = the harmonic number
A 17 -23 MHz bandpass filter, in the Second Converter Assembly A5 housing, follows the first IF and is
centered at 3 GHz. The wide bandpass accommodates signals in either the regular or alternate IF modes.
A schematic of the First Mixer Assembly A4 is shown in Figure 8-25. The output of the YTO is coupled into the
signal path ahead of the internal mixer. Mixing diode bias is supplied from the Step Gain Assembly A12. A
different bias current is used for each harmonic to minimize conversion loss and flatness problems. In addition
+
to mixer bias, the First Mixer Assembly A4 requires a 14.5V and - 10V to power and bias the transistor
buffer amplifier at its output. Conversion loss of the mixer is about - 12 dB.
8-51
SERVICE MODEL 8559A
Typically, a bad first mixer results in at least a 15 to 20 dB loss in sensitivity (i.e., the amplitude of displayed
signals is 15 to 20 dB low). There are, however, other factors that can affect spectrum analyzer sensitivity that
should be checked. The measurement of power levels along the signal path can give a good indication of where
the loss is occurring. The output of the Second Converter Assembly A5 offers a convenient point to isolate the
RF front-end from the IF section. If the loss appears to be in the front-end, measure the power levels of the first
and second local oscillator with a second spectrum analyzer. Next, measure the supply and bias voltages at the
first mixer. To access the push-on connectors of the first mixer's bias and supply lines, it is helpful to remove the
instrument's bottom guide-rail.
NOTE
Before making the following adjustments, measure and note the first mixer
bias voltage (A16TP1). This permits the instrument to be returned to calibra-
tion if the first mixer is good.
Adjust the V1 potentiometer (A12R72 on the Step Gain Amplifier Assembly A12) through its range and
observe the changes in the displayed signal peak and the bias voltage. With a good mixer, two changes are
observed: the displayed signal peaks at some point in the adjustment (usually with about - 5V or - 6V of bias
voltage) and the bias voltage (A16TPI) ranges from - 9V to + 2 k 0.5Y If all of these characteristics are not
present, the mixer is probably damaged.
MODEL 8559A SERVICE
The IF from the First Mixer Assembly A4 is coupled into the Second Converter Assembly A5 bandpass filter
through coupling loop L3. Three circular, slug-tuned cavity resonators, operating as an inductive transmission
line, make up the bandpass filter. The filter forms a high-Q circuit centered at 3 GHz with a 23 MHz bandwidth
that is required to accommodate the regular and alternate IFs. Coupling loops L4 and L5 provide coupling
between the cavities. Loop coupling is also used to couple the 3 GHz IF signal to the second LO output at the
mixer diode CR1.
The second LO contains varactor diodes that are controlled by a voltage from the Marker Assembly A8. The
diodes shift the frequency of the second LO either 15 MHz (ALT IF) or + 1 MHz (SIG ID). The varactor
control voltage is always between 1V and 28V and corresponds to the oscillator frequency; increasing the
voltage increases the frequency.
Both the second LO and the 3 GHz IF signal are coupled into mixing diode CR1, generating a difference
frequency of 321.4 MHz that is coupled through the matching filter (C3, L2, C4) to the Third Converter
Assembly AlO. The matching filter is a passive network designed to match the impedance of the second mixer
to the 50 ohm impedance of the Third Converter Assembly A10. The match is optimized in both IF modes by
adjusting L2 (2nd MIXER MATCH).
Verify that the Second Converter Assembly A5 supply voltages are correct.
If the displayed signal amplitude varies between ALT IF and REG IF, perform and verify the bandpass and
second LO frequency adjustments.
Second LO Frequency: A failure in the Second Converter Filter Assembly A5A2 can cause the Second
Converter Oscillator A5A1 to oscillate at about 3 GHz. This symptom can occur when the delay circuit in the
filter assembly does not delay the application of the + 13V bias voltage. To test the delay, observe the + 13V
bias as the instrument is turned on. There should be a noticeable delay before the + 13V is applied to the line.
The - 10V supply, on the other hand, should rise gradually. If the + 13V and the - 10V respond properly, check
the varactor voltage, varactor diodes, and the cavity adjustment as the possible source of the second LO
frequency error.
Second LO Fails to Oscillate: The Second Converter Oscillator Assembly A5A1 can intermittently fail to
oscillate after turn-on. If this symptom occurs, replace the entire assembly. Before removing the defective circuit
board, note the orientation of components, leads, and hardware; orientation is critical to proper operation. To
prevent damage to the replacement circuit board, do not over-tighten the hex-head antenna screw during instal-
lation.
Second Converter Bandpass Shape: Low signal power from the First Mixer Assembly A4 can distort the
second converter bandpass filter shape. Excessive ripple in the bandpass can be the result of a mismatch in the
signal path preceding the Second Converter Assembly A5. An input attenuator setting of 0 dB can cause such a
mismatch. The second converter mixer diode or Mixer Match adjustment can also affect the bandpass ripple.
Residual FM: Residual FM can originate from the Marker Assembly A8 Second LO Driver, which supplies
the varactor bias voltage, or from within the second LO itself.
8-53
MODEL 8559A
The YIG-Tuned Oscillator Assembly A6 consists of three parts: a sealed magnet assembly that encloses the YIG
sphere and oscillator; a bias board that uses discrete components to establish the oscillator and amplifier bias, as
well as protect the bias supply from noise and voltage overloads; and a mu-metal magnetic-shield can. Field
service of the YIG-Tuned Oscillator Assembly A6 is limited to replacement with a new or factory rebuilt unit.
The YIG-Tuned Oscillator A6 is a transistor thin-film microcircuit. It uses a Yttrium-Iron-Garnet (YIG) sphere
as the frequency determining structure. The YIG sphere is placed in the gap of an electromagnet to provide a
magnetic tuning structure whose field (and thereby the oscillator's frequency) is linearly proportional to the
drive current from the Frequency Control Assembly A7.
The Main coil is used for wide range sweeping and tuning with the coil current varying from approximately 69
mA to 138 mA. The FM coil performs these functions for narrow spans (1 MHz/div and less) with its coil
current varying from approximately - 18 mA to + 18 rnA.
Power Holes: Power holes that occur at the same point of the sweep in all bands are most commonly caused
by the YIG-Tuned Oscillator Assembly A6.
Power holes above 18 GHz are most commonly caused by the type-N RF input connector on the HP 8559A
front panel.
Residual FM: The primary cause of residual FM involving the first LO is the Frequency Control Assembly
A7.
MODEL 8559A SERVICE
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COVER MP1 L4 L5 2ND CONV OUT 52 TUNING SLUG 2 4 FL4 FL3
2N D SECOND CONVERTER
MIXER MATCH
- 2ND LO OSCILLATOR ASSEMBLY
TUNING SLUG 2 1 TUNING SLUG 2 2 TUNING SLUG 2 3 L2 L1 C3 OUTPUT J3 A5A1
2ND CONVERTER VA R
INPUT J l (UNDERNEATH) FLl CR2
A5A2
SECOND CONVERTER FILTER ASSEMBLY
P VARACTO R
1 V TO 28V
--- --7
I N P U T ATTENUATOR A ~ ~ R S T ~
1 86240-60022 I I M I XER 1 FLI 4 . l O H a
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YIG-TUNED OSCILLATOR FIRST MIXER 3 dB ATTENUATOR
ASSEMBLY A6 ASSEMBLY AT1
The Frequency Control Assembly A7 drives the YIG-Tuned Oscillator Assembly A6 and provides the regulated
+ 14.5V and - 10V supplies to the First Mixer Assembly A4, the Second Converter Assembly AS, and the
Marker Assembly A8. Inputs to the Frequency Control Assembly A7 consist of the tuning voltage and the band
information from the Front Switch Assembly A2, as well as the attenuated sweep from the Marker Assembly
A8. The tuning voltage is routed to the Marker Assembly A8 while the sweep plus tune (S + T) voltage goes to
the Step Gain Assembly A12 and Vertical Driver/Blanking Assembly A15. The YIG Tune Voltage (YTV) is
applied to the biasing circuitry of the YIG-Tuned Oscillator Assembly A6.
Coarse and fine tune voltages from the front panel are summed and buffered by U12 and resistors R77, R78,
and R79. This summed voltage is routed to the YTO Main Coil Tune Driver through Q13. It is also routed to the
Marker Assembly A8 to be conditioned for the Digital Panel Meter Assembly A1. Resistors R64 and R65 divide
the - 10V supply to develop - 5V at the noninverting input of U11, which buffers the voltage for use as the
mid-band tune voltage required for full sweep operation.
With the selection of full sweep operation, PI-41 (FS9) goes to + 15V and Q l l turns off. Without current
flowing in R90, Q10 is off. This allows Q9 to turn on because Q10 no longer supplies the positive gate-source
voltage that holds Q9 off. At the same time, 412 turns on, shutting 413 off. This routes the - 5V supplied by
U11 to the YTO Main Coil Tune Driver tuning the YTO to mid-band. When full band is not selected, PI-41
(FS9) is close to ground potential due to A8CR19, A8R91, and A8R92, on the Marker Assembly A8 (block B).
This results in Q10 turning on, holding Q9 off. Transistor A12 is now turned off, removing the pinch-off
voltage on 413. The tune voltage from the front panel now adjusts the YTO center frequency.
Operational amplifier U10 and resistors R61, R62, R72, R76, R80, and R82 sum and offset the applied tuning
and sweep voltages and convert them to the current required to tune the YTO. The current is set by the voltage
across R48 and the 6 GHz adjustment R47. Shaping of the voltage-to-current function is necessary to maintain
the linearity of the YTO sweep. This shaping is accomplished by using CRS, in conjunction with R59* and
R60*, to establish two break points in the sweep ramp. MOSFET Q8 adds current drive capacity to the output
of U10. Offset and buffering of the sweep plus tune voltage takes place in U9. It supplies the sweep plus tune
voltage to the limit comparator on the Vertical Driver/Blanking Assembly A15 and to the first converter band
tilt circuit on the Step Gain Assembly A12. Operational amplifier U9b supplies the YIG Tune Voltage (YTV) at
1V per GHz to the biasing circuitry of the YTO. This adjusts the YTO, controlling its harmonic output. Delay
compensation for main coil sweeps is provided by C12* and R58.
Quad switch U15 routes the attenuated sweep ramp to the YTO Main Coil Tune Driver or to the YTO FM Coil
Driver while grounding the unused inputs. Transistor 416 provides level shift for the switch drive and is con-
trolled by the FREQ SPAN/DIV control.
The YTO FM Coil Driver sweeps the YTO in spanwidths of 1 MHz per division and narrower. Operational
amplifier U13 inverts the sweep voltage and drives the push-pull current driver comprising 414 and Q15.
SERVICE MODEL 8559A
Resistor R92 is an adjustable current limiter that makes possible sweep width adjustment by changing the gain
of the stage. Delay compensation for FM coil swept spans is provided by U14, C14, R96*, and potentiometer
R83, the delay compensation adjustment.
This driver supplies current to the YTO main coil to set the start frequency of the first LO WIG-Tuned Oscilla-
tor Assembly A6) at approximately 3 GHz. Resistor R8 adjusts this frequency by changing the reference voltage
at U3 and, therefore, the drive to Q5. MOSFET Q5 buffers the operational amplifier's output and supplies
current drive to the YTO main coil.
A voltage divider, R18 and R19, form a nominal + 5V source that supplies U7 and establishes pull-up voltages
on the H2, H3, and PM lines. When alternate IF is selected, current to the YTO main coil changes, shifting the
sweep-center frequencies by + 15 MHz/N, where N is the harmonic number associated with the selected band.
Four-to-ten-line decoder U4 decodes front panel band information and activates the appropriate section of U1.
This selects the resistor that is paralleled with R9 in the YTO Main Coil Fixed Driver. Altering the effective
resistance of R9 changes the current drive to the YTO main coil by changing the gain of the YTO Main Coil
Driver circuit.
Precision, temperature compensated, Zener diode VR2 provides the reference for the voltage regulators. The
output of the + 14.5V supply is fed back through R39 to bias VR2, while VR3 ensures that VR2 initially turns
on. Transistor 4 4 is a series pass element driven by U6 and Q5, while R35, R40, and R41 sample the output
voltage and provide adjustment.
The - 12V supply tracks the + 14.5V supply and consists of a pass element, 47, driven by U8.
The - 10V regulator supplies the voltage to the TUNING control, and is heavily filtered by C3 and R33.
Transistor 4 6 is the series pass element driven by U7 and resistor R29 adjusts the output voltage level.
The Frequency Control Assembly A7 is the principal cause of excessive residual FM of the YIG-Tuned Oscilla-
tor's output. The following are a series of tests to help isolate the source of FM to a function block on the
Frequency Control Assembly. Components most likely to be the source of the FM in each block are also listed.
Be sure to check the following power supply voltages, for correct level and excessive ripple, before proceeding:
the + 14.5V Regulator (block H), the - 10V Regulator (block I), the - 12V Regulator (block K), and the + 15V
and - 12.6V Power Supplies (block J).
MODEL 8559A SERVICE
In the next steps, edge connector contacts on the circuit board are taped
over to isolate portions of the circuit. After completing a step where taping
is necessary, remove the tape and clean the circuit board edge contacts
with an 80120 solution of isopropyl alcohol and water before continuing to
the next step. Refer to PRINTED CIRCUIT BOARD EDGE CONNECTOR
CONTACT CLEANING at the beginning of this section for a detailed descrip-
tion of the cleaning procedure. Care should also be taken whenever
instructed to unsolder components during the test.
NOTE
a. To observe the first LO, connect a second spectrum analyzer to the H P 8559A RF input (a significant
fraction of the first LO power is coupled to the RF input by the First Mixer Assembly A4). When mea-
sured in this manner, the first LO power should be - 8 dBm t 3 dBm at about 3 GHz for the listed control
settings. This setup is used to observe the first LO in all of the following tests.
b. Begin by isolating the YTO Main Coil Tune Driver from the remainder of the frequency control circuit.
This is accomplished by taping over P1-3 on the circuit board edge-connector contacts.
c. If the residual FM is unchanged, assume that the YTO Main Coil Tune Driver and the circuits feeding it are
not the source of FM. The next step is to isolate the YTO FM Coil Driver from the circuit by taping over
PI-15 and PI-37.
d. If the residual FM is unchanged, assume that the YTO FM Coil Driver is not the source. Proceed by
placing a short across C1. This isolates the YTO Main Coil Fixed Driver from the circuit. Since the YTO
Main Coil Fixed Driver supplies the majority of the YTO operating current, the YTO will not operate
when the YTO Main Coil Fixed Driver is isolated from the circuit. To compensate for this, it is necessary
to increase the current supplied by the YTO Main Coil Tune Driver. Adjust the TUNING control of the
H P 8559A under test for a frequency display of 3 GHz; this supplies enough current from the YTO Main
Coil Tune Driver to allow the YTO to oscillate at about 3 GHz.
SERVICE MODEL 8559A
Observe
1 s t L.O.
I s o l a t e YTO
Main C o i l
Tune D r i v e r
I s o l a t e YTO FM Source o f FM
Replace Tune YES i s YTO FM
Voltage w i t h Coil Driver Coil Driver
0 I0
Source o f FM Source o f FM i s
1s n a i n c o i l FM/Main C o i l FM?
Tune D r i v e r
0 I
I NO
1
Replace -1OV I s o l a t e YTO Source o f FM
Regulator with Main C o i l i s FM/Main
Battery Fixed Driver C o i l Switch
Ir
Source o f FM NO
i n -iOV Source o f FM NO
Regulator i s ~ a i nc o i l
0 I
I . Fixed Driver
0 19
i n Tune/Full
Span V o l t a g e
+fpq
Text Annotation
Schematic B l o c k Reference
Reference YES
Step I n s t r u c t i o n
I d
goes h e r e . Source o f FM
i s YIG-Tuned
O s c i l l a t o r . A6
If the residual FM is unchanged, assume that the YTO Main Coil Fixed Driver is not its source. Retune the
HP 8559A to minimum, .010 GHz. Isolate the YTO Main Coil Filter from the circuit by mounting the
Frequency Control Assembly A7 on an extender board and taping over PI-19, PI-20, P1-25, while short-
ing PI-2 to PI-19.
If the residual FM is unchanged, the probable source is the YIG-Tuned Oscillator Assembly A6.
If isolating the YTO Main Coil Tune Driver from the frequency control circuit eliminates the residual FM,
proceed to further isolate the source by shorting the sweep from block A to ground. This is best accom-
plished by shorting the input side of R80 to the ground side of R63. Use a short jumper to prevent the
induction of line frequency noise into the circuit.
If the residual FM is eliminated, the source is probably the FM/Main Coil Sweep Switch. The most
common failure is U15.
If residual FM is present after shorting the input sweep, remove the jumper and substitute a battery for the
tune voltage. Do this by carefully unsoldering the input side of R82 and inserting a battery (5V to 10V)
between the free end of R82 (the " - " terminal) and the grounded end of R63 (the " + " terminal). Use the
shortest possible leads to prevent line frequency noise pickup.
If residual FM is unchanged, the probable source is the YTO Main Coil Tune Driver. The most common
failures are: U10, R72, R76, R61, R80, R63, and R62, in that order.
In this step, the - 10V regulator is replaced with a battery. Replace R82 and tape over P1-5. Attach the
negative (- ) battery lead to pin 3 of U12; attach the positive (+) lead to the grounded end of R63. If the
residual FM is eliminated, the probable source is the Tune/Full Span Voltage (block B). If the residual FM
is unchanged, remove the battery and the tape. Tune the FINE TUNE control to minimum, remover the
(945) wire from the COARSE TUNE control (A2R1), and attach the battery's negative (- ) lead to the
COARSE TUNE control in place of the (945) wire. Attach the positive (+ ) battery lead to the ground side
of R63. This test is necessary to eliminate the TUNING control as a source of residual FM.
If using the battery in place of the - 10V regulator eliminates residual FM, the - 10V regulator is the
probable source. All of the regulator parts can cause instability; however, the most common failures are:
U7, R30, R33, R32, C3, R29, and VR2 (block H), in that order. Also, verify that all supplies are properly
adjusted.
If the Tune/Full Span Voltage (block B) is the probable source of the FM, the most common failures are
U12 and 413.
If isolating the YTO FM Coil Driver eliminates the residual FM, short the incoming sweep to ground.
Install a jumper between the input side of R97 and the ground side of R95. Use the shortest possible lead
to minimize line frequency noise pickup.
If the residual FM is unchanged, the source is probably the YTO FM Coil Driver. The most common
failures are U13 and U14.
If the residual FM is eliminated, the source is probably the FM/Main Coil Sweep Switch. The most
common failure is U15. If the residual FM is unchanged, short TP8 to ground. If this eliminates the
residual FM, the source is probably on the Marker Assembly A8.
If isolating the YTO Main Coil Fixed Driver eliminates the residual FM, it is probably the source of the
FM. The most common failures are: U2, C1, R1, and R2, in that order.
If removing the YTO Main Coil Filter from the circuit eliminates residual FM, it is probably the source of
the FM. The most common failure is Q5. If the FM is not eliminated, the most common failures are
A16Q1 and A16C22.
&711&72
MODEL 8559A SERVICE
I Reference
Designation
HP Part
Number
Description Mfr Part Number
ALTERNATE
I F DRIVERS
COARSE TUNE
> tsv -
! FS6
'
YOR-
I
VOLTAGE '
-1OV -
1 TUNE REF
I , ,
REGULATOR
:
t j 4 . s ~
- ,
tisv
, -
FIGURE 827. FREQUENCY CONTROL ASSEMBLY A7, BLOCK DIAGRAM
SERVICE MODEL 8559A
A7
FREQUENCY CONTROL ASSEMBLY
SwP \ h
*\
TUNE
GND
&-
YTO
The Marker Assembly A8 comprises the Marker Generator, the DPM and Second LO Drivers, the ALT IF and
SIG IDENT circuits, the Auto Scan Time Drivers, and the Scan Attenuators.
The Marker Generator is basically a zero voltage detector. The four summed resistor voltages at pin 5 of U14
equal OV only when the sweep voltage and the tune voltage correspond to the same frequency. The marker is
then displayed at that frequency. If the input of U14b (pin 5) is at OV, the outputs (pins 7 and 1) should be at OV.
The anodes of CR7 and CRlO should therefore be at OV also. Resistor R45 pulls their cathodes down to about
- 0 . N This turns on U6c, which normally has its emitter held to about +0.7V ( + 1.2V in fullband). As the
emitter voltage of U6c increases, it turns on Q1. This pulls the video shift line down, shifting the signal and
noise at the Log Amplifier Assembly A14 about one division toward the bottom of the screen. The output of
the Log Amplifier Assembly A14 is permitted to be pulled low by the log shift resistor (A14R119) at its output.
The DPM Driver is an inverting operational amplifier circuit. The appropriate combination of input, offset,
and feedback resistors is selected by U5 for the chosen frequency band (see Figure 8-30). Input control lines H2,
H3, and PM carry the encoded band information. A truth table on the schematic, Figure 8-33, shows the levels
of these lines during each band.
t R offset
R Feedback
SELECTS
R ~nput R offset
R Input and
R Feedback
The Second LO Driver varies the voltage applied to the varactors in the second LO cavity (A5CR2 and A5CR3).
The upper limit of this voltage is dependent on the second LO sensitivity and varies during operation from
about I V to between 7V and 30V. An increase in the drive voltage increases the second LO frequency. The SIG
IDENT and ALT IF buttons both change the second LO frequency.
ALT IF. When ALT IF is not selected, TP2 is at -7.5Y setting the collector of 4 2 to + 15V (f7V). When
ALT IF is selected, TP2 goes to - 2.5% setting the base of 4 2 to about + 5V. The voltage on the collector of 4 2
varies within the range of 1V to 28V as needed to drive the varactors in the Second Converter Assembly A5. The
shift in drive voltage serves to offset the second LO to the alternate IF.
SIG IDENT. When SIG IDENT is not selected, U10 pin 4 is low and pin 11 is high. This supplies a current
through R37 and R38 to bias the second LO 1 MHz away from its minimum frequency. When SIG IDENT is
selected, pins 4 and 11 both are either high or low together, depending on the sense of the PM line (PM is low
for bands 1, 3, and 5). This either raises or lowers the frequency of the second LO 1 MHz. Resistor R39
provides additional shift, if necessary, when ALT IF is not activated (the second LO may be less sensitive at that
frequency). Flip-flop U3 alternates both the frequency shift and level shift on every other retrace.
As scan and bands change, sweep times must be changed to maintain amplitude calibration. The AST (auto
scan time) line, which goes to the Sweep Generator/Bandwidth Control Assembly A9, varies the sweep time by
varying the amount of current it carries. More current speeds the sweep rate, less current slows it. The current is
controlled through a current mirror on the Marker Assembly A8, comprising U6a and U6d. The current mirror
is a common-emitter amplifier with a current gain of - 1. Collector current changes through U6a (caused by
Ul 1a, U11b, or U l lc turning on) are mirrored in U6d.
Operational amplifiers U13 and U17 are buffer amplifiers that are not directly involved in the switchable scan
attenuation, but, if one fails, the scan becomes uncalibrated. The switching is done by 4 4 , Q6, and U12. For
fundamental mixing bands 1 and 2, U12b is on, all others are off. Resistors R22 and R23 form a voltage divider
with R24, R25, and R26. The division ratio is changed depending on whether 4 4 and 4 6 are on or off. For
higher mixing modes (bands 3 through 6), U12a or U12d is switched on, picking off the sweep from a lower
amplitude point on the voltage divider. For full span operation, U12c is enabled so that no attenuation is added
for higher mixing modes.
DPM Accuracy: DPM inaccuracy is often traceable to the calibrated-gain circuit in the DPM Driver (block
D). The most common cause is the gain determining resistors associated with U15. A generalized model of U15,
with associated resistors, is shown as Figure 8-30. Variations in the input resistors or in the feedback resistors
will cause DPM inaccuracies throughout its range. Offset resistor variations primarily affect the low end of the
range. When troubleshooting DPM inaccuracies, always start with the components related to the worst band.
Marker Accuracy: The marker accuracy is dependent on the frequency accuracy of the first LO and the
frequency accuracy of its sweep end-points (i.e., the frequencies that correspond to the + 5V extremes of the
sweep).
Spanwidth Accuracy: Observe the positions of the FREQ SPAN/DIV switch and how they relate to the
spanwidth errors. The problem could be originating from either the Marker Assembly A8 or the Sweep Genera-
tor/Bandwidth Control Assembly A9 or both.
8-84
MODEL 8559A SERVICE
Auto Scan Time (AST) Accuracy: Observe front panel switch positions to isolate the problem area. Auto
scan time can also be affected by circuits on the Sweep Generator/Bandwidth Control Assembly A9 and the
VIDEO FILTER control position. If the AST problem is band-related, the Marker Assembly A8 is the most
probable cause. If the AST problem is either bandwidth- or scanwidth-related, the most probable cause is the
Sweep Generator/Bandwidth Control Assembly A9. The greater the load on the AST line, the greater the
current demand. The greater the current demand, the faster the sweep rate.
Residual FM: Residual FM can originate from the Second LO Driver (block E). The most common failures
are: R88, R87, R33, R34, U1, U7, R37, and R38, in that order.
MODEL 8559A SERVICE
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SCAN ATTENUATOR
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--
FIGURE 8-31. MARKER ASSEMBLY A8, BLOCK DIAGRAM
SERVICE MODEL 8559A
A8
MARKER ASSEMBLY
b92
MODEL 8559A SERVICE
The Sweep Generator/Bandwidth Control Assembly A9 consists of the sweep generator circuit, the sweep
trigger circuits, the resolution bandwidth control circuits, the video filtering circuits, the sweep attenuator
circuit, and the sweep offset circuit.
A linear sweep from - 5V to + 5V is provided by the sweep generator circuit. Normally, the sweep operates in a
free run mode with sweep times automatically generated as a function of the FREQ SPAN/DIV, RESOLU-
TION BW, VIDEO FILTER, and BAND settings.
Fixed calibrated sweep times are available, ranging from 2 microseconds per division to 10 seconds per division.
This equals a full sweep time (10 divisions) of 20 microseconds to 100 seconds. Fixed sweep times are set with
the SWEEP TIME/DIV control and are used mainly in zero span to determine the modulation frequency of an
input signal. Modulation frequency determination is possible because during zero span operation the analyzer
displays the signal in the time domain rather than the frequency domain. The sweep can also be controlled
manually from the front panel with the MAN sweep control.
Besides internal triggering, SINGLE, VIDEO, and LINE triggering modes are also available. SINGLE starts or
stops a single sweep from the front panel. VIDEO triggering allows the sweep to be synchronized with the
displayed video signal. LINE mode synchronizes the sweep with the line frequency. Single sweeps can be initi-
ated via HP-IB if an HP 853A Spectrum Analyzer Display is being used.
The resolution bandwidth control circuit has three functions: First, it provides bandwidth-filter-control current
to the PIN diodes on the Bandwidth Filter assemblies (A1 1 and A13). Second, it provides current to the sweep
generator current source (via the AST line) to control the automatic sweep time circuit as a function of resolu-
tion bandwidth. Third, it switches in capacitance to the video filter to provide video filtering as a constant
percentage of resolution bandwidth.
The sweep attenuator circuit attenuates the sweep ramp to the Frequency Control Assembly A7 in proportion to
the FREQ SPAN/DIV selected. It also provides current to the sweep generator current source (via the AST line)
to control the automatic sweep time circuit as a function of the FREQ SPAN/DIV control setting. Note, the
sweep ramp passes through the Marker Assembly A8 before being attenuated by the sweep attenuator.
Sweep Generator
The sweep generator circuit comprises the current source, the buffer amplifier, the comparator, and the retrace-
out buffer amplifier. A simplified schematic is shown in Figure 8-34.
When AUTO sweep is selected, the voltage ramp is generated as follows: The ramp begins when the dead time
capacitor (comprising C10 and Cl1 in block L) charges to about + 1.2V through R44.This turns 433 on and
drives pin 2 of the comparator (block H) below +2.78\! The output of the comparator then rises to about
+ 14V,reverse biasing reset-diode CR2 (block I).
897
SERVICE MODEL 8559A
AMPL l F l E R
=t1OV RETRACE
= +0.5V SWEEP
With CR2 off, the current source begins charging the timing capacitor (C3 and C4, block I). As the timing
capacitor charges, the output of the buffer amplifier increases linearly. Transistor 4 3 3 is on and its collector
voltage is about + 0.5Y The voltage at U1 pin 2 is mainly established by sweep voltage divider R29, R39, and
R47*. (Components VR1, CR4, and R40 feed back some of the comparator's output to pin 2 and act upon the
divider. These components have been omitted to simplify the model; see block L on the main schematic.)
When the ramp voltage reaches + 5V, the U1 pin 2 is approximately + 2.78V. Consequently, the comparator's
output swings to about - 4V. This negative change reverse biases CR6 and turns 4 3 3 off. Resistors R42*, R39,
and R29 form a divider that, when combined with the feedback loop and the buffer amplifier, sets the ramp
voltage at - 5V during the dead time. (Factory selected resistor R42* adjusts the dead time voltage.)
The timing capacitor is discharged by the comparator and quickly reaches - 5V. The ramp remains at - 5V until
the dead time capacitor charges to + 1.2V and the sweep cycle is repeated.
Other components in the sweep generator have the following functions: Capacitor C6 speeds up the switching of
U1. Capacitor C8 and resistor R33 desensitize U1 from power spikes. Frequency compensation for U1 is
provided by C9, feedback compensation by C7. Zener diode VR1, switching diode CR4, and resistor R40 bring
U1 out of saturation at the end of the ramp to improve switching time.
&98
MODEL 8559A SERVICE
I
@SWEEP D E A D
SW l TCH TIME SWITCH
6&7
I I
FIGURE8-35. SIMPLIFIED SCHEMATIC OF FASTISLOWSWEEP TIME OPERATION
Timing capacitors C3 and C4 provide fast and slow sweep operation (refer to Figure 8-35). When a sweep time
less than or equal to 1 millisecond per division is selected with the SWEEP TIME/DIV switch, sweep control
line ST6 is grounded. This turns sweep dead time switch 4 6 (block K) and fast sweep switch 4 7 (block J) off.
With 4 7 off, C3 and C4 are in series; C4 effectively becomes the timing capacitor. With 4 6 off, + 15V at R46
reverse biases CR9 and CR8, switching C10 out of the dead time circuit. Capacitor C11 now sets a short dead
time of about 0.4 millisecond.
In sweep times greater than or equal to 1 millisecond per division or in automatic sweep, control line ST6 is
open, turning both Q6 and 4 7 on. Transistor 4 7 grounds C3 and it becomes the timing capacitor. Transistor 46
forward biases CR8 and CR9, paralleling C10 and C11. The dead time is effectively established by C10 at about
8.0 milliseconds.
SERVICE MODEL 8559A
The pulse shaper circuit (block M) consists of an FET switch, a Schmitt trigger, a differentiator, and an emitter --
follower (see Figure 8-36). Field-effect transistor 456, and its associated components, disconnects the base of
435 during the sweep cycle to prevent the Schmitt trigger from firing during a sweep. Transistors 434 and 435
make up the Schmitt trigger. Transistor 435 is normally off; 434 is conducting. On the positive portion of the
input signal (either video or line), 435 is driven into conduction, turning 434 off. The switching speed of 434
and 435 is increased by feedback (between the collector of 435 and the base of 434) through C13 and R58.
When 435 switches on, the negative change at the collector is differentiated by C14 and R60 and coupled
through 436 to the emitter of 433. The negative pulse causes 433 to turn on. Zener diode VRl switching diode
CR5, and resistor R41 keep 433 on while the ramp is generated. When the ramp is completed, the circuit
returns to its dead time state until another negative trigger pulse begins a new sweep cycle.
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Free Run
During the FREE RUN (internally triggered) mode, the trigger switch grounds the sync line, which removes the
pulse shaper (block M) from the circuit. At the same time, the switch applies + 15V through the trigger (TRIG)
line to voltage divider R52 and R53 (block L). This divider sets the voltage at the cathode of CRlO at approxi-
mately + 1.4Y Since the voltage drops across CRlO and CR6 are equal but opposite, they cancel. For this
reason, the base of 433 is also about + 1.4Y Transistor 433 turns on and drives the comparator to about
+ 14V, initiating free run operation as described in the sweep generator section.
Video Triggering
When the TRIGGER switch is in the VIDEO position, the trigger line is open and the video signal (from the
Vertical Driver/Blanking Assembly A15) is applied to the pulse shaper (block M) through the sync line. With the
trigger line open, 433 is held off until a negative pulse turns 433 on and begins the sweep cycle outlined in the
sweep generator description. At the end of the sweep, 433 is again held off until the next pulse.
Line Triggering
The sweep may be synchronized with the ac line voltage in the same manner as described for video triggering.
With the TRIGGER switch in the line position, the ac line from the mainframe power transformer is connected
MODEL 8559A SERVICE
to the Pulse Shaper. Resistor A16R2 and capacitor A16C8 on the motherboard attenuate the ac line signal to
approximately 1V peak-to-peak (at the base of 435) and filter line spikes.
Single Sweep Triggering and Abort
When the TRIGGER switch is in the single sweep position, the sync line is grounded and the single line open.
Transistor 433 is held off by the voltage developed across CRlO and R53. The voltage at the collector of 433 is
at + 10V, putting the emitter of 438 at + 9.4V This charges C15 to + 2.4V through voltage divider R48 and
R49.
A sweep is initiated when the trigger switch is set to the spring-loaded SINGLE position and + 15V is applied to
the single trigger switch (block N). When 437 turns on, a negative pulse is produced at the emitter of 433 due to
voltage stored by C15. This pulse turns 433 on and starts the sweep cycle.
The sweep may be aborted (reset to - 5V) by pressing the single sweep switch while the sweep is in progress.
During the sweep, the collector of 433 is at + 0.5V This puts the emitter of 438 at OV and charges C15 to - 4V
through voltage divider R48 and R49. Now when + 15V is applied to the single trigger switch (block N), 437
turns on and a positive pulse appears at the emitter of 433. Consequently, 433 turns off and the sweep is
aborted.
Manual Sweep
Manual sweep control is obtained when the SWEEP TIME/DIV switch is set to MAN. In the manual position,
ST7 is open (see Figure 8-37). Transistor 440 turns 433 on by supplying current to its base and 439 acts as a
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switch that connects R34 to the comparator. Turning the manual sweep control (A2R4) adjusts the voltage at the
control side of R34.
Operational amplifier U1, operating in a linear mode, fixes the voltage at pin 2 by feedback through CR2, the
buffer amplifier, and R29. This fixed voltage is applied through 439 to one side of R34. As the manual sweep
potentiometer is adjusted, the voltage across R34 changes, varying the current supplied to pin 2 of the compara-
tor. This current is forced through R29 and develops the voltage offset that varies the ramp voltage.
The current source provides a constant charging current to the timing capacitors (block I) at a rate selected by
either the SWEEP TIME/DIV switch or the automatic sweep time (AST) line.
Temperature compensation of the current source is accomplished by the nominal + 10V supplied by the temper-
ature-dependent power supply (block P). The 1 MS (one millisecond) adjustment fixes a voltage at pin 3 of U2a,
while the 5 MS adjustment varies the feedback around U2a.
During calibrated sweep time settings, the Sweep Cal. Switch (Qll in block G) is off. This allows the feedback
ratio of U2a, the voltage source, to be varied by grounding different input resistor combinations (R21 through
R24) with the SWEEP TIME/DIV switch. In the automatic sweep mode, Sweep Cal. Switch Q l l is turned on
by current through Q9 and R25. The feedback ratio now varies with the resistors attached to the AST line and
switched in by various settings of the FREQ SPAN/DIV and RESOLUTION BW switches. When the video
filter is on, it also affects the feedback and, therefore, the sweep time, by varying the voltage at the emitter of
Q8a.
The voltage applied to the emitter of Q8a from voltage source U2a is proportional to the logarithm of the sweep
time. Transistor Q8a converts this voltage to a current directly proportional to the sweep time, which charges
the timing capacitors in the buffer amplifier. A current limiter composed of Q5 and R15 limits the automatic
sweep time to about 1.5 milliseconds per division.
When the RESOLUTION BW switch selects a crystal filtered bandwidth (530 kHz), bandwidth control line
BW5 is open and pulled to - 0.5V by 412 and Q10 in the Xtal PIN Driver Buffer (block D). As a result, four
simultaneous changes occur in the analyzer: the crystal poles on the Bandwidth Filter assemblies are activated,
the LC poles are disabled, the crystal bandwidth-control current is established, and the automatic sweep time is
scaled for the crystal bandwidths.
Control line BW5, from the RESOLUTION BW switch, is routed to the Bandwidth Filter assemblies (A11 and
A13) where it activates the crystal filter poles. (Refer to Bandwidth Filter Assembly No. 1 All, Circuit Descrip-
tion and Schematic.) It reverse biases A1 1/A12CR2 (block D) and A1 1/A13CR13 (block G). At the same time,
A1 l/Al3Q3 and A1 1/A13CR8 (block D), and A1 l/Al3Q6 and A1 l/A13CR15 (block G) are turned on.
The LC poles on the Bandwidth Filter assemblies are disabled by a positive voltage on the BW7 control line.
Voltage for BW7 is generated in the LC PIN Driver Buffer (block C) on the Sweep Generator/Bandwidth
Control Assembly A9. Control line BW5 turns A1 l/A13Q22 off, allowing BW7 to be pulled to a level greater
than + 1OV by A1 l/A13CR17 and A1 l/Al3RlO5. This turns off the LC filter sections.
MODEL 8559A SERVICE
Crystal filter bandwidth is determined by the current on BW6. Transistor 413 in the Xtal PIN Driver Buffer
(block D) is turned off, allowing 414 to establish the bandwidth control current. Depending on the setting of
the RESOLUTION BW switch, one of the bandwidth control lines (BWl through BW3) is at + 15V while the
remaining two are open and pulled to a negative voltage. The positive voltage turns on one of the transistor
switches in the Xtal Resolution Bandwidth Control (442,444, or 446 in block B). The current on BW6 is now
established by one of the factory selected resistors, R109, R110, or R111, and the setting of R72 (the crystal
bandwidth adjustment, block D). When the 30 kHz bandwidth is selected, no current is drawn through 414 and
the bandwidth-control PIN diodes (A1 1/A13CR4 and All/A13CR12 on the Bandwidth Filter assemblies) are
off.
The automatic sweep time (AST) is determined by combinations of resistors switched into the current source
circuit by front panel settings. (See the Current Source circuit description.) These resistors are located in blocks
A, F, 0 , and the VIDEO FILTER switch A2S2. The contribution of the RESOLUTION BW occurs in the LC
Resolution Bandwidth Control (block A). Resistors R117, R119, R121, and R122 are switched into the AST
circuit by 4 31, 426, 427, and 428, respectively, when the proper control line is activated. Control lines BW2
through BW4 and the noise measure position of the VIDEO FILTER switch apply + 15V to their respective
control lines. The same lines are used to control sweep times in both crystal and LC modes. Since the same
resistors are used to establish the automatic sweep time for both crystal and LC modes, scaling is necessary. To
scale the sweep time, 424 in block A switches R75 in or out of the AST circuit. During crystal filter operation,
BW5 turns 424 off and removes R75 from the circuit, allowing a longer sweep time.
When an LC filtered bandwidth (1100 kHz) is selected, control line BW5 is pulled to + 15V by the RESOLU-
TION BW switch. This results in four simultaneous changes in the analyzer: the LC poles on the Bandwidth
Filter No. 1 and No. 2 Assemblies A1 1 and A13 are activated, the crystal poles are disabled, the LC bandwidth-
control current is established, and the automatic sweep time is scaled for LC bandwidths.
With + 15V routed to the Bandwidth Filter assemblies by BW5, A1 1/A13Q3, A1 1/A13Q6, A1 1/A13CR8, and
A1 1/A13CR15 are turned off and A1 1/A13CR2 and A1 1/A13CR13 are on. (Refer to Bandwidth'Filter Assem-
bly No. 1 A11, Circuit Description and Schematic.) This blocks any signal from passing through the crystal filter
sections. Transistor 413 (on the Sweep Generator/Bandwidth Control Assembly A9, block D) turns on and
control line BW6 is pulled to - 4V, which further inhibits the crystal filters.
The defeat of the crystal filter poles and the application of bandwidth-control current on the BW7 line activates
the LC filter sections. The LC bandwidth is controlled by the current through BW7 to the Bandwidth Filter
assemblies. Transistor 422, in the LC PIN Driver Buffer (block C), is turned on, allowing the current on BW7
to be controlled by 421. The position of the RESOLUTION BW switch, via BW2 through BW4, turns one of
the transistor switches (426, 427, or 431) in the LC Resolution Bandwidth Control (block A) on. The band-
width-control current on BW7 is now determined by a factory selected resistor, either R116, R118, or R120, and
R85 (LC bandwidth adjustment, block C). If the 100 kHz bandwidth is selected, 422 is turned on, but BW7 is
pulled up to greater than + 10V through R106. The bandwidth-control PIN diodes (A1 1/A13CR3 and A1 l /
A13CRll on the Bandwidth filter assemblies) are reverse biased by BW7.
Automatic sweep time scaling for LC occurs when BW5 turns 424 (block A) on. This switches R75 into the
AST circuit and decreases the sweep time. The effect on the automatic sweep time is determined by the parallel
combination of R75 and the resistor (R117, R119, R121, or R122) selected by the active control line.
SERVICE MODEL 8559A
Video Filter
The video filter comprises control A2R6, RESOLUTION BW switch A2AlS5, and eight capacitors on the
Sweep Generator/Bandwidth Control Assembly A9 (blocks A and B). VIDEO FILTER control A2R6 varies the
resistance of the RC filtering network that it forms with the video filter capacitor. The RESOLUTION BW
setting determines which video filter capacitor will be switched in by the transistor switches (441, 443, Q45,
and 447 in crystal bandwidths, and 454, 432, Q30, and Q55 in LC bandwidths). Increased capacitance is
switched in to provide increased filtering as the bandwidth narrows.
The output of the Xtal PIN Driver Buffer (BW6) is applied to the bases of 442, 444, 446, and 447 via CR18
through CR21. This holds the transistors off and prevents the crystal mode, video filter capacitors from being
switched into the circuit during LC mode operation. It is not necessary to switch the LC mode video filter
capacitors out of the circuit during crystal operation; their values are so much smaller that they are effectively
out of the circuit.
Switch A2S2 applies maximum video filtering for noise measurements by turning on Q55, which switches in
C28.
The Sweep Attenuator circuit attenuates the full span sweep (- 5V to + 5V), before it is applied to the Fre-
quency Control Assembly A7, as a function of the FREQ SPAN/DIV setting. The circuit also varies the
automatic sweep time (AST) as a function of the frequency span. Attenuation takes place in the 1-2-5-10
sequence that results in the FREQ SPAN/DIV control sequence. The circuit has two voltage dividers separated
by U3, the unity gain sweep buffer. The input divider provides divide-by-two and divide-by-five; the output
divider provides divide-by-ten and divide-by-one-hundred.
To select any of the input dividers, + 15V is applied to activate the associated control line. For example, if FS3 is
activated, Q51 and QSO turn on and ground R102 and R73. Resistor R102 becomes part of the AST circuit; R73
forms a divider with R70 that results in the ramp voltage being divided by two. The divided ramp is then applied
to the sweep buffer.
The dividers at the output of the sweep buffer have reversed control-logic. That is, they are normally connected
to + 15V by the FREQ SPAN/DIV switch and open (OV) when selected. Transistor Q19 is a gate to drive 417.
When FS4 and FS5 are connected to + 15V, Q19 is off. As a result, 417 is on and opens a path for the sweep
buffer's output to P1-12. No attenuation takes place. If either FS4 or FS5 opens, Q17 shuts off. When FS4
opens, 416 turns on and a divide-by-ten (R81/R82 +R83) is provided. When FS5 opens, Q15 turns on and
provides a divide-by-one-hundred (R81 + R82/R83).
Automatic sweep is varied as a function of frequency span by transistors 453, Q51, 449, 429, 425, and 423.
Transistor A29 is switched on in narrow spans (<1 MHz/div) when the YIG FM coil is swept. All of these
transistors act as switches connecting resistors from the AST line to ground. This varies the sweep time. (See the
Current Source circuit description.) As the FREQ SPAN/DIV is narrowed, the sweep time is decreased.
Sweep Offset
Transistor 420 in the sweep attenuator (block 0 ) makes it possible to offset the sweep ramp in response to the
position of a start-center (ST-CTR) switch. This capability is not required in the HP 855949. So, the + 15V from
the Motherboard Assembly A16 is applied to 420, holding it off. The circuit is always in the center position.
8104
MODEL 8559A SERVICE
Auto Scan Time (AST) Accuracy: Observe front panel switch positions to help isolate the problem area.
Auto scan time can also be affected by circuits on the Marker Assembly A8 and the VIDEO FILTER control
position. If the AST groblem is band related, the Marker Assembly A8 is the most probable cause. If the AST
problem is bandwidth or scanwidth related, the most probable cause is the Sweep Generator/Bandwidth Con-
trol Assembly A9. The greater the load placed on the AST line, the greater the current demand. The greater the
current demand, the faster the sweep rate.
Failure to Sweep: Check the + 10V (nominal) supply. If it is greater than + 11.5V, the sweep will be inhib-
ited.
If the + 10V (nominal) supply is low, check the Bandwidth Filter No. 1 and No. 2 Assemblies A1 1 and A13 for
a shorted crystal filter pole. Test from All/A13TP2 to ground and A1 1/A13TP5 to ground with an ohmmeter
to locate the possible short.
Begin troubleshooting the sweep generator by determining if the Current Source (block F) is operating and if the
Comparator (block H) will toggle.
The inability to trigger retrace, during the beginning of a sweep, is commonly caused by the failure of U1 or
CR7.
MODEL 8559A SERVICE
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SERVICE MODEL 8559A
1 C OP r,PIP b P TO 79 PKG
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8112
MODEL 8559A SERVICE
The Third Converter Assembly A10 contains a 321.4 MHz amplifier followed by a 321.4 MHz bandpass filter, a
double balanced mixer, a 21.4 MHz IF preamplifier, a flatness compensation amplifier, and a band conversion
loss compensating amplifier. Also included in the Third Converter Assembly A10 are the 35 MHz calibration
oscillator and the 300 MHz third local oscillator. The 321.4 MHz signal from the Second Converter Assembly
A5 is amplified in the 321.4 MHz amplifier and filtered in the 321.4 MHz bandpass filter before being mixed
with the 300 MHz oscillator in the balanced mixer. The output of the mixer is the difference frequency, 21.4
MHz, which is applied to the IF preamplifier where gain is added for the reference level calibration. The signal
now passes through two amplifiers to compensate for flatness across the bands and the varying conversion loss
of the bands before leaving the Third Converter Assembly A10 at a power level of approximately 0 dBm.
The 321.4 MHz Amplifier provides a broad-band fixed gain of approximately 18 dB to the incoming 321.4
MHz IF signal. The amplifier is a single-stage common-emitter transistor amplifier whose gain is determined by
the high frequency characteristics of Q10, the input matching bandpass filter, and the output matching elements
L3 and C8. The 3 dB bandwidth of the input bandpass filter is approximately 500 MHz (with 150 MHz and 650
MHz as the 3 dB points). The filter comprises series capacitor C1, two shunt capacitors, C2, and C3, and series
inductors L1 and L2. This bandpass filter attenuates the first and second LO feedthrough to prevent overload-
ing of the amplifier and to minimize spurious responses. Bias to RF amplifier transistor Q10 is provided by Q9
and R3 through L25. Note that Q9 and associated components are RF decoupled by C6 and C7.
The 321.4 MHz Bandpass Filter rejects the image frequency from the Second Converter Assembly A5 and limits
the signal power applied to the mixer in the Third Converter Assembly A10 to a 3 dB bandwidth of about 9
MHz. The filter consists of four LC resonators that are tap-coupled at the input and output of the filter and
capacitively coupled between sections by traces on the printed circuit board. The center frequencies of the four
poles are adjusted by C9, C10, C11, and C12.
Transistor Q l and associated circuitry form a grounded-base Colpitts oscillator. Direct collector current for Q1
is supplied through L8, whose internal parallel capacitance causes it to self-resonate at 300 MHz. Inductor L12
and capacitors C15, C16, and C17, form a tank circuit that feeds back the collector current of Q1 to its emitter.
The frequency of the tank circuit is selected by tuning L12. Power is tapped out of the tank circuit through C18
and L11 and sent to 42, a buffer amplifier that distributes the power and provides a constant load to the
oscillator.
The 300 MHz buffer amplifier isolates the oscillator from the mixer and provides the high-level signal required
to drive the mixer. The buffer amplifier is a common-emitter amplifier in which R10 and R11 set the emitter
current. Base current is supplied, through self-resonant L9, from R5 and R6. Inductor L13 and capacitor C19
form a matching network that matches the impedance of the signal applied to the mixer's (Ul) LO input. A test
port is provided, through R4 and J1, to monitor frequency and amplitude of the 300 MHz Oscillator (Third
LO). Voltage regulator U2 and its associated circuitry provide a regulated power supply for Q1 and 42.
The Double Balanced Mixer (Ul) mixes the 321.4 MHz second IF from the 321.4 MHz Amplifier with the 300
MHz Oscillator. This produces the sum and difference frequencies, 621.4 MHz and 21.4 MHz, that are sent to
the IF Preamplifier. The 621.4 MHz mixing product is removed by the matching filter at the input of the IF
Preamplifier. Inherent in the double balanced mixer is excellent port-to-port isolation.
SERVICE MODEL 8559A
IF Preamplifier (F)
The IF Preamplifier voltage gain is provided by Q8 in a common-emitter amplifier configuration. Circuit gain is
controlled with collector-to-base feedback through PIN diode CR4. The current through CR4 is adjusted from
the front panel by the REF LEVEL CAL control and can vary the gain of the IF Preamplifier over a 10 dB
range. Transistor 4 7 functions as an emitter follower buffer amplifier.
The flatness voltage from the Step Gain Assembly A12 sets the base voltage of 43. Resistors R41, R42, R43,
and diode CR5 establish the emitter current and cause it to vary non-linearly in response to changes in the base
voltage. This non-linear current drives CRl and enables the gain of the Flatness Compensation Amplifier to be
proportional to the base voltage (and flatness voltage) at about 0.4V per dB of gain.
The Band Conversion Loss Compensating Amplifier changes gain in discrete steps to compensate for the
changes in conversion Ioss associated with RF section harmonic band switching. In the fundamental mixing
bands (Bands 1 and 2), the circuit has unity gain. During second harmonic mixing (Bands 3 and 4), CR2 is
forward biased, allowing the gain to be set by R34 as shown in the following equation: Gain = 1 + R32/R34.
In the third harmonic mixing mode (Bands 5 and 6), CR3 is forward biased and R36 establishes the gain as
follows: Gain = 1 + R32/R36. See Figure 8-41 for a simplified schematic of the Band Conversion Loss
Compensating Amplifier gain switching. A gain-versus-band table is shown on the Third Converter Assembly
A10 schematic below function block I.
The 35 MHz Calibration Oscillator consists of a differential amplifier formed by Q l l and 412. A frequency
determining tank circuit (L21, C45, and C46) is connected to the base of Q11. The base of 412 and one side of
the tank are at RF ground due to C48. Capacitor C45 temperature-compensatesthe oscillator; R13 controls the
bias current and output amplitude. As the base voltage of Q11 increases, the voltage at the emitters of Q11 and
412 increases. Since the base of 412 is effectively at signal ground, the increase in voltage at its emitter reverse
biases its emitter-base junction, shutting 412 off. As 412 shuts off, the voltage at its collector increases and is
fed back in phase to the tank at the base of Q11 through C47. The output is taken from the collector of Q11,
filtered to lower harmonic content, and sent to the CAL OUTPUT connector on the front panel.
Three supply voltages power the Third Converter Assembly A10: + 15 VF, - 10V, and - 10.6 VF. The + 15 VF
is derived from the + 15V supply line and is filtered as it enters the board. The - 10V and the - 10.6 VF
originate from the - 12.6V supply line. After filtering, the - 12.6V supply feeds a shunt regulator comprising
R48, C53, VR1, and VR2 and develops the - 10V supply. The filtered - 12.6V supply also feeds three-terminal
regulator U2, which develops the - 10.6 VF supply. Regulator U2 improves isolation of the 300 MHz Oscillator
from the supply lines and reduces spurs caused by oscillator harmonics.
Spring contacts are used on the circuit board to ground portions of the
circuitry to the aluminum extrusion walls. Care is required when removing
the circuit board to prevent damaging these springs. The circuit board must
be installed in the extrusion before attempting to adjust the 321.4 MHz
Bandpass Filter (block C).
Low Gain: Most common failures are: CR1, CR4, the PIN diodes in the IF preamplifier, and the Flatness
Compensation Amplifier.
300 MHz Oscillator off F~equency: Most common failures are C16, C17, and C18.
35 MHz Oscillator off Frequency: Most common failures are C45 and L21.
MODEL 8559A SERVICE
Reference HP Part
Designation Number Description Mfr Part Number
A1 0
h10L1
4 1 lr,'
A 1 0C3
A 1 11 4
A l OC5
AI Or61
4 1 IlC7
AI n r c
A 1 OC9
A 1 lri 3
AIPCll
n i lnr 1 .I
A1 0 C l 3
nior 14
A 1 0C15
n1ns 1 6
& I 0C17
n i n r l n
A1 llC19
A 1 Or 2 3
A I OC21
PI1 1 r 7 ?
A 1 llC2 3
A1 Ilr?4
A 1 OC??
AI n r p t ,
A I IlC27
A 1 1r::l
AI o c 2 9
A1 1 1 7 1
AIOC31
A I 1:r
A l IlC33
n i n s 39
A 1 OC35
n i lr- r o
A1 nc37
n i ,lr 3 0
A l IlC3'?
ninrq?
A 1 OC41
AI [IT 47
A 1 OL43
A 1 0S 3 4
a 1 OC45
A1 0C4h
A 1 0C47
A 1 OT4O
A 1 0C49
A10C50
A101'51
A 1 8C.W
A 1 0C53
A1 9C54
A 1 OC55
A13C56
A 1 0C57
AIUC50
A 1 OC59 CAPACITOR- FXD 1 5 I I F i - 1 0 2 20VDC TA
A1OEl CORE- S M I E L ~ D I N GW A D
AlDE2
A 10E3
A 1 OE4
A l OL6
A1 '11 7
A I llL8
A1 l l 9
A l OLIO
A11111
A1 CLIP
A 1 ll 1 i
A10L14
A 1 0 I l',
AIOI 16
A111 1 7
A1 O L l 0
AllLlr?
A 1 OL20
A 1 01 7 1
A1 l l L 2 T
AIOLT'l
A 1 OL?4
A171 :',
A101 2 6
A1 0 L 7 7
AlOP1
A1 llO2 lRCN?T'il(tR NPN 'is TO 7 ' ) ?I> tW r l = F l O t l t l : l 7
A1 043 TRANST?TOR NPN $1 TO 1 0 P D 3bOnW
~ 1 3 n 4 lRFhSlr>lllR NPN 'il 1 0 72 PD :'03PW
A1085 TRANCJ9TOR PNP T N 3 7 5 1 ST TO 1 8 PD 3hOHW
A1 ! I n 6
A1 087
a1 .In0
A 1 0Q9
A10013
A 1 OR1
A1 OR?
A 1 OR3
A1 JR4
A 1 OR5
nl J n z l
A 1 OR42
A t 0R4 1
A L OR44
A 1 3R4'1
A L OR46
~llJR17
A 1 OR48
OlJR19
A l OR50
hl l R V
A 1 OR52
A 1 1R"r 3
Al(llI'1
n t nrlz
ALOTP 3
n t n l r ?
Al0lll
A 1 1112
RLOWl
AlOMPl OSCILLATOR S H I E L D
AlOMP2 GROUND LUG
AlOMP3 COVER T H I R D C O N V E R T E R
AlOMP4 STRIP, S H I E L DIN G
AlOMP5 CONTACT FINGER
MODEL 8559A SERVICE
FLATNESS
COMPENSATION
AMPLIFIER
I
NON-LINEAR
A10
THIRD CONVERTER ASSEMBLY
AlOWl
321.4 MHz
IF IN
@
321.4 MHz
BPF
ADJUST
'Q
C46
CAL FRED
300 MHz
LO OUT
(TEST CONNECTOR)
0
L12
LO ADJ \
BANDWIDTH FILTERS No. 1 and No. 2 ASSEMBLIES A l l and A13, CIRCUIT DESCRIPTION
Bandwidth Filters No. 1 and No. 2 Assemblies A l l and A13 are identical except for some off-board connec-
tions. Bandwidth Filter No. 1 Assembly A1 1 is described here. Bandwidth Filter No. 1 Assembly A1 1 operates
at 21.4 MHz with a variable bandwidth of 3 MHz to 1 kHz. The RESOLUTION BW switch selects one of the
following eight available bandwidths: 3 MHz, 1 MHz, 300 kHz, 100 kHz, 30 kHz, 10 kHz, 3 kHz, or 1 kHz.
Four stages of filtering are used for all eight bandwidths; each assembly contains two stages. The bandwidths
from 30 kHz to 1 kHz are obtained from synchronously-tuned crystal filters. The remaining four bandwidths
(100 kHz to 3 MHz) use synchronously-tuned LC tank circuits. The four crystal filter stages contain factory
selected and matched crystals (AllYl, A1 1Y2, A13Y1, and A13Y2) that must be replaced as a set. If replace-
ment of a bandwidth filter assembly is necessary, the new assembly is shipped with two crystals installed and
two packaged separately to replace the crystals on the other assembly. In addition to the filter stages, each board
contains a 10 dB Buffer Amplifier, a Unity Gain Buffer Amplifier, and an Output Buffer Amplifier.
- - -
R 1 ~
GAIN I N dB - 20 LOG li +
R5tR6tR7
-
R3
1
GAIN - 2.73
GAIN I N dB - = 8.7548
nYo current paths are used for dc bias in the input buffer amplifier, one for crystal filter poles, another for LC
filter poles. When a crystal filtered bandwidth (530 kHz) is selected, 4 3 (block D) and Q1 are the sources for
the current through 4 2 (see Figure 8-46). The base voltage of 4 2 is fixed by the divider R9 and R10, while the
W 6 rnA DC BlAS
I N BLOCK D
-
~4 mA DC BlAS
emitter is fixed by R8. The collector, therefore, becomes a constant-current sink for 20 rnA of current supplied
by Q1 and 43. A decrease in the current supplied by 4 3 results in increased current through Q1, keeping the
current through 4 2 constant. If an LC filtered bandwidth is selected, BW5F (filtered bandwidth control line 5
in block C) supplies current via CR1 and R13 (see Figure 8-47); 4 3 is effectively removed from the circuit.
To understand how 4 3 functions during crystal filtering modes, a new model is needed. (See Figure 8-48.)
Resistor R7 has been omitted to simplify the model. The emitter load of 4 3 (RJ is the series combination of the
internal resistance of Y1 (RJand a resistance determined by the bandwidth selected (see First Xtal Pole descrip-
tion). The crystal's series resistance at resonance (RJ is constant at about 10 ohms. In the 30 kHz bandwidth,
R23* is in series with k.Since R23* is very large by comparison, it represents the total load on 4 3 (RJ. When
R23* is substituted into the gain equation for R,, a gain of 2.7 (8.6 dB) results. This is roughly equal to the gain
without 4 3 in the circuit. In fact, the larger R,becomes, the closer the gains become.
Q lOdB INPUT
BUFFER AMPLIFIER
01,02 it -
R5tR6
R3
OAIN-
1- -
At
FOR 3 0 ~BW:
When: ~ t - 8 2 5 0n
I
R5
T -,R6
R3 FEEDBACK
I Then: OAIN-
185.7
110
23.7 - 2 . 8 9 OAIN 2 . 7 0 = B.6dB
4' 0
1- -
82.50
. 1 - 1 1
FOR i K BW:
When: Rt-70 a
Then: OAIN- 8' -
2..€ia-'.O = 12dB
When the 1 kHz bandwidth is selected, CR4 is biased on and has a resistance of about 60 ohms. This resistance
forms a voltage divider with R,that results in signal amplitude loss across the crystal. Increased gain in the input
buffer amplifier, caused by the load on 43, compensates for these losses. The gain increase occurs when the
reduction in R, turns 4 3 on even harder, resulting in some of the feedback from R6 being shunted to ground
through the collector of 43. This reduction in negative feedback increases the gain of the input buffer amplifier.
By substituting into the gain formula the 1 kHz bandwidth R,(10 + 60 = 70 ohms), a new gain of 4.0 (12 dB) is
derived.
First Xtal Pole (D)
Crystal filtering is used for bandwidths of 1 kHz, 3 kHz, 10 kHz, and 30 kHz. Individual poles have a band-
width about 2.3 times the selected bandwidth, and each filter board assembly (two poles combined) has a
bandwidth of about 1.5 times the selected bandwidth. For example, when the 1 kHz bandwidth is selected, each
pole has a 3 dB bandwidth of about 2.3 kHz, each assembly a bandwidth of 1.5 kHz. The signal from the input
buffer amplifier is routed to 4 3 and to compensation amplifier 44. (The action of 4 3 is discussed in the 10 dB
Input Buffer Amplifier description.) From 4 3 the signal is applied to the crystal (Yl), where it is filtered before
going to the unity gain buffer amplifier.
The crystal functions as a series-resonant filter tuned to 21.4 MHz. An equivalent circuit is shown in Figure
8-49. Parallel capacitance C, is the result of terminal and case capacitances in the crystal; R, is the effective
resistance at resonance (about 10 ohms). Both C, and R, are detrimental to the pole's performance, so
compensation is used to nullify their effects. Because they are cancelled, C, and R, are not shown in the
simplified crystal pole schematic.
Pin diode CR4 (see Figure 8-50) controls the filter's bandwidth by functioning as a variable resistance at 21.4
MHz. The voltage applied to BW6F controls the current through CR4 and its resistance. An increase in current
decreases the resistance and narrows the bandpass.
The crystal presents a low impedance (R,)to the signal at resonance, hence signal voltage is developed across
CR4. As the signal frequency varies from the center frequency (21.4 MHz), the impedance of the crystal
increases, making it part of a voltage divider with CR4 and causing more signal voltage to be developed across
the crystal. The frequencies at which crystal impedance and PIN diode resistance become equal are the 3 dB
points of the bandpass. Varying the PIN diode resistance, therefore, varies the bandwidth.
The case capacitance of the crystal (C,) would cause a second resonant point, or dip, in the bandpass if
compensation were not used to nullify its effects. Compensation is provided by 4 4 as a current equal to and
opposite in phase with the current flowing through C,, as shown in Figure 8-51. Capacitor C15 (SYM) adjusts
the phase of the compensating current.
T0
UNITY GAIN
BUFFER AMP
TOIFROM
10 dB INPUT
BUFFER AMP
The input capacitance of the unity gain buffer, the trace capacitances, and the capacitance of the PIN diode
add, causing the center frequency of the filter to be altered. Compensation is used to eliminate this effect. These
capacitances are tuned out by including them in a parallel resonant circuit (at 21.4 MHz) formed with L7 and
fine tuned by C25 (CTR). Adjusting C25 tunes the circuit to present a high impedance at resonance.
When LC filtering is selected, BW5F forward biases CR2, effectively grounding the emitter of 43. During
crystal filtering, CR2 is reverse biased.
A simplified model of the LC pole is shown in Figure 8-52. At resonance, a voltage divider is formed between
CR3 and the resonant circuit. The 3 dB points of the bandpass occur when the PIN resistance and the impe-
dance of the resonant circuit are equal. Varying the PIN resistance varies the filter's 3 dB points. The higher the
PIN resistance, the narrower the bandwidth. When the 100 kHz bandwidth is selected, CR3 is reverse biased
and R19* sets the bandwidth; if one of the other bandwidths is selected, the parallel combination of R19* and
CR3 is utilized. The intrinsic capacitance of PIN diode CR3 affects the bandpass, if not compensated for.
Adjustable capacitance C73 (LC DIP) and L5 are in parallel with the PIN capacitance and allow it to be tuned
out of the circuit.
MODEL 8559A SERVICE
A simplified schematic of the first LC pole is shown in Figure 8-53. The fundamental frequency-determining
components are L6 and the center-tapped capacitance C16* and C20*. Positive feedback is applied to the center-
tap at 21.4 MHz to compensate for losses in the tank circuit. The application of feedback makes it important
that C16* and C20* be about the same value for proper pole operation. The level of the feedback is controlled
by CR5, acting as a variable resistance. LC feedback control R26 establishes the current through CR5 and its
resistance.
1 C 8 ' t 2 3 + /
ci6* R25
(FEEDBACK) R24
t V F BIAS
When an LC filtered bandwidth is selected, BW5F is at + 15V; BW7F is at a voltage greater than or equal to
+ 6.8V and supplies bandwidth-determining bias current to CR3. Supply line + VF BIAS is always at + 6.8V
Control line BWSF reverse biases CR8 (block B), disabling the crystal pole, and forward biases CR1 (block B),
opening the dc bias path to 4 2 (see Figure 8-47). During LC operation, CR6 is reverse biased, keeping C28 out
of the circuit. When a crystal filtered bandwidth is selected, BWSF forward biases CR6 and allows C28 to
ground the signal path.
Operation of the Unity Gain Buffer Amplifier is similar to the 10 dB Input Buffer Amplifier, except that it has
an FET input (Q5) and unity gain. The input signal path is activated by the BWSF line, which switches on CR9
(during LC mode) or CR8 (during crystal mode).
When the crystal mode is selected, the current through the input FET (Q5) is determined by 4 6 and constant
current sink 4 7 (which sinks about 4 mA). During LC mode, current is supplied through R37 and CRlO from
BWSE The input FET current is a good indication of the stage's operation and can be monitored by measuring
the gate-to-source voltage. This voltage should be between + 0.2V and + 1.W (an increase in current decreases
the voltage).
Capacitor C68 and L19 form a feedback circuit that tunes Q7 to 21.4 MHz. Trimmer Resistor R31 (XTL
FEEDBACK) adjusts the feedback and controls the stage gain as did R5 and R6 in block B.
SERVICE MODEL 8559A
I,,, = Vb,(Q10)/R53
Which becomes:
The total current through Q9 and Q10 is set by R54. The input signal path is selected by either CR15 (during
crystal mode) or CR16 (during LC mode).
Observe front panel switch positions in relation to the problem to isolate the area of the failure.
Check for leaky diodes and capacitors. Loading of the signal path can alter either a pole's gain or bandpass
shape or both.
Isolate crystal poles from LC poles to prevent interaction of failure symptoms. Isolation of the crystal poles
from the circuit is best achieved by removing CR8 and CRl5 (blocks D and G). Isolation of the LC poles is best
achieved by removing CR9 and CR16 (blocks C and F).
MODEL 8559A SERVICE
A l l C27
A1 lC28
~11rz9
A1 lC30
hl l C 3 l
D I O D F S W I T C H I N G 70'4 7 5 K A I O N S
D I O D E - S W I T C M I N C 2 0 U 75MA I O N S
DIODE PIN I l O V
DIODF PIN l l O U
DIODC P I N 1 l O V
MODEL 8559A SERVICE
A l l MISCELLANEOUS PARTS
I I
--J
BY8 [CRYSTAL BANOYIOTH CONTROL)
BY7
--
[LC BANOYIOTH CONTROL)
--
FIGURE 8-54. BANDWIDTH FILTER NO. 1 ASSEMBLY A1 1, BLOCK DIAGRAM
MODEL 8559A SERVICE
The Step Gain Assembly A12 provides from 0 to 50 dB amplification of the 21.4 MHz IF in 10 dB steps, as
selected from the REFERENCE LEVEL control. A zero to - 12 dB REFERENCE LEVEL FINE attenuator
control is also included on the front panel. Generated on the Step Gain Assembly A12 are the first mixer diode
bias and a flatness control voltage proportional to the sweep plus tune (S + T) voltage.
There are three step gain amplifiers, one 10 dB and two 20 dB, cascaded as shown in the schematic diagram.
Full gain of any amplifier is selected by grounding the appropriate IFG line. The three step gain amplifiers can
be considered as operational amplifiers. An equivalent circuit for the three stages is shown in Figure 8-57. The
gain for each amplifier is: Gain = 1 + R,/R,. The feedback resistance, R,, for the 10 dB amplifier is R8, 562
ohms; for the 20 dB amplifiers it is R23 and R31, each 750 ohms. The input resistance, R,, is a combination of a
fixed series resistance (56.2 ohms) and the controlled resistance of the PIN diodes. The resistance of the PIN
diodes is approximately 10 to 1000 ohms and increases as the forward bias current is decreased from 100
milliamperes to 1 microampere. The input resistance, R,,for the 10 dB amplifier is approximately 260 ohms; for
the 20 dB amplifiers, it is about 83 ohms.
Selection of the correct combination of step gain amplifiers is accomplished with the REFERENCE LEVEL
switch. Rotating the switch grounds the emitter circuit of the selected amplifier (or amplifiers), allowing current
to flow through the PIN di8de (or diodes). The possible switch combinations allow the gain to vary from unity
(all switches open) to 50 dB maximum with all three emitter circuits grounded.
TestINorm Switch. In the emitter paths of the 20 dB step gain amplifiers are the TEST/NORM switches
used to disable both 20 dB amplifiers during log amplifier adjustment.
0-12dBControl (H)
The REFERENCE LEVEL FINE control provides approximately 0.3 to 12.3 dB of attenuation at the base of
4 6 in the 0- 12 dB control circuit. By regulating the current flow through PIN diode CR7, the amount of signal
attenuation is controlled. For example, if PIN diode current flow is increased, more RF signal is shunted or
bypassed to ground. Capacitor C23 provides the RF ground path.
A minimum current flow through the PIN diode, which provides the maximum allowable diode resistance, is
established by - 12 dB potentiometer R39 so that the diode is never completely cut off. Adjustment of R39 sets
the 0.3 dB point and is adjusted with the REFERENCE LEVEL FINE control set fully clockwise (- 12 posi-
tion).
8143
SERVICE MODEL8559A
The maximum current flow through the PIN diode is set with the 0 dB potentiometer R35. Resistor R35 is
adjusted to the 12.3 dB attenuation point with the REFERENCE LEVEL FINE control set fully counterclock-
wise (0 position).
Transistors Q5 and 4 7 are identical current sources. The maximum current is set with the 0 dB adjustment, R35,
in the common base circuit. Diode CR5 provides temperature compensation for the transistors.
Transistor Q5 provides current for a bias voltage applied to the anode of the PIN diode. The voltage source
consists of R39, R38, and CR6. Diode CR6 provides temperature compensation for the PIN diode. Inductor
L8 isolates the diode current source from the RF signal.
Transistor 4 7 provides current for a variable voltage source at the cathode of PIN diode CR7. Fixed resistor
R40 is effectively in parallel with the negative side (- 12.6V) of the REFERENCE LEVEL FINE control
potentiometer. Its purpose is to match the FINE control to changes in the PIN diode resistance. The FINE
control varies the voltage at the PIN diode cathode, this varies the diode current flow. When the FINE control
is fully clockwise, the PIN diode is at minimum conduction and maximum signal is applied to the base of 46.
Conversely, when the FINE control is fully counterclockwise, the PIN diode is forward biased into maximum
conduction and minimum signal is applied to 46. Buffer amplifier 4 6 operates as an emitter follower, providing
isolation between the 0 - 12 dB control circuit and the 21.4 MHz bandpass filter.
The 21.4 MHz Bandpass Filter at the output of the 0- 12 dB control circuit is a two-pole type used to reduce the
out-of-band noise produced by the step gain amplifiers and 0 - 12 dB control.
NOTE
For minimum step gain error, the ground plane on the Step Gain Assembly
A12 must be firmly connected to the chassis extrusion and the Motherboard
Assembly A16 common ground. This means that before you can make any
step gain measurements or adjustments, the Step Gain Assembly A12 must
be fully seated in its connector socket and all of its cover screws must be in
place and tightened. You can, however, leave the gold secondary cover off
for these measurements.
Band select decoder U3 is a 4-to-10 line decoder. It decodes the three band-select lines (H2, H3, and PM) to
select one of six output lines. The selected line goes low while the remaining five lines stay high. The status of the
decoder's outputs controls the tilt, offset, and bias circuits.
Band tilt is controlled with a variable, voltage-controlled voltage source comprising operational amplifier U4b,
current boosting transistor 42, and related adjustable resistor networks. The signal input to this circuit is the
sweep plus tune (S + T) voltage. Normally, this signal is a ramp extending from + 1.2V to + 4.8V or some level
in between, depending on the position of the FREQ SPAN/DIV and frequency TUNING controls.
When the S + T ramp is at its low point (+ 1.2V), the level at test point 3 should be + 10.6V + 0.1V When the
S + T ramp is at its peak (+ 4.8V), the level at test point 3 can be adjusted from about + 9.6V to + 10.9V with
the circuits's potentiometers and factory selected fixed resistors. Potentiometers R47, R48, R49, R51, R53, and
R55 adjust the overall tilt for each band. Ttvo factory selected resistors, R5O and R52, and potentiometers R54
and R56 provide additional tilt adjustment for harmonic mixing bands 2 + , 2 - , 3 + , and 3 - after a break-
point at approximately midband.
MODEL 8559A SERVICE
Operational amplifiers U4a, U4d, U4c, and their associated circuits provide offset and gain for the tilt voltage.
Potentiometers R57, R58, R59, R60, R61, and R62 are used to adjust the offset of each band. A fixed negative
offset is provided for all bands by operational amplifier U4c. The resulting flatness output voltage is applied to
a voltage-controlled amplifier on Third Converter Assembly AlO.
The four switches in U1 are normally closed, but the individual switches open when selected by a logic-high
control voltage. Since the outputs from the band select decoder U3 are all high except one, the normal status of
the switches in U1 is open until a low control input allows one to close. The switch then connects one of the
three potentiometers (R70, R71, R72) through a factory selected fixed resistor to the positive input (pin 10) of
operational amplifier U2c, forming a voltage source at that point. The table below shows which potentiometers
and factory selected resistors apply to which band.
.01-3 V1 R7 2 R7 3
6-9 V1 R7 2 R7 3
3-9 V2- R83 R84
9-1 5 V2+ R87 R88
6-15 V3- R7 1 R74
12.1-21 V3+ R7 0 R7 5
Operational amplifier U2c forms a negative impedance converter that increases or decreases bias as needed to
maintain a constant angle of conduction at the first mixer. This is necessary to maintain a constant insertion loss
through the first mixer. Operational amplifier U2c is connected to the voltage source at the junction of R73,
R74, R75, and Q1. This circuit multiplies its input source resistance by approximately - 1/110, thus converting
the input voltage source and series resistance into an equivalent voltage source and negative impedance (here,
approximately - 1000ohms).
Because of this conversion, as current increases in the circuit, the resultant output voltage decreases, just as it
would if a negative resistance value (- R) were substituted for R in the familiar expression for Ohm's Law. The
expression would then be rewritten as: E = I(- R). Notice now that an increase in current (I) results in a
decrease in voltage (E). This is the equivalent action of this circuit. If all of Ul's switches are open (as in band
2- or 2+), transistor Q1 forces the junction positive, turning off CR15 and thereby removing the negative
impedance converter from the bias output at P1-24. One of the other operational amplifiers in U2 is activated,
providing voltage sources and positive resistances to the bias output (TPl or PI-24). When one of the opera-
tional amplifiers is selected, the diodes at the outputs of the other two are reverse biased, and disconnect the
outputs from PI-24.
8145
SERVICE MODEL 8559A
Transistor 4 4 and its associated circuitry operate off the + 15V supply to furnish a regulated + 5.1V reference
for the flatness and mixer diode bias circuit.
Always check the supply voltages. If the + 15V supply drops (even slightly), the + 5.1V Reference becomes
unregulated.
Linear or Log Fidelity Errors: First readjust REFERENCE LEVEL FINE to the - 12 dBm position and
test again. If the problem is not present, gain compression may be occurring in one of the circuit's amplifiers.
The 10 dB Amplifier (block E) is the most probable source, and improper biasing of CRl is the most probable
cause. Insufficient dc biasing of CR1 allows signal voltage to vary the bias, causing the stage gain to vary as the
signal level varies. Diode CRl, not transistor saturation, is the most common cause of compression.
Reduction of the losses in the 0 - 12 dB Control (block H) allows the first amplifier stage to operate at a lower
input level, thus reducing compression. To decrease the losses, hand-select CR7 and C23 for minimum circuit
loss.
CAPACITOR FXD
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SERVICE
MODEL 8559A
A12 STEP G A I N
0- 12 dB CONTROL
REF LEVEL WP \
1
REF LEVEL CY
I 21.4
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10 dB
AMPLIFIER
20 dB
AMPLIFIER
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9 0 0 9
Bandwidth Filter No. 2 Assembly A13 is very similar to Bandwidth Filter No. 1 Assembly A11, and correspond-
ing components have the same reference designators. The differences between the two assemblies are in the TO/
FROM designations listed on the schematic diagrams. Refer to the Bandwidth Filter No. 1 Assembly A1 1
circuit description for complete information on circuit operation.
SERVICE MODEL 8559A
I Reference
Designation
HP Part
Number Description Mfr Part Number
RESISTOR 6 8 1 1 % ,125W F T C - 0 1 - 1 0 0
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MODEL 8559A SERVICE
I I
BY5 (POLE SELECTION)
BY6
I
BY6 (CRYSTAL BANOYIOTH CONTROL)
BY7 (LC BANOYIOTH CONTROL]
0 0 - 9 9 0 -.I
FIGURE 6-61. BANDWIDTH FILTER NO. 2 ASSEMBLY Al3, BLOCK DIAGRAM
MODEL 8559A SERVICE
The Log Amplifier Assembly A14 includes seven amplifier stages, each capable of providing linear and loga-
rithmic amplification. A detector circuit following the amplifier stages detect.7 the amplified 21.4 MHz IF
signal, producing the vertical display signal. The offset circuit that follows the detector operates in Log mode to
offset the vertical display signal in 100 mV steps. This steps the display in four 10-dB increments of apparent
gain and adds the last 40 dB of displayed step gain to the gain (50 dB) already provided in the IF section.
AmplifierStages(Istthrough7th) (A) (C) (D) (E) (F) (G) (H)
The seven amplifier stages are similar in operation. Different stages are selected as linear or log amplifiers,
depending on the setting of the Amplitude Scale switch.
Log Mode of Operation. In Log mode, the gain of the seven amplifier stages is sequentially limited as the
signal level increases. Limiting starts with stage seven, since it sees the combined gains of the other stages, and
continues sequentially as the signal level increases. Stage one is the last stage to begin limiting the signal. The
total limiting process provides 70 dB of log display range. Each stage consists of an emitter follower voltage-
driver and a common-base amplifier in which the gain is signal-level dependent. Increases in signal level
decrease the gain.
A simplified schematic of a typical log stage (the second stage) is shown in Figure 8-64. In Log mode, the LOG/
LIN control line is high (about + 15V); 424 is on, forward biasing diodes CRlO and CRll and the log diodes in
all of the other stages. Diodes CRlO and CRll are Schottky diodes with a forward bias voltage of approxi-
mately 0.4V Emitter follower 413 is a voltage source that develops signal current flow through CRlO and
CRl 1. This signal-current drives 420, a common-base amplifier tuned to approximately 21.4 MHz. The gain of
this amplifier is set by the ratio of R52 to the total resistance, R,, between the emitters of 413 and 420
(primarily the resistance of CRlO and CR1 I). The formula for computing the gain in dB is:
Gain (dB) = 20LOG(1 + R52/RT)
/ SECOND STAGE \
C6
.Ol
Y
I
+15V
LOG/LIN
CONTROL L I N E
Resistance R, is at a minimum (approximately 150 ohms) for small signals. The small signal gain of the stage
(about 10 dB) is established by the dc bias through the log diodes. As the signal level at the emitter of 413
increases, signal current cancels bias current in the log diodes, increasing R,. The gain of the stage for large
signals is reduced to unity (0 dB) as R, becomes very large.
Linear Mode of Operation. Two simplified schematics illustrating unity and 10 dB gain of a typical linear
stage are shown in Figures 8-65 and 8-66. In linear mode, the signal level dependent components are removed
from the signal path and a linear display is provided. The - 8 VT is applied to the base of 424, turning it off.
This removes dc bias from CRlO and CRll. Total resistance R, (primarily the resistance of R56 and CR12) is
high, since CR12 is reverse-biased. Control line IFG6 is high and the stage gain is near unity. The signal flow is
through emitter follower 413 and R52, to 420. In stages six and seven, an alternate signal path is used to fix the
gain at about 5 dB per stage, allowing for scale differences between Log and Lin modes. Both stages are
activated by the - 8 VT from the Amplitude Scale switch through R34, R93, R101, CR25, and CR28. The
combined stage gain is adjusted by R34 (LIN), which controls the dc PIN diode bias.
/ SECOND STAGE \
OUT
Stage 2, 3,4, and 5 each have an alternate signal path that switches in 10 dB of step gain for a total of 40 dB.
The alternate path is selected by the REFERENCE LEVEL control. With the INPUT ATTEN at 0 dB and the
REFERENCE LEVEL control at -68 dBm, the - 8 VT is routed, via the IF gain control line (IFG4), to
forward bias CR22 in stage 5. For each stepped increase in the REFERENCE LEVEL control, the - 8 VT
activates the IFG lines associated with the stages of gain required, forward biasing the diodes in the signal path.
Each IFG line has a potentiometer (block B) that controls the line's bias current and the stage gain. Note that
IFG6 controls two stages (stages 2 and 3) that, when switched in, provide 20 dB of gain.
SECOND STAGE \
/
i1iV
i1lV
A- - C FEEDBACK P I T H 1, .
-1OdB
ADJUST
collector of 424 goes to - 8 VT, turning the log diodes on. In Lin mode, the LOG/LIN line is at - 8 VT, 424 is
turned off and current flows through R34 (LIN) to stages 6 and 7.
In Lin mode, when approximately 700 mV rms (+ 10 dBm) is applied to the input of the Log amplifier, the
voltage at the output of stage 7 (TP5) is about 1.5 rms. With the same input in Log mode, the output at TP5 is
about 2.OV rms. To maintain an equal relationship with maximum input signal (the trace at top display), the
output in Log mode must be attenuated. This attenuation is achieved with variable gain amplifier 47, the gain
of which is determined by the ratio of its collector load to its emitter load.
In Lin mode, the LOG/LIN line is a - 8 VT, CR4 is forward biased, and the output of U2b (TP1) is approxi-
mately + 1 5 1 Diode CR29 is reverse biased and the gain of the variable gain amplifier is R104/R105 (100/316)
or approximately 0.3. In Log mode, the LOG/LIN line is at + 15V, CR4 is reverse biased, and the output of
U2b (TPI) is about -0.45V. Diode CR29 is forward biased and exhibits an ac resistance of about 100 ohms.
This resistance is in parallel with the 100 ohms of R104 for a total of 50 ohms. Since the collector load of 4 7 is
about 50 ohms, the gain becomes 0.15 (50/316). This gain depends upon the resistance of CR29, which is
established by SLOPE adjustment R23.
Detector (K)
The detector comprises a voltage-to-current converter, a half-wave rectifier, and a low-pass filter. The output of
the variable gain amplifier is applied to 46, where voltage variations are converted to current variations.
Transistor Q5 acts as a current driver for half-wave rectifier 44, while CRl biases 4 4 just below cutoff. When
the signal is positive going, 4 4 conducts; during the negative half-cycle, Q4 is cutoff. The detector's output goes
to the low-pass filter, a series of pi-section filters that smooth the detector's output and remove RF signal
components.
SERVICE MODEL 8559A
C 4 1 / 0 - T 0 If,?.' F
C4 1/0 TO-1033 F
R F S I G T O R 2.37K 1% .125W F T C = O + - 1 0 0
A 1 4 MISCF-LLANEOUS P A R T S
COVER, LOG A M P L I F I E R
MODEL 8559A SERVICE
I LO6 MODE
TEWPERATURE
I
LO6 CONTROLLEO
I AMPLIFIER ATTENUATOR DETECTOR
I BAIN
b
CONTROL
LINES
IF65 IF65 1-
IF68 IF68
",6/LIN
POWER SUPPLY
) C
The Vertical Driving/Blanking Assembly A15 contains a preamplifier to amplify the detected and filtered video
received from the Log Amplifier Assembly A14. It also supplies the video signal needed to trigger the sweep
generator in the video trigger mode. Following the preamplifier is the vertical driver, a differential amplifier that
drives the vertical deflection plates in push-pull. Blanking, penlift, retrace, and sweep indicator signals are also
supplied by the Vertical Driving/Blanking Assembly A15.
Preamplifier (A)
The detected and filtered video (0 to 800 mV) from the Log Amplifier Assembly A14 is applied to the gate of
Q17a. Transistors 4 1 7 (both sections), Q l l , 412, and 4 1 8 form an FET input differential amplifier; the gate of
Q17a is the noninverting input and the gate of Q17b is the inverting input. The amplifier's output, at the emitter
of 418, is fed back to the inverting input (Q17b) through a voltage divider (R11, R12, and R13). A simplified
preamplifier circuit diagram is shown in Figure 8-70. The voltage gain can be expressed as a function of these
resistor values: Gain = 1 + Rl l/R12 + R13. The circuit's gain is 10. Since the limit to the input voltage is 800
mV, the maximum voltage at the output of 4 1 8 (TP3) is 8V. This voltage is coupled through R17 and becomes
the trigger voltage for the video trigger mode (VIDEO position). Transistor array section U2d and transistor
4 1 3 are temperature-compensated current sources. These bias the differential amplifier (U2a, U2b, and Q20)
that provides isolation between the preamplifier and the vertical driver. The preamplifier output is sent via R40
to the rear panel (AUX VERT OUTPUT, P 1 pin 14).
Since the vertical driver deflection sensitivity is 800 mV, for full-scale deflection, a divide-by-ten circuit and an
offset circuit are used to obtain the correct signal amplitude. With the LOG/LIN switch (A2AlA2) in either the
10 dB per division or linear position, + 15V is applied to the EXPAND line. This reverse biases CRl and turns
Q19 on, dividing the preamplifier's output by 10. Diode CR2 is forward biased and diode CR3 is reverse biased.
Transistor Q19, R18, and R20 form the output divider network. When 1 dB per division is selected, the
EXPAND line is open and Q19 is biased off by CR1 and R22, disabling the divide-by-ten circuit. The full
preamplifier voltage is now available at the output of 4 1 8 and must be offset + 7.2V to display the 800 mV
signal peak. This in effect expands the display.
The offset of the signal is accomplished by a circuit comprised of U2c, CR3, CR4, and R18. Transistor array
section U2c forms an adjustable current source that draws current through CR3 and R18. The 1 dB offset
control is used to set the voltage drop across R18 at + 7.2V This voltage shifts the signal negatively as it passes
through R18. Diode CR4, becomes forward biased as the offset signal goes below - 0.6V and acts to clamp the
minimum output at that level.
SERVICE MODEL 8559A
Beamfinder
With 1 dB per division selected, the baseline is off-screen. Without a visible signal present, there is no displayed
trace. This condition could be misinterpreted as a display malfunction. On an H P 180 series mainframe, a
visible trace can be produced by pressing the BEAMFINDER switch on the mainframe. This causes the - 12.6V
on the beamfinder line to be removed, turns Q19 off, and disables the current source, U2c. The vertical display
then reverts to the 10 dB per division mode while the horizontal display sweep is narrowed and the trace is
intensified by the mainframe. The H P 853A mainframe does not require a BEAMFINDER, therefore the
mainframe always supplies - 12.6V to the beamfinder line.
OUTPUT TO
VERTICAL
DEFLECTION
PLATES
Y NORM
INPUT
I Q 15 9 CURRENT SOURCE
015 Z 1 O m A
L NORM I N P U T
BYPASS + 1 2 V
NORM - 1 2 V
The gain of the vertical driver is set by a voltage divider consisting of R39, R42, and vertical gain control (VERT
GAIN) A2AlR7. This gain control adjusts the ratio of the voltage divider. Transistor pairs Q2/Q6 and Q3/Q7
are current-to-voltage amplifiers driven by the current from the collectors of Q14a and Q14b, respectively.
Diodes CR5 through CR8 prevent the bases of 4 2 , 43, 46, and 4 7 from being driven negative more than 0.6V
Resistors R44 and R52 decouple the capacitive load presented by the CRT plates from the emitter of 4 2 and 4 3 .
Decoupling is necessary to prevent overshoot and ringing in the Vertical Driver.
MODEL 8559A SERVICE
SWEEP RAMP
HI/LO LIMIT
COMPARATOR
i 1 2 I N BYPASS MODE.
- 1 2 I N MODE
CRT
BLANKING
-11V TRACE
output to the mainframe, 4 4 must receive a positive voltage. The Blanking Driver is driven by the Vertical/
Baseline Comparator and the Sweep Ramp High/Low Limit Comparator. Either of these circuits can produce
the positive input needed by the Blanking Driver to produce a blanking output.
The display is blanked during retrace and during the dead time of the sweep ramp. Retrace blanking from the
Sweep Generator/Bandwidth Control Assembly A9 is applied to the emitter of the buffer amplifier Q1. When
the sweep ramp is turned off (dead time), the retrace blanking signal rises to + 1 0 1 This voltage appears at the
base of Q4, blanking the display. Simultaneously, the + 10V signal is applied to base of Q5, causing the collector
of Q10 to rise to + 15Y Transistor Q10 provides the signal used to lift the pen of the X-Y recorder during the
analyzer's sweep retrace and dead time. Zener diodes VR2 and VR3 limit the output to 35V to protect Q10 from
high voltage and inductive transits generated by the X-Y recorder.
The front panel SWEEP indicator lights when the retrace blanking signal is low (OV). Transistor 4 2 2 is turned
on by the low retrace signal and switches on the SWEEP light-emitting diode.
Display Held in Blanked Mode: When this occurs, it may be necessary to increase the display intensity (on
HP 180 series mainframes) to make the trace visible. A bright dot appears at the beginning of the trace and the
BL CLIP control does not work. Most common failures are 4 8 and 4 1 6 (always change both).
The S + T line from the Frequency Control Assembly A7 can cause the comparators (block C) to latch-up.
The Sweep Generator/Bandwidth Assembly A9 retrace line input line can lock-up retrace.
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MODEL 8559A SERVICE
r-- GAIN
0 -
A15 V E R T I C A L D R I V E R I B L A N K I N G
VERTICAL DRIVER
0 0
-7 VERT
VERT
-
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I
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I
I
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* I
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A15
VERTICAL DRIVERJBLANKING ASSEMBLY
53
VERTICAL
DEFLECTION OUT
L
& L NORM
J1 52
@ VERT (-1 VERT {+)
\ I
R1 54
/Y NORM
1 dB
OFFSET
GND
A16
MOTHERBOARD ASSEMBLY
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E X T HORlZ Q A I N
T o obtain servicing information o r t o order replacement parts, contact the nearest Hewlett-
Packard Sales and Service Office listed in the HP Catalog, o r contact the nearest regional office
listed below :
IN CANADA
SWITZERLAND
Hewlett-Packard (Canada) Ltd. Hewlett-Packard (Schweiz) AC
1 7 500 South Service Road 2 9 Chemin Chateau Bloc
Trans-Canada Highway CH-12 1 9 LeLignon-Geneva
Kirkland, Quebec H9J 2M5