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Micro Processor and Micro Controller

Micro processor and micro controller

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Janaki Ram
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93 views

Micro Processor and Micro Controller

Micro processor and micro controller

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Janaki Ram
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© © All Rights Reserved
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LUNIT-1_(0096 Archtecturm int, con Sat and as What Is meant by rag OF eroprocarsor?, “PY eaten in abe feed om code segment dds ables ofan ston, st diferent types of 8086 hardware interrupts. sensi, a ep. eK “Te een seit 086 a, General puposereisters Seginen registers 2 3, Pointers and Tnden registers 4. eso, (R84. 018) Wat ant and conwel age of | & — Ifespapismade |, ten micoprecs ie reemee eet ar censor nsagl ppg mode iy of 886 microm about 13086 microprocessor? sa reaenemeee imag genet ‘sel in sing operations o move the data from stern 8086 consist of nie fags and ae ed ge nae | ihre telnet ese WARMING: XeosPhterigs! tia CMA. ESL pce SPECTRUM ALLIN-ONE JOURNAL FOR EN ‘Scanned with Comscanner MOV Al-20H ;Das20HamovediomtsectinAL Moy (290 HT da 20F Hinmevet a2. Se Bo am 1 is TRUE then ihe se net tO. the SK re BSS. & Draw the functional diagram af 8086 micropr sor and explain x Jas {yNTUHYOERABAD] ND MICROCONTROLLE! om ofan | 16 MICROPROCESSORS At Tegmen egos “Fr iss nimonsamennc ete Mes year vbr ND) whch tO ‘tics is ae no 16a semen 2 Exhseymencontin 64k ates of meme Bat ‘Fany prctineSOe os ny fur 6 Seveement. 18 Thefouracmentos coe spent dcp, tr cpmen 20 sk Seen Eh segment isle with Hi segment reser | Thoesepmenteiten auntie ring Micwcore sermons tnsracon Painter TP) 12 pins te fi ads of he net instuton tebe feedtrom oe seemen. © Mivupde by BIUs0 htt contig the oft {Gane in te from se ares ef ie nest section Unt UD ‘The excction uit giv {etnetion oe isto te Ft Garaeced and exces De ston |& The execution nit provides effective addresses of Treioryestons. Taras ithe acd 10 BSE SSE ne eens ns ee “The finns prs of xecaion wit, Cont it Insection decoder ‘rth a ie wit agrees Genel prose mises oie and den ee. — . pert. fechinginsinin See hm baricc eat andenetonotmsrcion Perce wi ae pertormed siinacy i Shed prt proces 44.2 Register Organization, Programming Information ofthe pene se 1 rear ott oe Se apaas Osan cai Sctitn t b ot oer ae sos ncn eae a en ‘nt ity 583,000) eta Tn Te od nd Genera purpose reper ee rgecnie Tecan ach sarememeanais Tae einen red sep sow ane 8 Towers withthe ye with {Thee reir cn test he a ible and Retoclneeut rast eran oan ot 384 lator eit (AX) ‘eis V6bieeiser ich pl no wo Biceps, ALasdAH, a 2°" Abs wed to stor lowe byte adres an AH is wed ‘Sore bigeye ses 2 swept Oopratins nd ing spon, Base register (OX) Iisa tiesto sete gang base adress ‘fe memay nese sis ss sepmet, Counter repter(CX) obi ger ctor stig pean forged epson Date regter(O8) © Wis 6St pnd ince ep aes Woereatons ee ros ‘Meante wed asa 32-bit by combining it wth scalar reper (DX: AN) efor al Sascopreenn DI Pefom mainly ont WARNING: eoxPitcog is bois a CRADUAL Ayn fod py ABLE Wc LEAL pce, UNIT-1 (0006 Arcee, ne SeamentResiters re arf Dement ei in 0, Date Sement Rec BS} see pint the is es oat epen Code Segmini Reger es) I nused ite uses cade sept ack Segment Register [SS] — {ee ad orth baa of ck emery Extra Seiment Register [ES] ivetinare behets oti geet The pointer and ine group reiser ewe a0 eines : — wo Sch Pinter '@ eis wed oho the ais of ak top & Stack opi pper most ils memory lation a sack & Whenever the dats is sored in stack memory, the ‘sont of tack pine ae Est azeremersl and hen incremented afer every sack read eperaion fea mean ener ‘© + The BP reine i ity eed wo aces any teason ‘eal nts Indes repisters Seuree ney and Detnation Index Stand Daca memory yin seo sept | tepner DS. Micyproeerwil take he eee Mrs ofthe das fom St ond ores DL _Imorcin rity ENNO CL O9 BOHN Tee contnsthe feats denen ich ip pune mt mtecton oh eth on + code segment, Program Counter © atholde ye adds ofan insptin whichis 9 © When reser setvate the PCs sto the aes of the fist inscton to be tebe. The, the contents of oram contr are aio incremented Flag Reth Misa 16-biropiser which provides compuaionressbs erformed inthe ALU. ‘Gas Draw tho flag register of 8086 microprocessor ‘and explain each flag. cox... a1 rueton Sot ond Assert Language Programming of 8086) a ‘Draw and expiainthe each ita 2086 famiy microprocessor. (on Draw the structure of 086 Mag register ‘explain the nite Fig epster ia Iehteptermbich provides comput- on ota petricd nw ALU. eyewel™™ © eons of 9 ative Mags panied ito t¥9 Fa, Conon codec st p35 Nachine conto Mag3 © gress, aes are wed a states ag. They ae '& ~ Whenmicopcesor performs any aithnes or gic ‘peation in ALU, depending upon Tsui of ea ‘Blropcenor sore eomesponding stats bits ob inst tags. © Operation ofeach tm ag ia follows, Carry FCP) «+ daring ation avubacion. awulary Cary Fag (AP) Wis set oT ia cary onstflows from loner ithe to higher nthe te. from D9, Pari Fag (PP) : & Iesstto fhe numberof one in LSBs of result is svenie.0,2,4,8ete PF = & Uethenamber of ones in LSBs of tet sold Le, 1.3, 5.78 Zero Flag ZF) © Wis sett 1 if te ees of any arithmetic or lgieal operation in ALU ie 70. resets 100, the result in ALU is non 200, Sign Fag (SF) Tes sett Vif the result of any arte o logical peraton in ALU We negatve ‘Overton Flag (OF) & Wisscto ifthe rsh of any arithmetic opeasion of Signed binary numbers i outof range & —teresets 0 ifthe signed results within the range. Machine contol Mags to ag sepser3 lags ate wed 2 contol fags. They (or) se Th and DF, ‘SPECTRUM ALLIN-ONE JOURWAL FOR ENGINEERING STUDENTS ‘Scanned with Comscanner Lens {JNTU-HYDERABAD) onTRO UNIT-1 (0086 Archers JcESSORS AND MICROC’ are the 100 owes are ton Set oe a micnoPRoces: Roce ater ce het MO = Asertly Language Programming of 8088) 19 Taterropt Flag OF) Ne cdr = exh pater E eects "Figure (I) lastates the non-oveap agers Fr lier toy ountioqnbitistcheiere crt |. oicencintndoabowcramen serena PEEPIEF] ae careers | tase “Sito be bh eshon a = none Tete bes tt j 4 Recmtegmblemassbeinertamteestodate |e con cnet fis ei Fling he GRRE} ies teierne Te i eo ee wt): Boot {= a epee emer Fo sti ef fw Seat 4 Tgeeewina ered ond rap fags made 0 thn micrpecenr exces [snk samen i ump ta ds Csconcnicntsa nesed ee | eta totam, figment 4 msg operon ~ A Bi. How 1 clclae the phyteal memory of aD, he 4 Hap fags made then miroprocemer excete tbe Sy ¢ me? 7 — we lems, frovim singe trinr mode ol i ane: = Seneseragmmstutio dena teorovine | wet se Phys asin 208mg a el = Mis gemrte by ating egret on oe Etecive E Direction Fag (DF) aS en rs) arenes wich Tebit wide Prone Figure Mas ovrapping Segments wed in git opts mone nom | BGI Ie | ope ont i eh 2. Ovrappe Seqmentation Agee ate oloverbneatrserviervems | ‘Gt a | nat te ade of sen rept i pens | ® These which ov itech eter we how 2 itniseno}.sringtoia seacenedtrombideryts | | sith fo Oise 000 SB dine cay | avovetped eemenaton Sonne ere || ee |. a om o | a : 4 Aa sepment wih 2 6 yt of ema sar a §F Mauwec sing igma aroeceet teniecetgie | ets ra | Them theoreti addi tres nr toa ante sept ors tre dares to higheF Bye nabs ma Fre Tas Sci | aca tree then overlap occur, Advantage : 41.3 Memory Segmentation, Memory Addresses, Physical Memory Organization . ‘229, Explain the concept of segmented memory. ‘What are the advantages? + Ans: peo noione ‘Memory Segmentation & Unt0s6,svalable emery space i divided into hash Shed semen Sct aeons known a evi mor de proces shown memory epson In 086, the available memory space ic IMB isdivided {nv mamber of logical segments a shown in se ach egments64K bytes insze nd essed by one “The segment register of 086 acts a base register ‘The segment registers points tothe stating emery ress of he erently Wied semen Memory segmentation process i explained wing tbe following example. conser «housing colony with 10D howe. [Afocating the mabe consult thous fom 1 Moo ssp technique for numbering th houses ‘Consider case that a person wants 0 reach Rowse ene so, for entiyinghowse no. SE, be will art te house muir 1 and go onl ke Binds he house eetpered 8, This eases time taking abe th ser to work with registers having only re, “eT dts andthe mer’ cade canbe stored separ ‘owing fr more Best ‘Seqwertion slows programs 10 be Foaded and run Sphere inte meme . toms the recomiltion of progr independent ats hese eis trend ese og edt pectin a ‘inlet ding rowing se: Iu redces the number of bis tequired Sides 3 memory lesion ___memon ection _____ ab, Describe the Implementation of pipelined pro- cess of 8086. Ans: eeegee os nce 9, CRO Piping ses tine require fer exci nstcins For exampl ifs ation operation it be performed tithe operands vies, the microprocessor takes 100, ‘ockeycles, however, wibou pipelining and with pipelining. the number of elok cles rege o mally $9 operands fpetrcativly eae. Ther are mary instctions 8086 thst equ hge number felock le, Ts the pre-e queue becomes 3 crucial pa in enharcng the performance ofthe system. Following figure depicts the ime taken for executing "oisrctions with and without pipelining WARNING: xecuPisorn lek ZCHINAL a Ay ed ty URL LEAL pen ‘Seren ses 195 cv ates = 4537 : Posnti=? Physical aes Sepmetades Eines — an - mE ysl stess = MOAT ‘G52. Explain segmentation using overlapped and nonoverlapped segments. Ans: In 8586, the memory segmentation eased ino to ‘ypesas, Now-overlapped Segmentation “The segments which doesnot overlap wih each ter ar Anon as non verapped sepme'. ‘The adresses ofthe oe overlapped seen ranges Foe, 000# to Food Hand fet adres vals ae asics, fom 0000 11 o EFF H. Ths the psi dese re (00000 119 FFFEF 1. Aste segments doesnot overlap with each ther, his FE of epneiation is non a non-over seMERACA. Astoth the sepmests overlap with ach othe is ype ‘tsepmentton i known st overlapped sepmention- Figure (2) lasses the overlapped Segmentation. (2 velpped Segment {G33. Explain the physical memory organization of Ans: ° ‘8086 system. presi, 0) ‘The addressing capacity of 8086 microproceserisabout MB (i, 20 adress ines, 2"). “The total memary space is divided ino to backs of S12 [kB each, These wo memory banks are eferedas lower (er even) bank and upper (or 04) bank. ‘SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS ‘Scanned with Comscanner Se svoswi QC 200) CD = meg ont gre 1: We Operation The sbove ting diagrams can be underood by he folowing eps 1 Dising the clock ple T, jt befor staring the ber ‘pte the status signals (§ «3, 5) are set 191 By {he change in he stats signals, conte snes ple wale, 2 After etising ge ALE. the signals NHRDC TORE (temo, Res Command Input Out Read Conn) ‘dT Kare sable ul fsaté Thiseanbe achieved tpmaking DEN = O and TR low forint onde + Groupee 3. Then IC#299 old the address during lock pute 2 folowing edge ofthe ALE signal sare dled athe stats Bis 55, ate present on A S/S, and BNE, respectively. 'S. The tansecver activate by making Dat Embie We bey DEN -1.thevead operation ca out by ‘craig the signal! MRDC or IORC fa 7, stand Paintin, During the write operation, th signals AIC ot ‘RIOWC ar enabled rom 07, ad the size MIWTC oF IOWC are eosie fom 7, 7s 7. After he reception of dat ie the ck ple 7, he processor iss the signal MWTCie, MNTC=I, 8. Detectingtheehange inthe writ signal menory and VO devices dbl te respective digs. 9. Forciberseador write operation wasceieria dhpd Syising Data Enable (DEN signal When the READY input of £086 isnot activated, iivonal wait stats (7) are employed beter the MICROPROCESSORS ANO Ml scnocONTROLLERS [NTUHYDERABAD ter piste Pa that ry Inara naa on tance nae elisnetSe sa (51 To, ip cee a ied wart ers a6 a ray e ‘eee ft a lise it tee way SitowninFeot. | Marware and Sftate eterapts | Hardee intestines which ney evel hard by sedi Fe ero pin fe rocena, Sf tne we, NM and NTR, nero eines, which are tine ing speci ineions inthe program rng IZESGtE tat poco ere 286 soe Soekgeowh bn chen hee Mashable nad Novae teropts The reenr it ey ct) tet : soo ore Pagani pcre Seelam inter it ae aig eng Sicep > Fepsengpmcartjc iemt cae ‘ake ding rag 25 wy Beer re casi nto eastable ‘nde aise eres tn 06 pce, * that Veter a Rood Tero © Wenminenge raced hy he rset, i Naar ay moet branches tre specie wae fades, the the interropeis called # Meester den lock pales 7,207 LUNIT-1_(0086 Architecture. Instruction Set and Asser Language Programming of 8086) ‘G41. Write short notes on interrupt service routine ‘Concept of 8086 microprocessor yom cum (on Explain interrupt service routine concept. * poorer 1& HONG prone sevice 10. ert by exciting & progam ale the itt serie rte. 8 Amine a seca event forthe procenoe Ae providing serie to all he nterope. oes it ese nora program exec 9 4086 stops execution of progr nd resume it er by svi he pogrom cutter vale ad processor sas Information before execuing the tempt service routine, and.then restoring the progam ouster and Procesor sts before exting the inert service ‘Te complete ier cyl is lows 1. When am interptoeeus, save the program counter value inibe wack 2. Save the processor sas (nctaling the procestor ‘usregie and some ober reper) he ck. enti he ease of their 4. thease of hardware intra though INTR. the pro= ‘stor nal intert acknowledge epee fo gt he Isterup type number For sotwateinerops, be pe umber speed in the stun uel. For NM {nsrastion the ype suber deine by INTEL 5, Resolve he sartig ders fhe comespeoding Inter opt Service Rostine (1), 6 Execute the ISR to servic the interrp. 7. Restore the proceso sts nd the program courier fo the stack before citing the ISR estat the ram, (242, Draw the interrupt vector table and explain is operation, ‘ete. OH te (on, Explain interrupt structure of 8086, 47 ‘anes eee 2 ecnptstuctze fen othe pees of nema 4 Teprecadec fiers iinporants hous ths higher pcedece trp can Pd cra loner py Than pce an deers of 8 ccuitiontanttelas © Thefllowig Fie sons th interop stn of OSA, {i ahocalad crm coe ube Se gre Intrap Strate of 8085 @ Thememary sizer vecter ube of WD4 byes fads fen OOo OOF Hh © eons 256 perf interupt vectors cach of Bytes © 191086, among 286 pes finer vector fit pres les ype Ovo ped vectors ae defined by INTEL 30 they known ts predetned step vectors. ©” Thevecton fom ype Stone 31 Le, 27 afereserved feethir en in varios miemprocesor fami, © Teta ae nabslgs ar aa 4 Thefistine imeeript vector ar identical inal INTEL rmeropeocesorfaily members Gorn the 8086 to the peti. 4 Exchvectritoffourtytsslong and consinthesarting ress ofthe inert service procedure % The fst tw bytes ofthe vector contains the oft acess andthe Iast to bytes contain the sement 2 stor ae avalbBleas aS RTE esto Mares. © The following are the INTEL predefined or desist) Interrupt. om ‘TypeO (Division by zerotaterrupt: ors whencver ‘theresulofadivison overflows orwheneveran emp ‘ismade to divide by tere ‘Type 1 (Single step or trap interrupt): It sus afer the execution ofeach stato, ithe Tap Fag (TF) Tits set Upon aeepting thi ert, the TFit cleared, so that the interup service executes 2 ull ym. 098) (on Wite short note on interrupt structure of 8086. oR. (A UY explain aboutinterupt structure of 8086 micro- processor. vost n0n 049) (on Explain the interrupts structure of 8086, pomp S,08 speedy sak d spree ‘SPECTRUM ALL N-ONE JOURNAL FOR ENGINEERING STUDEN! \ \ ‘Scanned with Comscanner of plcingw logs 108 he ML pat pin proce This iepuis on mast, which mena eamot be dsc, = ps om terra: Iiswsed imple reskin faction, which neers program pay poiieaotocon cm s ‘ype 4 Orettow tntéceupt: Ii rei vector ti een ThE en fan eve condition x, Sted be So (243. What are Interrupts? What ae thelr uses? List and explain aiferent Interrupt supported by {8086 microprocessor. ose of « Eaplan varus pen of ftert nC mrprocetsor - ser tear aX Ferenc fer Unit ond 80 Te vaio interop i 8986 a, 1. Hardware tterraps The inept which are inte by apie oper signals to INTR and NMI pine of F086 ae elie as rare iter, . ven amie 1 he Rare serps ae al. © When IF i 0 the arma interrupts re masked sled (NMI (00 Mashable laterropt) tuna postive ede tigger hardware nem pin tavighipher pny thas INTR.NMIpin.canet be dplayed. So, I sealed as noe-masiable Tempe (WTR Cterrapt Request) 1 evel wggeed hardware itera Aleve sould be applied cotnuosly on IXTR pn it the tie procenor ives acknowl sgl on NTR pin MICROPROCESSORS AND MICROC’ oNTROLLERS [JNTU-HYDERABAD, = af Tehran reat eto i omaha teres ity IST nat ves A hes eters . i incon 18 FRVOKEA Dy eT a Te moe EE ae sree SR Ny a rege DO * ptine Freer ene is ert sae ening ath prac #61" AREY Etc Mf "so86 automatically jumpy ach iy ayes fe CS POF he a sen owe PRESET Soy wy a2: Tsien calledeowmattie iat SN ‘When he pin O86 proceso eeives Frentigh easton he proceso aon eves pein Fae oped intrapt cannot be disabled ee rated If 406i exeeuting insition “Af Fie foone, Men sie th itera device ress psn ede sigs en NMI pi then he enor oes he tof inal on NMI in Treonplereuice of eet instrstion ‘4 sodthen eee rare interop NMI, Whe «tees NMI tances om main prog of SRasig INT 2 tion {INT Tsing igwed 6 examine he CPU and memory afer the execution of a group of isruton isa one byte nro, wheres coe star inept a to bt isting (9 IST: Tisinemisactatey the CPU, whee eimai placed afer sigsed nue scntcasIMUL oe ADD and OF = 1 When (OF 0, RTOs mt ened bt iy adc asNOP. TNT cause he CPU topes "NT and jas to pyc ostion OOOH af Severe pte CSI of he ISR (G44. What isthe aiference between maskable and onsmashable interrupts? ‘Ans: 1 dees been maabe and non masks ” tert aa flo, ARNG et " roceeigs. t / unit. 119 (0006 Archtecive,Instrction Set and Assembly Language Programming of 8086) TT an et car ever Be redo, en RH Ted erste era tot of te devicer alow thew inept ured on iran aera ci Be trae ol By Be OSE ice called mashable merge Devices by deft tr off o dnge mastable} 2 Stokoe eres ba eahatle trope omer pein than non | 3 cpt The pony stars the adress ONFFE 44. |The prioty start atthe ate OXFFE. 4 5: | STR oie yt mene mutate] 3. [Nitin proiey sss ecenetnow-maate 6 [ROTTS RST 6s, RST 55. arethe examples of| 6, [Tha the mest popu example ofgonmasable mashable inter ern 21] Fm interne ne ma | Poser tre eters are non-mashablentemupts (045, Oraw and explain Interrupt acknowledgement cycte of 8086, fain : os.inon a8) {@ The RONG mathabeierrpt ar inked vi the ENTR pin [brie enim pai e men | & The state of INTR pins sampled during the lst clock eyle oF ‘cach insiction, The response of B86 to INTR is dscuned 35 <= - ma ——+ . & Toc interopt acknowledge nequence inches wo TA, cycles separate by two ile elock eyes Hence, 8086 fst“ oes two interop acknowledge cyte as depicted inthe ge = wae to getibe iterupt type fom the external device. ‘Tew lncerpthctoretops Cpe + _Infrat inter acknowledge machine cycle the 8086 flats the data bus lines AD, AD,, and sends out INTA pulse on its INTA ouput pin @ ALK also generated bythe $086 and wll aid he OSG wth interme information & The fiat INTA bus cycle indicates tha, an ntrup acknowledge cyte isin progres and allows the system tobe ready toplce the interapt ype code om the next INTA Bus ele & uti the ssond interop acknowledge machin yee the S036 sends out anaes pulse on its TST ousput pin, ‘© —Inresponsetoths second INTA pulse the extemal device puts the nteropt type on lower 8 bis ofthe data bus, % Oncethe 8086 receives he interop pe, it pushes th Nags the tack, clears TF and IF and pushcs the CS and IP values of the nex instruction on othe stack. 8086 then gets the new value of TP fom the memory adéeess equal a4 times the intemupe ype (number). eI 4 tnteropt number ‘And 6 valve from the memory address equal 04 times the interrupt type (umber) plus 2 Le, C84» Interapt number + 2. ‘Hence, itequies a minimum of? bus cycles pls an additional of? ile clock cycles to execut the fist iastruction in the Inter sevice routine afer an interrupt i recogized 1.2 Instruction Ser ano Assemsty Lancuace Procramminc of 8086, 4.2.4 Instruction Formats ass, Uist out and explain instruction formats of 8086 microprocessors. te on. ca) fon Discuss different instruction formats supported by the 8086 microprocessor. (or) ‘SPECTRUM ALLAN-ONE JOURNAL FOR ENGINEERING STUDENTS ye, 8 00 ‘Scanned with Comscanner RAB NTROLLERS [INT 240) 2. MICROPROCESSORS AND MA AST a mode 412.2 Addressing Modes 48. riety explain sqquental control low and con- trol transfer instructions, Ans: Fase o the Now of instruction execution, stations eels int we types mal, Sequential onitol New Ssroctions and Conta ranaferinsttons 1. Sequeatilcontrl ow tnstrcto ‘The strctons which er excastion, wasters te conto he net nstcton wich appear cdl er itis he program are known as sequential ont New insvctont Example: Ardmetie opel, dita wanser and prsesor ‘ete inaction. ‘The insetons which ranser contol to some redefined adres ort the adesesomeferespecied {he insrction afer tei execution are known ot cntl traernterons. Example: INT.CALLRET and INP. {Q49. Define addressing mode? List out aerent ad ‘dressing modes used in 8086 microprocessor. ‘cael XX tus and explain siterentadresing modes ore tm 800 ikceprceesor (on oxas.mn.can fo Discuss the addressing modes of 80867 Give examples. ven. (or) LUst and explain with examples, the address- Ing modes of 8086 pp. mem mincam (on) Enlist the addressing modes of 8086 and de- Scribe briefly each addressing mode with one ‘example. _ eat (en, Explain the addressing modes of 8086. ayn 00) (0 ‘Explain addressing modes of 8086 with an ex- ample. 490m 29) “ Meme sy a veant wa addressing mode? g, iat rt asin Os Me, me Steam " set ce the dat rig ode ine na sting tthe sir Soporte ERE acts in desir ee rene aks FOS oscar and control instruction’ 2 inthis address og Node his sing 1 Reger Ade ation ae Seca sie of sm a set OE Fee ec ena nae i, abi eam ag coment BLE veo AL eof Lat ded wah cy. ADD Ce Bip ret is red in CL. mmc ting ete 8 ig ed et ped ec at se ncn ty en Baume: AOV AL 20M Da0Hsmenedioantanetich, Mov [i.230F 1H The data 20 TH istnoved oe Seemory (St 3. DutaSemiry Addreslag Mod aa mena siessing modes ae (0. Dire Addesng In this aessing mode, be ete aes let adress of perdi Speedin iestetion Th operand vac inte py asiesis moved the dstisien rege ie: MOV AL, 100011) lev adits = 1000 4 Menoryaddein=DS = 1011+ EA 310008 ‘ye sled from 31000 H memery Instn dsr in AL, (0) ‘Baw Addesing: In this addressing mo, Contents of BX oe BP risers constitute be — _fftive ade fiction. ie. EA = (8X) EAS [RP] je: @ Movct, tax) Meomry ass =DS 161 + (8X) =320011 ‘The ot othe memory address (32000 18 ‘ead fom dat segment ant stored in CL. ® MovDx, (nF) Memay aides =86 1011+ fr} = 41000 Ans: 3 ect yes fon WARNING: Zootoo Pe wed fom 4100 tt memery desi Svoseckepnect an stored in DX ca iA. eye ed ay LAE LAL ced LUNIT-1_ (0006 Architecture, struction Set and Assembly Language Programming f 086) a) Bae Relative Adreing: neiasng mode, fhe cre fase regiter sg wih te 1 {i duplacmet conta he ectne aes of ie FAs Mscrepiter + 6itipaement MOVAX. (0X +5} Memory address = DS «1011 EA =DS «1011 tax] +5 = sn000 = 2000 + § 32005 1 ‘he word fom 32005 H memory ade i read and sored AX fie) Index Addresig: In is addresing mode, he ‘nets of St or I reper contin eectve + se fiesrcon {en EA [Sl] or EA (01) Example: MOY. CX, (DI) Memory alress = DS « 1011+ EA, =D »10H1+ (0) = 306001 + 3000 11 * 33000 ‘The vod fom 33000 1 memory addes is ead and sored in CX, (9) Index Relative Adaresing: a this adzessng mode, index registers long with displacement Coosa elective ass of the intrction te, BA=[SI]# 816 displacement. MOV Bx, [St~ 10011) EA [St]- 10081 Memory aes = DS = 10+ SI] 100} "30000 H+ 10004f= 00H = 30F00 The word foes SOFO0 1 memory adress ie read and stored BX, " (61) Base Plus Index Addressing: In this addesing ‘mode, the contents of hae register tad i ‘easter donstts elective addres. ie, EA=(BX]+ [SI] Example: MOV AX, [BX + St Memory aes = DS x 1011+ [BX] +1] = 30000 H+ 20001 + 10001 % 33000 ‘The word fom 33000 H memory adres is rend and sored AX (i) Base Relative Ph Index Address ddcessing mode, the contents of base reise, index reser and an S-bi016-i displacement ona effective adds, ie, BA=[BX]*(Sl]+8/16itdsplacement Exam 1.23 ple: MOV CX.[8X+ sI+ 20") EA= [Bx] + (51) +20 Memory ates = DS» 10H + (BX) + [81] +2011 “30000 +2000 + 10081» 201 =nm0n ‘he word am 35020 H memory address is vend and sored in CX Reanch-Related Addrewing Modes: There ae fo ‘ppevoftranch elated adlresing mes. They ae, (0) Intrasegment Direet Mode: In this addressing rode he cote olson Pier) alone sith Te ceplacementconstites te eect ranch address. ‘EBA=Content of P+ 716 placement. ‘his addressing mode i used with conditional or ‘icondtonl branch intrusions apa is refered to aerate adressing mode (0) tnteasegment tndireet Mose: In this dressing ttode, he contents of ny regime) location Aeessed wing any ofthe data elated desing tmodes except immediate mode consuiutes the fective branch address. The effective branch ‘Mrs replce te contents of. This addressing ‘pode is ured only in unconditional branch lersegment Diceet: In this aéresing ode, ‘one hal of insractionfesent ithe memory ate ‘copiedinto IP and another afnto Code Segment (CS). This allows branching between two code segments, (Go) Tntersegment Indirect: Ie this addressing mode, the contents of the two successive words present In memory ae accessed using any of the data- related sdcesing modes except the immediste andregister modes. These contents are copied ito and Code Segment (C8) 41213 instruction Set n (250. What are the ciferentinstruction types of 80867 Anat yay 54 08) ‘The dferat astructon types of 086 ae cased a+ follows, Data Copy/Transfer Instructions ‘The instructions which are responsible foe tansfering «aa fom source operand to dstton operand are ald ata copy or transfer intretons. Miche ore, oe, ‘The instructions which caryout arithmetic, logic, in semen, decrement, sean nd compare fonctions are called arithmetic an logis instructions. ‘SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS: ‘Scanned with Comscanner Ute piven with DT then EA aloted tthe fet 10 fst mabe cused the ae his ae! (GRD aris ica (6. ASSUME: eis wied te inform te assembler which Inpeal segment name i aumed fr coe, € sck fda segments. Example [ASSUME CS : CODE , DS : DATA. ES : EXTRA “The mimo segment having name cade is code meng sepnct When pega is exceed, Be tae ae of ths memory sepment shouldbe ordi CS ee 7. END (End of Program): Inform thease 1 ‘Hop the program excetion. END drive shoul be Imenioned only once atthe end ef he poem. ‘ould mot be used tn the mil ofa program ast igeores the realning source lines. PROC (Procedare) and ENDP (End Procedare: PROC sssenbler directive tuted o india thet tf sebprogram or procedure Similarly ENDP issedte inde the ead of program or reed Ie gene form is, LABEL PROC NEARFAR LABEL ENDP 9. SEGMENT and ENDS: Segment asemblerdcite iS wed to inform the assembler that» semen is ‘Saring is genera form [tome SEGMENT) * ENDS assembler dete seo inform hese Ber tout be endo sqpnen Hs gral fm i, (SaneENDS + Exam DATA SEGMENT DATAENDS 10. EVEN(Alignon even memory address: ised wit DW dire to ifom Be aseaber tat memo Fret aioopent ford word shouldbe sted mat comnalaess - An, EQU Equate: is sed def te vale of el Even fo abel used emule tines, wehaveta dee its vale only once ‘The general orm of EQU asseble directv i, (aber EQU 8a 16 bt aber anne expres) [LABEL EQU 03008 [ADDITION EQUADD re 1s ITU-HYDERABAr ens (INI 0) 1.34 icnopRocessons AND MIGROCONTROL . Ta ENTRNS eed Oo Beri iswoning this directive thu the mare 98 eis een foi, rye FARNEAR Taumple . FAR EXTRN REPEAT NEAR ember tha, emcee sete a ee a neat Eat pray rr ones Sam et on em a nett e oer seo erate nth # Inte indie te Kaehetecmnec tHE eee paces such a8 label, aie, oct Te Fah we decd 6 LOCAL ec tte ely at module ele. eesctaial anne of «mods 1 specion te NANT ae bee mlipl shes Garset hanged he assembler tcalssae Se or dopicenet of samedi Hem oe nl form of OFFSET ase Sree ore sample: MOV OFFSET tit ~ ‘ORG (Orn) Listed foo he seb fate mene cao tment om the aes chs decent eo . Hes, EA~ Eee Ades FIR ote ede ee me pt This petri reed by BYTE or WORD. BYTEPTE: Vr er memory operand a i ‘WORD PTR phe or memory operand as 16 pe INCAYTE TRS} ida ofmeinoryisiocesel NCWORDFTR|S 6d ofmemory since Hebd ofmeonysi SOREN ease at nly 680%) aces Mente amp nsruction. specified ater te LABEL, Tater r Das i Bye oe fos 2] sor 2 34 GLOBAL: The puameters fechas 7 sateen ta 1s arb constant or peda chore dcaedas GLOBAL ina module hy tis used to erate numerous men elation and alloc ales to them. Ferma oe Dat ype NUM DUP Vaio 36 CODE-DATA, STAGE {CODE ce coe segment te err formats, [CODE a] LDATA- refers ota epmen “STACK: feo sack sept In geo frmat i [STACK] 125 macros : Ok. Detoe Mie? Explala sinprzcen a8 prgranming Ee pau pope 049 {hat perform ove ak seas procedure: The diference that a procedure is accessed by wings CALL sii shies macs mend pepan ar op emer Macro sequence afer tan prods eros Few opcode ean esr AERO Sata tit pects tee bw CALL and RE menses Be 9 _Arepestéd code inown a5 prtaypee ee me Lays eode ying etn the efeencing and terminating statements i led macro © Thefistsatementofthe sco stem Tf the MACRO stent that contin the ame ofthemacro ad any pruetes ssid 4 Theieron of mac ih sine aay pointe gan eared mc cal Wen membre ash mace Yee men ret eas mel he mc ane pr i dey eae Thi tte cis expanded sensing ting curs in code no i acl ‘multiple string characters known as dummy parameters in ordet to process the assembler without any error. ee Erample MOVE —-MACROA,# Neusat, ax MOV. AX MOV -AAX por Ax END lth shove ample, MOVEisa ane ase oe ine el : incon ance bere he eit Bisav ol eso panne Ao Te sel be Nao he ENDML wh sh ot ‘The nsrcion sequence replaces he MOVE tnracton whenever appean inthe opr i 63." Explan the difference between procedure and macro used In 8086 microprocessor. to) What isthe itference between Macro and Subroutine? é ‘SPECTRUM ALLAN-ONE JOURNAL FOR ENGINEERING STUDENTS ‘Scanned with Comscanner LHYDERABAL 22 MICROPROCESSORS AND MICROCONTROLLERS [JNTUA AD) PART-A SHORT QUESTIONS WITH SOLUTIONS 1, Write an overview of 8031 microcontroler, — anes lacs «CPU! Athy gtd chi hat coin al he components comprising commas Tre ee some form of ROM. VO port incr The aint ofa miecotoer eon a ariel 7G Cvs fox emedld aplcatons contrat the mopar wed in pes oases plications : Fee G2 Wate brie the evolutions of microcontroller Ans: : A micoconrle isu ng chip which oni of mires along with memory (HOM smd RAM VO ‘rik nt sd vero pepe eae © es developed ini 970% {iat bi wit finite RAM syndy exer bed autre tos was mut tel Corson + "ea system on-chip (SOC) with two teers one serial pt nd four data ports Later, Intel eorpration manutd [Uicrecenalis in onan Yor conpsios Man LN ye RAM. te ofonehin mena a Draw the rame format of PSW. : 7 (on What isthe significance of program status word (PSW) register of 8051 microcontroller? er me, plcsions. Later, in 1981-8 powerful Bit Ans: & Program Status Word (PSW) is a special fineton reise. “@ —treontins four math gs user program ag FD and wo reser select is as shown ine. “& provides tats bits that indict the current state of CPU, ev |-ac | Fo [si] sof ov] - | Figur: PSH Fama Forme ‘Ga. Describe about the memory organization In 8051 mlcrocontrolier, 7 — Novsoa.st (R19. 8 ‘Memory efganizaton in 851 mlcrocontlei done a flows, 1, Program Memory )Exteral progam memory (i) tera program memory. 2 Data Memory (i) External data memory of 4K byes eapacity (Gi) ternal data memery of 286 byes apa, WARNING: oxPbtcrfon ts CAMERA Ar at ty ABLE LEGAL paces oe. 7 |e |] freon afte 8081 mina yrT-2_(InOSUCTON to Microcontroters an. om ds 8051 deren berm 14 051 Ret SHE Rea Te cory 2.3 ‘ral and intemal program memony? Teen Bene eral itera pga Program Memory intericed to poara| 2, [when EA pin is proundc,itindses tt he propram| code stored in exer memory. 3, | raet081 can have externa memory oto KB meres it, with address map OOKOKLFFFF, 4, |insietadesing moe i wed acess ewera bene, Internal Fegan Memory Teterat memoiy physelly exists on the chip of Program memory of #51 microcotlie. When EX pinis connect V., tnd tht be ora code i ord the mirocomtle s0n-hip (era) memary The intra memory £051 sof KD, with adress map 0004. OFFI Dizect addressing mode is wied to acees internal emeey (og. Define Instruction set and draw the instruction format of 8081, ans ° ° -Afoaat consisting of mnemonics Predefined Exp wed an peas is called an scion. A oup that consis of may istration fr april mzoeoni ical an inion et, ‘The inreton format of 851 micecontlle ssh afi. {TABELOPCODE OPERANISTCONIN Fre © Opes code (Opcode) represents the ype of peraton whe performed Opera epresens the data availble in the registers and abe ote operated {In 054, which register bank conficts withthe stack? Why? Ans: ‘The bank 1 register bank coutics withthe stk. Due tothe deft sing ecm ens.cne fhe stack, i st oct if AM is OBL hich belongs t ester RO of egter bank 1. Hence, they te ame memory ace 8. What nas Program counter isa 16-bit 8. List itferent instruction set groups of 8051 . a ‘The various instruc ‘ata manipulation instretons Data transfer itstrstions ‘Avithmeti istrtions * Logical instructions and Uonchinginstrtions. the size of program counter and SP register in 8051? ee, 8, 0H) inet Stack pointer isan St reise mersteiamere mse groups of 8051 micocontoler a8, ‘SPECTRUM ALLAN-ONE JOURNAL FOR ENGINEERING STUDENTS: ‘Scanned with Comscanner 24 ‘Gio, What PUSH and POP Instructions in 80517 Ans: sort 99, ae) rust “The PUSH instr increment the sack pine and stores te vale of he species te operand i the itera MICROPROCESSORS AND MICROCONTROLU ens [JNTU-HYDERABAD) TSI Lit te various Ineropts #UPPONES By the {8081 mlerocontrll re pov of $51 microcentole ay ans he iret ier fahutted below RAM ada indirectly referenced by he stack pointer, vor ‘The POP instruction needs byte fom the address init ference the SP reps. The vue esd steed stibe spectied ables andthe ack pote a decremented G11. What isthe Importance of Jur assembly I cof next instracion (Le nstuction afer jump insrcton) in eceram count Q12. Whats the function of Timer? Anat (oan Paper ig e473, OHO “he ain function of ter ae, measures the easton time. 2.” Wegulates the sped of the motor by atomically _swthing the ouput at a desired fequeney. 5. W awakens the procesor fiom low-power mode 12 tesive tate whenever any action sping perfor. 4 iegenerates time day. {G13. How many Umers and counters are avalable in ‘8051 microcontroller? What are thelr sizes ie 96.000) “$081 suppons two counters mer, namely timer and time 1. The sz ofeach timers bit ‘mcr 1. The siz ofeach timers WR _____ ‘G14. Draw the Toand Ti registers of 8951 microcon- troller. Ans: ‘Toand Tare it reginers which specifies the loge «ies and upper its of Ste TMOD register respectively “The egiter formate of TO and TT are shown in ewe, ert) Taner) rot 22 | esematiardware ert os) 43, | timesouer 0 overBow TPO) «4 eset Harare ner Jost) 1s. | rimesgomer vertow TF) eri emerge RUC _yNIT-2_ {introduction to Microcontroters anc 8051 14 8051 Real Tine Cont 2.5 PART. "ART-B ESSAY QUESTIONS WiTH SOLUTIONS. ZA WTRODUCTION To Micnoconrnottens: Ad Overview of 8051 Microcontecler ‘raw the block dlagram of mierocom, 18 eplan each block in deta. oa ‘Te block diagram ofa microcomputer in {a}? Tae Te Gis Latins various applications of 8051 microcon, toler ans 051 tas several applications in embedded produc, Some oftbem Ie Washing mais, fier, migrowave ovens Cabelas, Keyhods, Printers, Modems Figures Formas of 8a 1 WARNING: ex Phscoa bet i HMMA toa ind ay nL iL oy Figo: lok Diagram Wiroampster ‘Alike components ofamicrocdmputer re bien coe on Ceara Procesting Unt (CPU) 4 Iiethe hear of microcomputer sit 44+ (CPU) performs and conto lle operations oft smirocomputet 4 east ofthe following cements 2. Ini corals, i eatin mptems, cn ‘Arsh Logie Unit ALU) ecto ees i performs arithmetic operation ke wibratin, 4. My apteaios salon miiieaton, viion an lp opetons ‘ The AND, OR NOT, NOR angNAND et . Taicceotey oma re conbalee. | . Pee Program Counter (PC) Smuts ATM mtn ce isos 16it atest of he neat stun o be ‘GIT Now dows affect the SBUF SFR in wove com | carted im the program thu, it heeps Eck ofthe ‘montis of 80517 ropa sequent Stack Pointer (SP) os an aso. pron bat aleer nee hols tates ofthe pofbeseek (ete adies 8 SBF SER an 8 einer wh oni of fe eth lcton in stck, whee De sda wast). reser mmely, Tass tr (parallel is Accamelater ct aie) and Reve bul (a npr eins tpecial it epister a which te eu of ay ice : mathematical operation gts accumulated (sored) ised fds rmision and reception by wit Automatically ean slate edo sore he 8, sodreding acto SBUF reine rempective General purpose registers ttre vations at, Timing and contr wait : ‘used to synchronize the internal operations of icocomputer with he fequeny of be cock ital {nda onl te fo of aa wate meet ‘dato tween he ices eral Se ro Oster circuit ect eto * [isa known as clock gene. © Inconsst ofa rexonator and neces electial ® The feqency ofthe cock pulses and he fuctionng ‘peda merce pnt open be ee On-chip Memorex ‘ Thee are wo ypesof sn chip memos ape eral ROM (4) anneal RAM (128 te) © Internal ROM stores the program (code) Instron. iran Known a n-cip FORE Internal RAM stores he ta. is also known as nck ds memory TimervCesaters, Theseare torte regiter which we wedina progam, 1» decrmine the time period of am event ett cleats the umber of events. For example, pulve-wisth measurement, freqeney mearureren, baud at generation, and coting of ‘ate, can be done ing on-chip tier counter Interrupt Loge Cireitry 9° Rietbelogi creat ubich senses the inert asin ‘he microcompster snd shes the micrcempuie aware tthe ative iierrpt ad the order ofthe interrupts Swbich should be served by the microcmpute. Teizchdes iterrpt enable reps, fete pity register and other necesay clement ‘Serial and Paralel UO Ports ° “© ‘These ae wed to interface exzmal devices with the smecompue © The serial UO por is meant for tasting the data ‘etween microcomputer and extemal eves inte for of bis (Leone bit ata ie) whereas, the parallel LO [orisforeanferrng the data inthe frm ofbytes (ie, Discuss the advantages of microcontroller based ‘system over microprocessor based system. Ans: ‘Tee advantages of micoconrller bated system over risroprocestor based system are, 1. Miercoorollr based sym contains ton cuits suchas RAM, ROM, inp outptinefcingecuitand petpheral devices. 2. Lees hardware is required forthe system using ‘microcotoler de oi ia ull atonal fears ‘SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS. ) ‘Scanned with Camscanner 26 MICROPROCESSORS AND MIGROCONTROL! Tass Un eq for lain memary ofmceconrller Hee. pel of perso (eed fangs . ‘The POD sire rogue fora #micnconroler based systems Meroconole based systems are more reliable Mos of he pias of microcontroller are mulifenctiond Leone pin cag perform muti hndware requremes ‘The con of micrcenvole based sytem is st due LERS [JNTU-HYDERABAD) coal Ban det ee hardware Foren sions. “The coven of commen softwartardwaze desig svi frm marche Miercenoters ean easily synchronize the communesion between prea of ita reds. 10, _ Microconllet have many bi handing isttons ad hence comralings moe at aero ‘Gad What isthe difference between microprocessor and microcontoler? ; — utcenaig, |) (SSE [ SCS Se Ne ORT a, Como mrnracstrand mirza : i ao = edits teteen mips od mice lw. cain a T [Treacher of micepecsser consisoVADU | [The abies TNE ROM and RAM 7 SxS ce and vcs pecpheral wis axcsIRB. Orns an ee rere Ol 7S 2, | There are only few instructions in microprocessor that | 2. cer hasan i. SXCSIRC_ =. suppor data handling in bits AP aac most of the pins bave multiple = EXCSIRD, 3, | In a microprocessor, only few pins have multiple] 3. |1n # microconuolle, Tas Seven ae fuser. ae bo dressed sig diferent emery emaetie’, [BESS poems we ated win te ape 4 [Dusen se mem Tefen anemia a erate sui feet alten ition bites «REESE asin ic | 5 | ee ny mation mre ee | Ta Tao Fefen cesmierameng meme CPU. | | pet eve amber | With it | aemory | ROM Memery 6, | ntkes ore ume te acess memory and UO devices] 6; [hte Tits eicocentol 07 D Tr 7, | ardware requirements are mote for the systems that| 7. | Less hardware is required forthe systems that ue 8051 8 [ities | ans : om cca : asi sus ereow rere em 0 aoentatewt sti | [astm | «ap ertos «| RESane eicomecnn ted en | 4. | easing ine rosea] |2800ye| aun ‘ate Se | ae frou] + __[asetyes| sapernow os o. |Site my orn nod c 9, | has single memory to stove data and cose. “Tobie De 8051 Family of Microcontrollers MCS. ithe family name of fit micrcente. McS-St ie wih ther ROM sie sf 8051 microcontoter Tomi en ‘ 7 Inte corporation manatres varow micacotaler inssheand 1h configurations, Fach member of MCS. family ay vations por umber ‘able (1) i es the dierent micrcontles of ‘Ans: (on) Write an overview of 8081 microcontrollers. ‘The fears of #051 microcontrollers are mentioned below, They have 4096 bytes of inter progam meme Penance 0. 0. 2 “They have 128 byes of inter data meme “They poses fur regiter banks (G21, List out the important features of 6051 microcontroller along with ts applications. 128 weer dened sofware fags are avilable in 805) microontoles. “They pores one mierosecond instruction yee with 12 Me yal, “They bave 32 bidirectional UO hes organized as four 8: por, “They const wuliple made, bih-speed propane seri por. “They have l6-bit timerscounters. They poses two-level prictizedinferupt stctre. ‘They suppor fll depth rack fr subrtine rsa linkage and data storage “They have direct byte and bit address abi. “They spor signal overflow detection and patty computation eae, Applications For answer refer, Unit2, 23 WARNING: Xerox eto ERMAN At Aaa ody LUE LEGAL proceed ‘G23. List the applications. Ans: _asiomoble engineering, conv OlSysemy Fe The few o ® iy w o 051 microcontrollers, ot, nh. 230) Microcontllers are widely wed in consumer products, ‘one of miercon Micréconrollers ste used in robotics application ‘wherein mubple asks a’ ange to diferent modules Communication between the modales is handed by & ened tata og, User ag 3 inst [so] Retbier & ofa * rfo rtrd sf een, le: ait Sle Bs “The 051 microconolerisa0 pnd package Ic ep. The pin diagram of 8051 microcnzllerishows figure below EST, Figure: Pin Diagram 081 Mlrseeatoer ‘The 40 pins of 8081 microcontroller are configured as flows, Vo Pins ® The3210 pins 8081 are divided int four S-itparal- let ports PO, PL, P2 and P3 as shown in iu. ® Owtofthe 32pias,24 pis (., pins ofPO, P2 and P3) are ‘configured to perform atemae fuetions (UO futon, ees or data bus for higher ode memory and some ‘other special fictions) and the remaining § pins are ‘configured to perform only UO function Exel dene ano rn an evra Emory. Portt (Pins 8) The is 8 ar config sport Tepio of thipt cnet eco ony UO Aactsas an tc hidectona ht adcesabe at, Port.2 (inh TI e ‘The pint 21-28 fr a pare 10 poet (pore 2) ‘The ins of port 2 can be enffed as LO pins er they an te confined a her ander adress ines (ADS. ADIS)ofa two byte aT eT SE IRacteas an it bidretional bit addesabe po. Port (Pies 10-17) ‘he pins 10-17 are configured as Por 3, is also a biti- rectioal LO por ‘The pias of ort 3 canbe configured to faction as YO ins nd also to peform aerate fantom \ Power Supply-and Ground Fis, Pin-40(): Tht tea power supply pp. An external DC power supply of SV rs connected to this in Pin-20 (GND): This pins the ground pn of 8051 anit ‘sconectedtothesround inorder o round the eit (of 8051 misrocontoler Oselator Pine [TALI ahd XTAL2 ae the ipat nd out of ample. ‘To stn oxiltions inthe euit crystal mst be cone ected eseen XTALI (Pa-1§} and XTAL2 inp. Incase of eternal lock genestrtheoufpt of externa ‘oslsr (clock generator) connected to pins XTAL2 anal XTALI pins mus be couneted tthe ground 1a case of intemal lock generator, the XTAL pin it connected a inp tothe inverting pli of ull torcireuitand XTAL 2 pins connected tthe ouput of inverting split. Controt Pin-29 (YSEN -Program Store Enable) SEN isan ative low, output cont! sgn ‘When microcontroller repds the extemal propram ‘memory, the PSEN signal gts ata at every sit ‘oseillator periods ‘The PSEN signal serves asthe ral stobe to the external program memory This signal causes the extra program memory to enable its contents toe £05. SPECTRUM ALLIN.ONE JOURNAL FOR ENGINEERING STUDENTS * ‘Scanned with Comscanner

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