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Dic Lec 23 Economics v01

This lecture discusses the economics of integrated circuit design. It notes that non-recurring engineering costs (NREs) such as personnel costs, support costs, and prototype manufacturing costs must be recouped over the lifetime sales of the product. Recurring costs include manufacturing costs, support costs, and costs of sales. Design and development timelines can be 1.5-2 years for complex chips. Costs can be reduced through design reuse, purchasing intellectual property blocks, and focusing on well-defined market segments rather than general purpose chips.

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68 views16 pages

Dic Lec 23 Economics v01

This lecture discusses the economics of integrated circuit design. It notes that non-recurring engineering costs (NREs) such as personnel costs, support costs, and prototype manufacturing costs must be recouped over the lifetime sales of the product. Recurring costs include manufacturing costs, support costs, and costs of sales. Design and development timelines can be 1.5-2 years for complex chips. Costs can be reduced through design reuse, purchasing intellectual property blocks, and focusing on well-defined market segments rather than general purpose chips.

Uploaded by

OPTICALMIMOOFDM
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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‫ن ا ْلعِْلِم إِاَّل قَلِ ًيل‬ِ ‫وما أُوتِيتم‬

‫م‬
15 February 2020 1441 ‫ جمادى الثانية‬21

َ ُْ ََ

Digital IC Design

Lecture 23
IC Design Economics

Dr. Hesham A. Omran


Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
This lecture is mainly based on “CMOS VLSI Design”, 4th edition, by N. Weste and D. Harris and
its accompanying lecture notes
Introduction
❑ IC designer need to be able to predict the cost and the time to design an IC
▪ Otherwise you won’t make profit
❑ IC design costs
▪ Non-recurring (fixed) engineering costs (NREs)
▪ Recurring (variable) costs

23: IC Design Economics 2


Non-Recurring Engineering Costs (NREs)
❑ Non-Recurring costs: spent once during the design of an IC
▪ Engineering design costs
▪ Prototype manufacturing costs
❑ These costs are paid back over the total number of ICs sold (over the lifetime of the
product)
❑ The non-recurring costs can be viewed as an investment for which there is a required rate
of return (return on investment: ROI)
▪ Example: if $10M is invested in NRE for a chip, then $100M has to be generated for an
ROI of 10

23: IC Design Economics 3


Engineering Costs
1. Personnel costs (labor for design, simulation, layout, verification, documentation, etc.)
2. Support costs (computers, CAD tools, etc.)
❑ Example (USD per annum)

❑ Engineering costs can be drastically reduced by reusing modules or acquiring fully


completed modules from an intellectual property (IP) vendor

23: IC Design Economics 4


Prototype Manufacturing Costs
❑ The mask set cost (increases exponentially with technology scaling)
▪ 45nm mask set costs $5M
▪ Use MPW to reduces costs (MOSIS, Europractice)

23: IC Design Economics 5


Example: NREs
❑ You are starting a company to commercialize your brilliant research idea. Estimate the cost
to prototype a mixed-signal chip in a 45 nm process. Assume you have seven digital
designers ($70k + $30k per annum), three analog designers ($100k + $30k per annum), and
five support personnel ($40k + $20k per annum) and that the prototype takes two
fabrication runs and two years.

❑ The seven digital designers will cost 7 × ($70k + $30k + $10k + $10k) = $840k.
❑ The three analog designers will cost 3 × ($100k + $30k + $10k + $100k) = $720k.
❑ The five support personnel cost 5 × ($40k + $20k + $10k) = $350k.

23: IC Design Economics 6


Example: NREs
❑ One fabrication run with the back-end tools will cost $6M.
❑ Thus, the cost is $7.91M per year with one fab run.
❑ The total predicted cost here is nearly $16M.
❑ The venture capitalists providing this money will want a good return for their risk so you’d
better have a $100M market for your idea!

23: IC Design Economics 7


Example: NREs
❑ Typical chips at the 45 nm node require larger design teams and cost $20–$50M to design,
so the markets must be even larger
❑ You may see ways to improve this
▪ You can reduce the number of people and the labor cost
▪ You might reduce the CAD tool cost and the fabrication cost by doing multiproject
chips
• However, the latter approach will not get you to a pre-production version, because
issues such as yield and behavior across process variations will not be proved
• You may also worry about the protection of your IP
▪ Your best bet may be to find a product niche that can be filled using a more mature
and less expensive manufacturing process!

23: IC Design Economics 8


Recurring Costs
1. Manufacturing is a recurring cost: it recurs every time an IC is sold (includes fabrication
process, packaging, and testing)
2. Another component is the continuing cost to support the part from a technical viewpoint
3. Finally, “the cost of sales,” which is the marketing, sales force, and overhead costs
associated with selling each IC
❑ A few large companies such as Intel and Samsung have in-house manufacturing divisions at
state-of-the-art nodes
▪ Annual sales need to exceed about $10B to justify the investments at 45 nm, and this
figure continues to climb
▪ More companies at mature nodes (TI, ADI, Bosch, Agilent, etc.)
❑ Many fabless semiconductor companies outsource their manufacturing to a silicon foundry
such as TSMC, UMC, or GF

23: IC Design Economics 9


Recurring Costs: Manufacturing
❑ Rtotal = Rprocess + Rpackage + Rtest
▪ Rprocess = W/(N × Yw × Ypa)
▪ W = wafer cost ($500–$5000 depending on process and wafer size)
▪ N = gross die per wafer (the number of complete die on a wafer)
▪ Yw = die yield per wafer (should be ~70–90+% for moderate-sized die in a mature
process)
▪ Ypa = packaging yield (should be ~95–99%)

23: IC Design Economics 10


Example: Recurring Costs
❑ Suppose your startup seeks a return on investment of 5. The wafers cost $2000 and hold
400 gross die with a yield of 70%. If packaging, test, and fixed costs are negligible, how
much do you need to charge per chip to have a 60% profit margin? How many chips do you
need to sell to obtain a five-fold return on your $16M investment?

❑ Rtotal = Rprocess + Rpackage + Rtest = $2000/(400 × 0.7) = $7.14


❑ For a 60% margin, the chips are sold at $7.14/(1 – 0.6) = $17.86 with a profit of $10.72 per
unit.
❑ The desired ROI implies a profit of $16M × 5 = $80M.
❑ Thus, $80M/$10.72 = 7.4M chips must be sold.

23: IC Design Economics 11


Project Schedule
❑ Engineering costs depend on the complexity of the chip
❑ It is usually best to get a product first to market and then shrink the die when the product
becomes successful
❑ Optimizing without market feedback is usually a recipe for loss of market share or even
failure
❑ The best predictor of design schedule for a team is previous performance
❑ Gantt chart example for simple chip (1.5-2 years for a complex new chip):

23: IC Design Economics 12


Design Reuse and IP Blocks
❑ Design cost and time can be drastically reduced by design reuse or purchasing IP blocks
❑ Companies wish to reuse designs over several product generations by porting designs
between processes with minimum intervention
❑ If an IP block is available from a reputable source, purchasing the IP will normally be less
expensive than redesigning it yourself
❑ The IP can be hard (defined at mask level), firm (at gate level), or soft (at RTL level)
❑ Price sheets are not published, and licensing terms are generally kept confidential
(relationships are important)
❑ A very rough guideline: you may pay around $100k for a block such as a USB controller with
its software stack and test fixture
❑ Microprocessor cores may be offered on a 1% royalty basis (percentage of gross or net
revenues)

23: IC Design Economics 13


Thank you!

23: IC Design Economics 14


Typical SoC Costs
❑ Assumptions: Three years from start to break even for product, $150 thousand/engineer,
75 person company
❑ Some startup companies spend up to $50 million without reaching break-even!
❑ Simply, don’t do SoCs!
▪ Find a more focused market segment.

23: IC Design Economics [A Lean Fabless Semiconductor Business Model, Andreas Olofsson, 2012] 15
Advice for Silicon Startups
1. Don’t make semiconductors! Customers and investors are looking for solutions.
▪ If your innovation is another processor, IP block or even novel analog circuit you are in
for an uphill climb.
▪ Go after “well-defined and defensible market segments with whole products.”
▪ Develop solutions in silicon, an IC + software or services
2. Anything general purpose is special to no one.
▪ Not only will you simplify your challenge, more importantly you will learn quickly from
deeper interaction with customers in your focused segment.
3. Go from Powerpoint to prototype ASAP.
▪ A SPICE simulation, FPGA emulation or a discrete version of your eventual solution will
show credibility and help you stand out from the others.

23: IC Design Economics https://www.eetimes.com/author.asp?section_id=36&doc_id=1329123 16

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