VN5E025AJ-E

Single channel high-side driver with analog current sense

for automotive applications

Features
Max supply voltage VCC 41 V
Operating voltage range VCC 4.5 to 28 V
Max On-State resistance RON 25 mΩ
Current limitation (typ) ILIMH 60 A
PowerSSO-12
Off state supply current IS 2 µA(1)
1. Typical value with all loads connected. – Reverse battery protected
– Electrostatic discharge protection
■ General
Application
– Inrush current active management by
power limitation ■ All types of resistive, inductive and capacitive
– Very low stand-by current loads
– 3.0 V CMOS compatible inputs ■ Suitable as LED driver
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility Description
– In compliance with the 2002/95/EC The VN5E025AJ-E is a single channel high-side
european directive driver manufactured in the ST proprietary
– Very low current sense leakage VIPower M0-5 technology and housed in the tiny
■ Diagnostic functions PowerSSO-12 package. The VN5E025AJ-E is
– Proportional load current sense designed to drive 12 V automotive grounded
loads delivering protection, diagnostics and easy
– High current sense precision for wide
3 V and 5 V CMOS compatible interface with any
currents range
microcontroller.
– Current sense disable
– Off state openload detection The device integrates advanced protective
functions such as load current limitation, inrush
– Output short to VCC detection
and overload active management by power
– Overload and short to ground (power limitation, over-temperature shut-off with auto-
limitation) indication restart and over-voltage active clamp. A dedicated
– Thermal shutdown indication analog current sense pin is associated with every
■ Protections output channel in order to provide Ehnanced
– Undervoltage shutdown diagnostic functions including fast detection of
overload and short-circuit to ground through
– Overvoltage clamp
power limitation indication, over-temperature
– Load current limitation indication, short-circuit to VCC diagnosis and ON-
– Self limiting of fast thermal transients state and OFF-state open load detection.
– Protection against loss of ground and loss
The current sensing and diagnostic feedback of
of VCC
the whole device can be disabled by pulling the
– Over-temperature shutdown with CS_DIS pin high to allow sharing of the external
autorestart (thermal shutdown) sense resistor with other similar devices

September 2013 Doc ID 13106 Rev 5 1/37

www.st.com 1
Contents VN5E025AJ-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolue maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 24
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1 Short to VCC and OFF state open load detection . . . . . . . . . . . . . . . . . 27
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28

4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/37 Doc ID 13106 Rev 5

VN5E025AJ-E List of tables

List of tables

Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching characteristics (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Current sense (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Openload detection (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 13106 Rev 5 3/37

List of figures VN5E025AJ-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Openload Off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Delay response time between rising edge of ouput current and rising edge of current
sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. IOUT / ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. OFF-State Open Load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. TJ evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. Input clamp level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. On state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 28. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 29. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 33. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 34. Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 30
Figure 38. Thermal fitting model of a single channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 30
Figure 39. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 40. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4/37 Doc ID 13106 Rev 5

VN5E025AJ-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

VCC

Signal Clamp

Undervoltage Control & Diagnostic

Power
Clamp

IN DRIVER

VON
Limitation

Over Current
temp. Limitation

OFF State
Open load
CS_
DIS
VSENSEH

CS Current
Sense

OUT
OVERLOAD PROTECTION
LOGIC (ACTIVE POWER LIMITATION)

GND

Table 1. Pin function

Name Function

VCC Battery connection.

OUTPUT Power output.

Ground connection. Must be reverse battery protected by an external diode /

GND
resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls
INPUT
output switch state.

CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current.

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

Doc ID 13106 Rev 5 5/37

Block diagram and pin description VN5E025AJ-E

Figure 2. Configuration diagram (top view)

TAB = Vcc

Vcc 12 OUTPUT
1
GND 2 11 OUTPUT
INPUT 3 10 OUTPUT
CURRENT_SENSE 4 9 OUTPUT
CS_DIS 5 8 OUTPUT
6 7
Vcc OUTPUT

Table 2. Suggested connections for unused and not connected pins

Connection / pin Current sense N.C. Output Input CS_DIS

Floating Not allowed X X X X

Through 1kΩ Through 22kΩ Through 10kΩ Through 10kΩ
To ground X
resistor resistor resistor resistor

6/37 Doc ID 13106 Rev 5

VN5E025AJ-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

IS

VCC VF
VCC

IOUT
ICSD
CS_DIS OUTPUT
VCSD VOUT
IIN
INPUT ISENSE
CURRENT SENSE
VSENSE
VIN GND

IGND

Note: VF = VOUT - VCC during reverse battery condition.

2.1 Absolue maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC DC supply voltage 41 V

-VCC Reverse DC supply voltage 0.3 V
- IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse DC output current 20 A
IIN DC input current -1 to 10 mA
ICSD DC current sense disable input current -1 to 10 mA
-ICSENSE DC reverse CS pin current 200 mA
VCC-41 V
VCSENSE Current sense maximum voltage
+VCC V
Maximum switching energy (single pulse)
EMAX 140 mJ
(L=0.8mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )

Doc ID 13106 Rev 5 7/37

Electrical specifications VN5E025AJ-E

Table 3. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Electrostatic discharge
(Human Body Model: R=1.5KΩ; C=100pF)
- INPUT 4000 V
VESD - CURRENT SENSE 2000 V
- CS_DIS 4000 V
- OUTPUT 5000 V
- VCC 5000 V

VESD Charge device model (CDM-AEC-Q100-011) 750 V

Tj Junction operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C

2.2 Thermal data

Table 4. Thermal data
Symbol Parameter Max. value Unit

Rthj-case Thermal resistance junction-case 1.4 °C/W

Rthj-amb Thermal resistance junction-ambient See Figure 36 °C/W

8/37 Doc ID 13106 Rev 5

VN5E025AJ-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8V<VCC<28V; -40°C<Tj<150°C, unless otherwise
stated.

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC Operating supply voltage 4.5 13 28 V

VUSD Undervoltage shutdown 3.5 4.5 V
Undervoltage shutdown
VUSDhyst 0.5 V
hysteresis
IOUT= 3A; Tj=25°C 25 mΩ
RON On state resistance IOUT= 3A; Tj=150°C 50 mΩ
IOUT= 3A; VCC=5V; Tj=25°C 35 mΩ
Vclamp Clamp voltage IS= 20 mA 41 46 52 V
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V 2(1) 5(1) µA
IS Supply current
On State; VCC=13V; VIN=5V;
IOUT= 0A 1.5 3 mA
VIN=VOUT=0V; VCC=13V; Tj=25°C 0 0.01 3
IL(off1) Off state output current µA
VIN=VOUT=0V; VCC=13V; Tj=125°C 0 5
Output - VCC diode
VF -IOUT= 2A; Tj= 150°C 0.7 V
voltage
1. PowerMOS leakage included.

Table 6. Switching characteristics (VCC=13V, Tj=25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-On delay time RL= 4.3Ω (see Figure 6.) 15 µs

td(off) Turn-Off delay time RL= 4.3Ω (see Figure 6.) 40 µs
See
(dVOUT/dt)on Turn-On voltage slope RL= 4.3Ω V/µs
Figure 26
See
(dVOUT/dt)off Turn-Off voltage slope RL= 4.3Ω V/µs
Figure 28
Switching energy losses
WON RL= 4.3Ω (see Figure 6.) 0.4 mJ
during twon
Switching energy losses
WOFF RL= 4.3Ω (see Figure 6.) 0.5 mJ
during twoff

Doc ID 13106 Rev 5 9/37

Electrical specifications VN5E025AJ-E

Table 7. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low level voltage 0.9 V

IIL Low level input current VIN= 0.9V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN= 2.1V 10 µA
Input hysteresis
VI(hyst) 0.25 V
voltage
IIN= 1mA 5.5 7 V
VICL Input clamp voltage
IIN= -1mA -0.7 V
CS_DIS low level
VCSDL 0.9 V
voltage
Low level CS_DIS
ICSDL VCSD= 0.9V 1 µA
current
CS_DIS high level
VCSDH 2.1 V
voltage
High level CS_DIS
ICSDH VCSD= 2.1V 10 µA
current
CS_DIS hysteresis
VCSD(hyst) 0.25 V
voltage
ICSD=1mA 5.5 7 V
VCSCL CS_DIS clamp voltage
ICSD= -1mA -0.7 V

Table 8. Protection and diagnostics (1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC= 13V 43 60 85 A
IlimH DC short circuit current
5V<VCC<28V 85 A
Short circuit current
IlimL VCC= 13V; TR<Tj<TTSD 15 A
during thermal cycling
TTSD Shutdown temperature 150 175 200 °C
TR Reset temperature TRS + 1 TRS + 5 °C
TRS Thermal reset of status 135 °C
Thermal hysteresis
THYST 7 °C
(TTSD-TR)
Turn-Off output voltage
VDEMAG IOUT= 2A; VIN=0; L= 6mH VCC-41 VCC-46 VCC-52 V
clamp
IOUT= 0.1A
Output voltage drop
VON Tj= -40°C...150°C 25 mV
limitation
(see Figure 8)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device operates under
abnormal conditions this software must limit the duration and number of activation cycles.

10/37 Doc ID 13106 Rev 5

VN5E025AJ-E Electrical specifications

Table 9. Current sense (8V<VCC<18V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

IOUT= 0.05A, VSENSE=0.5V,

KLED IOUT/ISENSE VCSD=0V
1370 3180 4930
Tj= -40°C...150°C
IOUT= 0.5A; VSENSE=0.5V;
K0 IOUT/ISENSE VCSD=0V;
1990 3050 4120
Tj= -40°C...150°C
IOUT= 2A; VSENSE=4V; VCSD=0V;
K1 IOUT/ISENSE Tj= -40°C...150°C 2100 2860 3840
Tj= 25°C...150°C 2220 2860 3500
IOUT=2A; VSENSE= 4V;
Current sense ratio
dK1/K1(1) VCSD=0V; -10 10 %
drift
TJ= -40 °C to 150 °C
IOUT= 3A; VSENSE=4V; VCSD=0V;
K2 IOUT/ISENSE Tj= -40°C...150°C 2300 2850 3520
Tj=25°C...150°C 2420 2850 3300
IOUT=3 A; VSENSE= 4 V;
Current sense ratio
dK2/K2(1) VCSD=0V; -7 7 %
drift
TJ= -40 °C to 150 °C
IOUT= 10A; VSENSE=4V; VCSD=0V;
K3 IOUT/ISENSE Tj= -40°C...150°C 2690 2830 3060
Tj=25°C...150°C 2700 2830 3020
IOUT= 10 A; VSENSE= 4 V;
Current sense ratio
dK3/K3(1) VCSD=0V; -4 4 %
drift
TJ= -40 °C to 150 °C
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj=-40°C...150°C 0 1 µA
Analog sense VCSD=0V; VIN=5V; Tj=-40°C...150°C 0 2 µA
ISENSE0
leakage current
IOUT=2A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj=-40°C...150°C 0 1 µA
Open load ON state
VIN = 5V, 8V<VCC<18V
IOL current detection 5 30 mA
ISENSE= 5 µA
threshold
Max analog sense
VSENSE IOUT= 3A; VCSD= 0V 5
output voltage
Analog sense output V
VSENSEH(2) voltage in fault VCC= 13V; RSENSE= 3.9KΩ 8
condition
Analog sense output
ISENSEH(2) current in fault VCC= 13V; VSENSE= 5V 9 mA
condition

Doc ID 13106 Rev 5 11/37

Electrical specifications VN5E025AJ-E

Table 9. Current sense (8V<VCC<18V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Delay response time VSENSE<4V, 0.5<Iout<10A

tDSENSE1H from falling edge of ISENSE=90% of ISENSE max 40 100
CS_DIS pin (see Figure 4)

Delay response time VSENSE<4V, 0.5<Iout<10A

tDSENSE1L from rising edge of ISENSE=10% of ISENSE max 5 20
CS_DIS pin (see Figure 4)

Delay response time VSENSE<4V, 0.5<Iout<10A

tDSENSE2H from rising edge of ISENSE=90% of ISENSE max 80 300
INPUT pin (see Figure 4) µs

Delay response time VSENSE < 4V,

between rising edge ISENSE = 90% of ISENSEMAX,
ΔtDSENSE2H of output current 110
IOUT = 90% of IOUTMAX
and rising edge of
current sense IOUTMAX= 3A (see Figure 7)

Delay response time VSENSE<4V, 0.5<Iout<10A

tDSENSE2L from falling edge of ISENSE=10% of ISENSE max 80 250
INPUT pin (see Figure 4)
1. Parameter guaranteed by design, it is not tested.
2. Fault condition includes: power limitation, overtemperature and open load OFF state detection.

Table 10. Openload detection (8V<VCC<18V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Openload Off state

VOL voltage detection VIN = 0V 2 4 V
threshold
Output short circuit to
tDSTKON VCC detection delay at See Figure 5. 180 1200 µs
turn off
Off state output current at VIN=0V; VSENSE=0V
IL(off2)r -120 0 µA
VOUT = 4V VOUT rising from 0V to 4V

Off state output current at VIN=0V; VSENSE=VSENSEH

IL(off2)f -50 90 µA
VOUT = 2V VOUT falling from VCC to 2V
Delay response from
output rising edge to VOUT= 4 V; VIN= 0V
td_vol 20 µs
VSENSE rising edge in VSENSE= 90% of VSENSEH
open load

12/37 Doc ID 13106 Rev 5

VN5E025AJ-E Electrical specifications

Figure 4. Current sense delay characteristics

INPUT
CS_DIS

LOAD CURRENT

SENSE CURRENT

tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L

Figure 5. Openload Off-state delay timing

OUTPUT STUCK TO VCC

VIN
VOUT > VOL

VSENSEH

VCS

tDSTKON

Figure 6. Switching characteristics

VOUT
tWon tWoff

90%
80%

dVOUT/dt(on) dVOUT/dt(off)

tr 10% tf
t

INPUT
td(on) td(off)

Doc ID 13106 Rev 5 13/37

Electrical specifications VN5E025AJ-E

Figure 7. Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)

VIN

ΔtDSENSE2H

IOUT
IOUTMAX

90% IOUTMAX

ISENSE ISENSEMAX

90% ISENSEMAX

Figure 8. Output voltage drop limitation

Vcc-Vout

Tj=150oC Tj=25oC

Tj=-40oC

Von

Iout
Von/Ron(T)

14/37 Doc ID 13106 Rev 5

VN5E025AJ-E Electrical specifications

Figure 9. IOUT / ISENSE vs IOUT

Iout / Isense

4200

max Tj = -40 °C to 150 °C

3700

3200
max Tj = 25 °C to 150 °C

typical value

2700
min Tj = 25 °C to 150 °C

2200
min Tj = -40 °C to 150 °C

1700
2 3 4 5 6 7 8 9 10

IOUT (A)

Figure 10. Maximum current sense ratio drift vs load current

dk/k(%)
10

-5

-10
2 3 4 5 6 7 8 9 10
IOUT (A)

Note: Parameter guaranteed by design; it is not tested.

Doc ID 13106 Rev 5 15/37

Electrical specifications VN5E025AJ-E

Table 11. Truth table

Conditions Input Output Sense (VCSD=0V)(1)

L L 0
Normal operation
H H Nominal
L L 0
Overtemperature
H L VSENSEH
L L 0
Undervoltage
H L 0
H X Nominal
(no power limitation)
Overload
H Cycling VSENSEH
(power limitation)
Short circuit to GND L L 0
(power limitation) H L VSENSEH
Open load OFF state
L H VSENSEH
(with external pull-up)
Short circuit to VCC
L H VSENSEH
(external pull-up
H H < Nominal
disconnected)
Negative output voltage
L L 0
clamp
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.

16/37 Doc ID 13106 Rev 5

VN5E025AJ-E Electrical specifications

Table 12. Electrical transient requirements

Burst cycle/pulse
ISO 7637-2: Test levels(1) Number of
repetition time Delays and
2004(E) pulses or
Impedance
Test pulse test times
III IV Min. Max.

1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω

2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω
3a -100V -150V 1h 90ms 100ms 0.1µs, 50Ω
3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω
4 -6V -7V 1 pulse 100ms, 0.01Ω
(2)
5b +65V +87V 1 pulse 400ms, 2Ω

ISO 7637-2: Test level results

2004E
Test pulse III VI

1 C C
2a C C
3a C C
3b C C
4 C C
5b(2) C C

Class Contents

C All functions of the device performed as designed after exposure to disturbance.

One or more functions of the device did not perform as designed after exposure to
E
disturbance and cannot be returned to proper operation without replacing the device.
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.

Doc ID 13106 Rev 5 17/37

Electrical specifications VN5E025AJ-E

2.4 Waveforms

Figure 11. Normal operation

Normal operation

INPUT
Nominal load Nominal load

IOUT

VSENSE

VCS_DIS

Figure 12. Overload or Short to GND

Overload or Short to GND

INPUT
Power Limitation
ILimH > Thermal cycling
ILimL >
IOUT

VSENSE

VCS_DIS

18/37 Doc ID 13106 Rev 5

VN5E025AJ-E Electrical specifications

Figure 13. Intermittent Overload

Intermittent Overload

INPUT
Overload
ILimH >
Nominal load
ILimL >
IOUT
VSENSEH>

VSENSE

VCS_DIS

Figure 14. OFF-State Open Load with external circuitry

OFF-State Open Load

with external circutry

INPUT

VOUT > VOL

VOL
VOUT

IOUT
VSENSEH >
tDSTK(on)
VSENSE

VCS_DIS

Doc ID 13106 Rev 5 19/37

Electrical specifications VN5E025AJ-E

Figure 15. Short to VCC

Short to VCC
Resistive Hard
Short to VCC Short to VCC

VOUT > VOL

VOL
VOUT

IOUT

tDSTK(on) tDSTK(on)

VCS_DIS

Figure 16. TJ evolution in Overload or Short to GND

TJ evolution in
Overload or Short to GND

INPUT
Self-limitation of fast thermal transients TTSD
THYST
TR

TJ_START
TJ
Power Limitation
ILimH >

< ILimL

IOUT

20/37 Doc ID 13106 Rev 5

VN5E025AJ-E Electrical specifications

2.5 Electrical characteristics curves

Figure 17. Off state output current Figure 18. High level input current
Iloff (nA) Iih (µA)
1500 5

4,5
Vin=2.1V
1200 Off State
Vcc=13V 4
Vin=Vout=0V
3,5
900

600
2,5

2
300
1,5

0 1
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 19. Input clamp level Figure 20. Input low level
Vicl (V) Vil (V)
7 2

1,8
lin=1mA
6,8 1,6

1,4

6,6 1,2

6,4 0,8

0,6

6,2 0,4

0,2

6 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 21. Input high level Figure 22. Input hysteresis voltage
Vih (V) Vihyst (V)
4 1

0,9
3,5
0,8
3
0,7
2,5
0,6

2 0,5

0,4
1,5
0,3
1
0,2
0,5
0,1

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Doc ID 13106 Rev 5 21/37

Electrical specifications VN5E025AJ-E

Figure 23. On state resistance vs Tcase Figure 24. On state resistance vs VCC

Ron (mOhm) Ron (mOhm)

80 60

50
Iout= 3A
60
Vcc=13V
40 Tc=150°C
Tc=125°C

40 30

Tc=25°C
20

20 Tc=-40°C

10

0 0
-50 -25 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 40

Tc (°C) Vcc (V)

Figure 25. Undervoltage shutdown Figure 26. Turn-On voltage slope

Vusd (V) (dVout/dt )On (V/ms)

8 700

7
600
Vcc=13V
6 RI=4.3 Ohm
500

5
400
4

300
3

200
2

1 100

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 27. ILIMH vs Tcase Figure 28. Turn-Off voltage slope

Ilimh (A) (dVout/dt )Off (V/ms)

80 400

350
Vcc=13V Vcc=13V
300 RI= 4.3 Ohm
70

250

60 200

150

50 100

50

40 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175

Tc (°C) Tc (°C)

22/37 Doc ID 13106 Rev 5

VN5E025AJ-E Electrical specifications

Figure 29. CS_DIS high level voltage Figure 30. CS_DIS clamp voltage
Vcsdh (V) Vcsdcl(V)
4 10

3,5 9
Iin = 1 mA
3 8

2,5 7

2 6

1,5 5

1 4

0,5 3

0 2
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 31. CS_DIS low level voltage

Vcsdl (V)
3

2,5

1,5

0,5

0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)

Doc ID 13106 Rev 5 23/37

Application information VN5E025AJ-E

3 Application information

Figure 32. Application schematic

+5V

VCC

Rprot CS_DIS

Dld

ΜCU Rprot IINPUT

OUTPUT

Rprot CURRENT SENSE

GND

RSENSE RGND
VGND DGND
Cext

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1: resistor in the ground line (RGND only)

This can be used with any type of load.
The following show how to dimension the RGND resistor:
1. RGND ≤ 600mV / (IS(on)max)
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC<0 during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that, if the microprocessor ground is not shared by the device ground, then the
RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output

24/37 Doc ID 13106 Rev 5

VN5E025AJ-E Application information

values. This shift varies depending on how many devices are ON in the case of several high
side drivers sharing the same RGND.
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.

3.1.2 Solution 2: diode (DGND) in the ground line

Note that a resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives
an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift not varies if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent
the µC I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ
Recommended values: Rprot =10kΩ, CEXT=10nF.

Doc ID 13106 Rev 5 25/37

Application information VN5E025AJ-E

3.4 Current sense and diagnostic

The current sense pin performs a double function (see Figure 33: Current sense and
diagnostic):
● Current mirror of the load current in normal operation, delivering a current
proportional to the load one according to a know ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5V
minimum (see parameter VSENSE in Table 9: Current sense (8V<VCC<18V)). The
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8V<VCC<18V)).

● Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a

maximum current ISENSEH in case of the following fault conditions (refer to Truth table):
– Power limitation activation
– Over-temperature
– Short to VCC in OFF state
– Open load in OFF state with additional external components.

A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.

Figure 33. Current sense and diagnostic

VPU
VBAT

VCC

Main MOSn
41V
PU_CMD

Overtemperature
IOUT/KX
RPU
+
OL OFF
ISENSEH -
VOL ILoff2r
Pwr_Lim
CS_DIS OUTn ILoff2f
INPUTn

VSENSEH
CURRENT
SENSEn GND Load
RPROT RPD

To uC ADC
RSENSE
VSENSE

26/37 Doc ID 13106 Rev 5

VN5E025AJ-E Application information

3.4.1 Short to VCC and OFF state open load detection

Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off state. Small or no current is delivered by the current sense
during the on state depending on the nature of the short circuit.

OFF state open load with external circuitry

Detection of an open load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module stand-by mode in order to avoid the
overall stand-by current consumption to increase in normal conditions, i.e. when load is
connected.
An external pull down resistor RPD connected between output and GND is mandatory to
avoid misdetection in case of floating outputs in off state (see Figure 33: Current sense and
diagnostic).
RPD must be selected in order to ensure VOUT < VOLmin unless pulled up by the external
circuitry:

VOUT Pull − up _ OFF

= RPD ⋅ I L ( off 2) f < VOL min = 2V

RPD ≤ 22 KΩ is recommended.
For proper open load detection in off state, the external pull-up resistor must be selected
according to the following formula:

RPD ⋅ VPU − RPU ⋅ RPD ⋅ I L ( off 2) r

VOUT = > VOL max = 4V
Pull − up _ ON RPU + RPD

For the values of VOLmin ,VOLmax, IL(off2)r and IL(off2)f see Table 10: Openload detection
(8V<VCC<18V).

Doc ID 13106 Rev 5 27/37

Application information VN5E025AJ-E

3.5 Maximum demagnetization energy (VCC = 13.5V)

Figure 34. Maximum turn off current versus inductance

100

B A

C
10
I (A)

1
0,1 1 L (mH) 10 100

A: Tjstart = 150°C single pulse

B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse

VIN, IL

Demagnetization Demagnetization Demagnetization

Note: Values are generated with RL = 0Ω.

In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.

28/37 Doc ID 13106 Rev 5

VN5E025AJ-E Package and PC board thermal data

4 Package and PC board thermal data

4.1 PowerSSO-12 thermal data

Figure 35. PowerSSO-12 PC board

Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).

Figure 36. Rthj-amb vs PCB copper area in open box free air condition

RTHj_amb( °C/ W)

65
60
55
50
45
40
35
30
0 2 4 6 8 10
PCB Cu heat sink area ( cm^ 2)

Doc ID 13106 Rev 5 29/37

Package and PC board thermal data VN5E025AJ-E

Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse

ZTH (° C/ W)
100 Footprint

2 cm2

8 cm2

10

0,1
0,0001 0,001 0,01 0,1 1 10 100 1000
Time ( s)

Figure 38. Thermal fitting model of a single channel HSD in PowerSSO-12

Equation 1: pulse calculation formula:

Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tp ⁄ T

30/37 Doc ID 13106 Rev 5

VN5E025AJ-E Package and PC board thermal data

Table 13. Thermal parameter

Area/island (cm2) Footprint 2 8

R1 (°C/W) 0.3

R2 (°C/W) 1.3

R3 (°C/W) 4

R4 (°C/W) 8 8 7

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1 (W.s/°C) 0.001

C2 (W.s/°C) 0.003

C3 (W.s/°C) 0.05

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

Doc ID 13106 Rev 5 31/37

Package and packing information VN5E025AJ-E

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of Second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.

5.2 PowerSSO-12 mechanical data

Figure 39. PowerSSO-12 package dimensions

32/37 Doc ID 13106 Rev 5

VN5E025AJ-E Package and packing information

Table 14. PowerSSO-12 mechanical data

Millimeters
Dimension
Min. Typ. Max.

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e 0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

k 0º 8º

X 1.900 2.500

Y 3.600 4.200

ddd 0.100

Doc ID 13106 Rev 5 33/37

Package and packing information VN5E025AJ-E

5.3 Packing information

Figure 40. PowerSSO-12 tube shipment (no suffix)

B
C Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A 1.85
A B 6.75
C (± 0.1) 0.6

All dimensions are in mm.

Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty 2500

Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
End
All dimensions are in mm.

Start

Top No components Components No components

cover
tape 500mm min
500mm min
Empty components pockets
saled with cover tape.

User direction of feed

34/37 Doc ID 13106 Rev 5

VN5E025AJ-E Order codes

6 Order codes

Table 15. Device summary

Order codes
Package
Tube Tape and reel
PowerSSO-12 Root part number 2 VN5E025AJTR-E

Doc ID 13106 Rev 5 35/37

Revision history VN5E025AJ-E

7 Revision history

Table 16. Document revision history

Date Revision Changes

24-Jan-2006 1 Initial release.

Reformatted.
15-Jan-2007 2
Section 4.1 restructured.
Document reformatted and restructured.
Changed max. operating voltage value from 36V to 28V.
Changed Description on cover page.
Table 6.: Switching characteristics (VCC=13V, Tj=25°C): added
typical values.
Updated Table 9.: Current sense (8V<VCC<18V):
– changed VCC max. value from 16 V to 18 V
– added K, dK/K values
– added IOL parameter
– changed VSENSEH typical value from 9 V to 8 V.
– changed ISENSEH typical value from 8 mA to 9 mA.
– changed tDSENSE1H typical value from 50 µs to 40 µs.
01-Apr-2008 3
– changed tDSENSE2L typical value from 100 µs to 80 µs.
– changed tDSENSE2H typical value from 70 µs to 80 µs
– added ΔtDSENSE2H parameter
Updated Table 10.: Openload detection (8V<VCC<18V):
– added IL(off2)r, IL(off2)f and td_vol parameters
Added Figure 9.: IOUT / ISENSE vs IOUT.
Added Figure 10.: Maximum current sense ratio drift vs load current
Added Section 2.4: Waveforms.
Added Section 2.5: Electrical characteristics curves.
Updated Section 3: Application information:
– added Section 3.4: Current sense and diagnostic
Added Section 4.1: PowerSSO-12 thermal data.
10-May-2010 4 Updated Figure 9: IOUT / ISENSE vs IOUT
20-Sep-2013 5 Updated disclaimer.

36/37 Doc ID 13106 Rev 5

VN5E025AJ-E

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE
SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2013 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com

Doc ID 13106 Rev 5 37/37