4364 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO.

4, JULY/AUGUST 2023

A Level Enhanced Nearest Level Control for Modular

Multilevel Converter Without Using Sensors
Hari Babu Gobburi , Student Member, IEEE, Vijay B. Borghate , Senior Member, IEEE,
and Prafullachandra M. Meshram , Member, IEEE

Abstract—Modular Multilevel Converters (MMCs) have gained widely studied in different aspects since from its invention. The
popularity in high and medium power applications. The nearest mathematical model is presented in [5]. MMC has fault tolerant
level control (NLC) is the suitable modulation technique as it offers capability and, to enhance this, hybrid topologies with the mixed
low switching loss and easier implementation compared to the
carrier-based pulse width modulation techniques. However, the combination of different type of SMs are detailed in [6] and
harmonic performance is poor in case of MMC with low number of [7]. A circulating current control technique is discussed in [8].
submodules (SMs). Apart from this, the SM capacitor voltage bal- Nevertheless, MMC needs modulation methods. These are of
ance control is crucial, which demands expensive voltage and cur- two types, classified based on switching frequency. The carrier-
rent measurement boards with conventional balancing approaches. based pulse width modulation (CPWM) techniques such as
This article presents a level enhanced NLC method for MMC. The
proposed method derives the necessary switching patterns using phase shifted carrier PWM (PSCPWM) and Level shifted PWM
simple logical operations based on the inherent property of NLC (LSPWM) are the high switching frequency methods. With these
reference waveform. By which, equal insertion and bypass periods methods, MMCs generate N+1 and 2N+1 output levels with N
are ensured for the SM capacitors and eliminated the voltage and SMs per arm based on the carrier position between the upper and
current sensors needed for the capacitor voltage balance control. lower arms [9], [10], [11], [12]. However, the PWM operation
Also, the output voltage level number increases to 2N+1 (where N is
the number of SMs per arm) with reduced half step size. Hence, the leads to high switching loss. A step wave modulation method
quality of ac output waveform can be improved with low number (low switching frequency method) introduced in [13] and [14]
of SMs. The proposed method is verified by simulations in MAT- offers low switching loss and enhances the output voltage levels
LAB/SIMULINK software, and for the validation, experimental to 2N+1. Nonetheless, MMCs must be embedded with voltage
results are presented.
and current sensors for the capacitor voltage balance control [9],
Index Terms—2N+1 self-voltage balancing method, modular [10], [11], [12], [13], [14]. Therefore, the cost and complexity
multilevel converter (MMC), nearest level control (NLC), total increase sharply with the increase in SM number. In recent years,
harmonic distortion. the research on MMC is carried further to eliminate or minimize
the sensors requirement as follows.
I. INTRODUCTION The PWM pulses are exchanged among the SMs in [15]
ODULAR Multilevel Converter (MMC) was proposed and [16]. The suitable switching patterns which eliminate the
M first by Lesnicar and Marquardt in 2003 [1]. MMC
can be found in several applications ranging from medium to
need of voltage and current sensors are found based on rank
calculation and self-balancing ability of two and three level
high power such as motor drives, renewable energy generation MMCs [17]. A self-balanced MMC structure is proposed in
systems, high voltage dc transmission and STATCOM, etc., [2], [18]. Each individual SM capacitor voltage is controlled through
[3], [4]. a PI controller to follow the reference value [19]. Estimation
On account of research interest by several authors and at- technique is proposed which eliminates the need of voltage
tractive characteristics like modularity and scalability, MMC is sensors [20]. In all of these, MMC is controlled using N+1
modulation. A PWM based 2N+1 voltage balancing method
Manuscript received 28 October 2022; revised 24 February 2023; accepted 17 which improves the harmonic performance is proposed without
April 2023. Date of publication 25 April 2023; date of current version 19 July voltage and current sensors in [21]. To the best of author’s
2023. Paper 2022-IPCC-1207.R1, presented at the 2022 IEEE IAS Global Con-
ference on Emerging Technologies, Arad, Romania, May 20–22, and approved knowledge, none of the sensorless methods in the literature
for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the have addressed the level enhancement (2N+1 level) with low
Industrial Power Converter Committee of the IEEE Industry Applications Soci- switching frequency modulation technique.
ety [DOI: 10.1109/GlobConET53749.2022.9872328]. (Corresponding author :
Hari Babu Gobburi.) By addressing the aforementioned research gap, a level en-
Hari Babu Gobburi and Vijay B. Borghate are with the Department of Electri- hanced voltage balancing method based on nearest level control
cal Engineering, Visvesvaraya National Institute of Technology, Nagpur 440010, (NLC) is proposed without any voltage and current sensors. The
India (e-mail: [email protected]; [email protected]).
Prafullachandra M. Meshram is with the Department of Electrical Engi- sensors requirement is eliminated by considering the inherent
neering, Yeshwantrao Chavan College of Engineering, Nagpur 441110, India feature of NLC reference waveform. By this feature, the voltage
(e-mail: [email protected]). levels at equidistance from the reference axis will have identical
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIA.2023.3270113. durations. Therefore, insertion of suitable switching patterns
Digital Object Identifier 10.1109/TIA.2023.3270113 will ensure the equal duty cycles for all SMs in the phase leg.

0093-9994 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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GOBBURI et al.: LEVEL ENHANCED NEAREST LEVEL CONTROL FOR MODULAR MULTILEVEL CONVERTER 4365

Vl − Vu
Va = (2)
2
where ω, 0 < m <1, Vu , Vl, & Va denote the angular frequency,
modulation index, voltage across upper and lower arm, and
phase-a output voltage, respectively. In MMC, arm voltages
follow the SMs insertion and are given by (3).

Nu = N2 [1 − m sin (ωt)]
(3)
Nl = N2 [1 + m sin (ωt)]
where Nu & Nl represent the upper and lower arm SMs insertion
indices, respectively. However, these must be modified accord-
ing to the type of modulation technique. This paper implemented
the nearest level control (NLC). The NLC is a rounding method
by which the number of SMs to be inserted is decided by
performing round function on the sampled sine wave reference.
For N+1 modulation, the inserted number of SMs from the upper
and lower arms are given by [2] as follows.
 
Fig. 1. Single phase MMC structure. Nu = round0.5 N2 [1 − m sin (ωt)]
  (4)
Nl = round0.5 N2 [1 + m sin (ωt)]
These switching patterns can be derived using logical operations
in much simpler way than presented in [22], and without any The conventional round function (round0.5 (y)) rounds down
rank calculation as required in [17]. The proposed method is not or rounds up the decimal fraction number y by 0.5 to the nearest
required to generate any carrier waveforms. Hence, it offers low integer. For example, round0.5 (1.6) = 2 and round0.5 (−1.6) =
switching loss. No estimation and PI controller is required. It −2. With this function, the instants of step changes in the upper
also does not need to calculate the optimal firing angles as in and lower arm voltages are same [2]. For the level enhancement
[14]. Apart from keeping the conventional topology, the output with same SM count, the moments of step changes in the arm
voltage level number enhances to 2N+1 with N SMs per arm voltages must be different and, in this case, the inserted number
similar to the balancing methods discussed in [10], [11], [12], of SMs from the upper and lower arms are given by [13] as
[13], [14] and [21]. Therefore, the total harmonic distortion follows.
(THD) and hence the quality of output waveform gets improved  
Nu = round0.25 N2 [1 − m sin (ωt)]
substantially with low number of SMs.   (5)
The remaining part of this paper is organized as follows. Nl = round0.25 N2 [1 + m sin (ωt)]
Section II presents the fundamentals of MMC and principles The modified round function ( round0.25 (y)) rounds down
of proposed 2N+1 modulation. Section III details the proposed or rounds up the decimal fraction number y by 0.25 to the
method followed by generalization of the method in Section IV. nearest whole number. For example, round0.25 (1.26) = 1.5
Section V validates the proposed method by simulation and and round0.5 (−1.24) = −1. The control diagrams for N+1
experimental results. The conclusions are drawn in Section VI. and 2N+1 modulation are illustrated in Fig. 2(a) and (b), re-
spectively. The corresponding output voltage waveforms are
II. FUNDAMENTALS OF MMC AND PRINCIPLES OF PROPOSED shown in Fig. 2(c) and (d), respectively. The common thing
2N+1 METHOD observed from these waveforms is the appearance of integer
The Fig. 1 shows the single-phase MMC structure. It has levels. Therefore, the proposed method derives the necessary
two arms denoted as upper and lower arm. There are total switching patterns for the integer levels and then inserts the
2N number of two-level half-bridge submodules (HBSMs) and, same for non-integer levels in such a way that the total insertion
cascade connection of N SMs in series with the arm inductor of SMs at integer and non-integer levels will be N and N+1,
(L) forms into one arm. Each HBSM is having a pair of IGBT respectively. These switching patterns will also ensure the equal
switches and one capacitor (C). These two switches operate duty cycles for the all SMs in the phase leg and increases the
in complementary manner for the insertion as well as bypass output voltage level number to 2N+1 with N SMs per arm. The
of SM capacitor. During this, the SM capacitor voltage (Vc ) deriving process of necessary switching patterns for the integer
must be maintained at Vdc /N [1]. Where Vdc designates the levels is as follows.
DC input voltage. Modulation methods are required for MMC Regardless of N+1 and 2N+1 output waveforms shown in
operation. By this technique, SMs are inserted and arm voltages Fig. 2(c) and (d), the integer voltage levels (+Vdc /2 and −Vdc /2
are controlled for the generation of output voltage [12]. These levels) are at equidistance from the reference axis and their
are given by (1) & (2). durations are equal. To generate these, the SMs can be in-
 serted and bypassed without giving attention to the status of
Vu = V2dc [1 − m sin (ωt)] capacitor voltages and arm current direction [2] and [13]. The
(1)
Vl = V2dc [1 + m sin (ωt)] corresponding switching states of the upper and lower arm SMs
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4366 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023

Fig. 3. (a) Lower arm NLC reference with N = 4 and (b) switching pattern
deriving process for level 3 using bit rotation operation.

given by (7).
 
N N!
mkl = = (6)
Fig. 2. (a) Control diagram of N+1 modulation, (b) control diagram of 2N+1 k k! (N − k)!
modulation, (c) output waveform with N+1 modulation and (d) output waveform
with 2N+1 modulation. where k represents the level index from 0 to N.
⎡ ⎤
⎢ ⎥
⎢1 1 1 1⎥
are in complementary to each other and they ensure identical ⎢ ⎥
⎢0 1 1 1⎥
insertion and bypass periods for the SM capacitors in the phase ⎢ ⎥
⎢1 0 1 1⎥
leg. Similarly, other integer voltage levels at equidistance from ⎢ ⎥
⎢1 1 0 1⎥
the reference axis are having identical durations. ⎢ ⎥
⎢1 1 1 0⎥
⎢ ⎥  5
In order to ensure identical period of insertion and bypass ⎢0 0 1 1⎥ ⎡ ⎤
for the SM capacitors at these levels, the switching states for ⎢ ⎥ Y4l5 1×4 ← Level 4
⎢0 1 0 1⎥ ⎢ ⎥
⎢ ⎥ Y3l5 4×4 ← Level 3
the upper and lower arm SMs at each integer voltage level ⎢0 1 1 0⎥ ⎢ ⎥
Yl = ⎢
5
⎥=⎢ Y2l5 6×4
⎥ ← Level 2 (7)
must be in complementary to each other. With this, the need of ⎢1 0 0 1⎥ ⎢ ⎥
voltage and current sensors can be eliminated for the capacitor ⎢ ⎥ ⎣ Y1l5 4×4
⎦ ← Level 1
⎢1 0 1 0⎥
voltage balance control. In the next section, the process is ⎢ ⎥ Y0l 1×4 ← Level 0
⎢1 1 0 0⎥
described for N = 4. ⎢ ⎥
⎢0 0 0 1⎥
⎢ ⎥
⎢0 0 1 0⎥
⎢ ⎥
III. PROPOSED 2N+1 VOLTAGE BALANCING METHOD WITH ⎢0 1 0 0⎥
⎢ ⎥
NEAREST LEVEL CONTROL ⎢1 0 0 0⎥
⎢ ⎥
⎣0 0 0 0⎦
The NLC is a reduced switching frequency method offers low 
switching loss as well as easier implementation. The required Lower arm
switching patterns which eliminate the need of voltage and cur-
rent sensors for 2N+1 modulation are same as N+1 modulation. In (7), Yl5 contains the total number of switching combi-
Therefore, the proposed method begins with N+1 modulation nations corresponding to lower arm. Y4l5 , Y3l5 , Y2l5 , Y1l5 and Y0l5
as follows. are the matrices consists of the possible number of switching
combinations for each individual level obtained based on level
index. The superscript ‘5’ indicates the number of levels in
A. N+1 Modulation the reference waveform. The extraction process of required
For N+1 output levels, the proposed method performs the switching patterns for each individual level is as follows.
complementary operation between the upper and lower arms as Level 4 & Level 0: The Level 4 is indexed with the number 4.
discussed earlier. For the understanding of process, the lower It means, insert all four SMs. And for Level 0, bypass all four
arm is considered. With N = 4, the lower arm reference wave- SMs. With these patterns, SMs in lower arm get equal chance
form is depicted in Fig. 3(a). It has 5 levels denoted as Level 0, of insertion and bypass at Level 4 and Level 0, respectively.
Level 1, Level 2, Level 3 and Level 4 as per the index number. The Therefore, the fundamental principle of proposed method is
Level 2 is the center level positioned on the reference axis. With to insert the complementary switching patterns for the levels
respect to this, the Level 4 & Level 3 are at equidistance from at equidistance from the reference axis. Based on this, the
Level 0 & Level 1, respectively. The total number of possible switching patterns for Level 3 and Level 1 are derived as follows.
switching combinations with N SMs per arm are 2N i.e., 24 = Level 3 & Level 1: For Level 3, any three SMs from the lower
16 (with N = 4). Out of these, the possible number of switching arm can be inserted. With each pattern corresponding to this,
states for each individual level are calculated as per (6) and are only 3 SMs out of 4 are in the insertion mode. In order to ensure
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GOBBURI et al.: LEVEL ENHANCED NEAREST LEVEL CONTROL FOR MODULAR MULTILEVEL CONVERTER 4367

can be observed from the duty cycles of the lower arm SMs
depicted in Fig. 6. Thus, the same switching patterns can be
utilized for 2N+1 modulation as follows.

B. 2N+1 Modulation
With N = 4, the inserted number of SMs for 2N+1 modu-
lation given by (5) are shown in Fig. 7. These are having both
integer and non-integer levels. For integer levels, the switching
patterns derived for N+1 modulation are inserted. Whereas, for
non-integer levels, SMs in fraction number can’t be inserted as
there is no switching mode (PWM mode) operation with NLC
modulation. Therefore, it is required to round off the fraction
number to the nearest whole integer using conventional round
function. Upon doing this, the number of SMs to be inserted for
the non-integer levels can be obtained. For example, round0.5
(2.5) = 3. It means, 3 SMs are to be inserted. Therefore, the
Fig. 4. SMs insertion for N+1 levels with N = 4. (a) For lower arm and switching patterns inserted for Level 3 can be used for generating
(b) for upper arm. non-integer Level 2.5.
The same can be followed for the all non-integer levels except
for Level 1.5. Though the round0.5 (1.5) = 2, the switching
equal chance of insertion for all 4 SMs, four switching patterns
patterns inserted for the Level 2 can’t be used. Because, this
are required. The initial pattern is taken randomly from Y3l5 . The
is not a center Level and is just below the reference axis. As
further patterns are generated by performing bit rotation (Rotate
discussed earlier, for the levels above and below the reference
the bits by ‘1’ bit left) operation until the initial one repeats
axis, the number of switching patterns to be inserted must be
as shown in Fig. 3(b). This process generated four number of
equal to N i.e., 4. Therefore from Y2l5 , the first group patterns
patterns for Level 3. The complementary of these are inserted
[0011 0110 1100 1001] are chosen for Level 1.5 instead of
for Level 1 as shown in Fig. 4(a). With this, all four lower arm
the second group patterns [0101 10 1 0].
SMs get equal period of insertion and bypass at Level 3 and
With the above discussed process, the switching patterns are
Level 1, respectively.
inserted for the upper and lower arm reference levels shown in
Level 2: This is the center level. As a prerequisite, knowing
Fig. 7(a) and (b), respectively. These patterns lead to the total
the formation of this level enhances the deriving process of
insertion of SMs as N (= 4) and N+1 (= 5) at integer and
switching patterns.
non-integer levels, respectively. Moreover, the duty cycles of
In the lower arm modulating signal shown in Fig. 5(a), the
the upper arm SMs and lower arm SMs get equal as shown
center point is the reference axis i.e., where the magnitude is
in Fig. 8(a) and (b), respectively. Hence, the moments of step
2 (N/2). With respect to this, the part of modulating wave upto
changes in the arm voltages will be different and, the output
2.5 is at equidistance to the part upto 1.5. On rounding off these
voltage level number increases to 2N+1 under the condition
parts, the Level 2 is formed and positioned on reference axis.
of same switch count without voltage and current sensors. In
Therefore, it is denoted as center level. The switching patterns
the following section, generalization of the proposed method is
for this level must satisfy the fundamental principle of proposed
presented.
method. The deriving process is as follows.
The possible combinations for Level 2 are six as given by
IV. GENERALIZATION OF PROPOSED METHOD
(7). The initial pattern for this level is chosen randomly from
Y2l5 . The further patterns for the same level are obtained by The MMC structure shown in Fig. 1 has 2N SMs per phase.
bit rotation operation. This process generated two groups of Regardless of N+1 and 2N+1 modulation, the proposed method
switching sequences. The first group is having the switching derives the necessary switching patterns by considering either of
patterns [0011 0110 1100 1001] and the second group is hav- the arms. The lower arm is taken for the process understanding.
ing the switching patterns [0101 10 1 0]. As per the fundamental With N SMs per arm, the lower arm reference with conventional
principle, the switching patterns for the part of Level 2 appeared and modified round function is shown in Fig. 9(a) and (b),
at the end of one half-cycle and appeared at the start of immediate respectively. The common thing observed from these waveforms
half-cycle must be in complementary manner. This is fulfilled is the appearance of integer levels. Therefore, for 2N+1 modula-
by 2nd group patterns compared to 1st group and can be seen tion, the proposed method derives the switching patterns for the
from the Fig. 5(b) and (c). Therefore, the 2nd group patterns are integer levels and then inserts the same for non-integer levels.
considered for the center level. Considering N+1 level reference waveform, it has the integer
All the above derived switching patterns are inserted for the levels indexed from 0 to N as shown in Fig. 9(a). With N SMs
lower arm reference levels and their complementary are inserted per arm, the total possible switching combinations are 2N . Out of
for upper arm reference levels as shown in Fig. 4. these, the number of possibilities for each individual level can be
With these patterns, the duty cycles of the all SMs are shifted calculated by using (6) and are formed into a matrix YklN +1 with
in time, but, identical for every 2 (N/2) fundamental cycles. This a size of mkl × N . By combining all possible combinations of
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4368 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023

Fig. 5. Switching pattern deriving process for the center level. (a) Modulating signal for lower arm with N = 4, (b) insertion of 2nd group switching patterns for
level 2 in 5 level lower arm NLC reference and (c) insertion of 1st group switching patterns for level 2 in 5 level lower arm NLC reference.

Fig. 6. Gate pulse signals for lower arm SMs with proposed N+1 modulation.

Fig. 8. Gate pulse signals with 2N+1 modulation. (a) For upper arm SMs and
(b) for lower arm SMs.

each individual level, a matrix with a size of 2N × N is formed

and is denoted as YlN +1 given by (8).
From (8), the extraction process of suitable switching patterns
is as follows. The number of SMs from the lower arm to be
inserted is decided by the index number given to the each
individual level.
The Level N is indexed with N and to generate this, all N
SMs must be inserted. And vice-versa for Level 0. These two
levels are at equidistance with respect to Level N/2 (reference
axis) and their durations are identical. Therefore, with the in-
serted switching patterns, SMs get equal chance of insertion
Fig. 7. SMs insertion for 2N+1 with N = 4. (a) For lower arm and (b) for
upper arm.
and bypass at these levels. Similarly, the durations of the other
levels at equidistance from Level N/2 are identical. For Level

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GOBBURI et al.: LEVEL ENHANCED NEAREST LEVEL CONTROL FOR MODULAR MULTILEVEL CONVERTER 4369

For center level i.e., for Level N2 , the switching patterns

[0101 · · · ·01 10 1 0 · · · ·10] can be chosen from Y NN+1l to
(2)
fulfill the fundamental principle of proposed method. Once the
desired switching patterns are found for the lower arm SMs,
the complementary of these can be inserted for the upper arm
SMs simultaneously as given by (9) to generate N+1 output
Levels.
In (9), with respect to lower arm, (YklN +1 )N ×N is the comple-
ment of (YklN +1 )N ×N from k = ‘((N/2) + 1)’ to ‘N’. The Y N +1
consists of the derived switching patterns for the upper and
lower arm SMs. These switching patterns will ensure the equal
duty cycles for all SM capacitors in the phase leg. Therefore,
the same patterns can also be used for 2N+1 modulation as
follows.
With modified round function, the lower arm NLC reference
waveform has both integer and non-integer levels as shown in
Fig. 9(b).
⎡     ⎤
YNNl+1 1×N YNNl+1
⎢    1×N ⎥
⎢ ⎥
⎢ Y(N N +1
Y N +1 ⎥
⎢ −1)l N ×N (N −1)l N ×N ⎥
⎢ ⎥
⎢ . . ⎥
⎢ ⎥
⎢  .   .  ⎥
⎢ ⎥
⎢ ⎥
Fig. 9. Lower arm NLC references with N SMs per arm. (a) Using conventional ⎢ Y NN+1 Y N +1
⎥
⎢ ( 2 +1)l N ×N ( 2 +1)l N ×N ⎥
N
round function and (b) using modified round function. ⎢ ⎥
⎢ 010101 . . . ..01 101010 . . . ..10 ⎥
⎢ ⎥
Y N +1 = ⎢ ⎢ 101010 . .. ..10
⎥
010101 . .. ..01 ⎥ (9)
(N−1), mkl given by (6) is N and all these switching patterns ⎢ ⎥
ensure the equal chance of insertion for all SMs at this level. The ⎢ Y NN+1 Y NN+1 ⎥
⎢ ( 2 ) N ×N
+1 l ( 2 ) N ×N ⎥
+1 l
corresponding complementary patterns ensure the equal chance ⎢ ⎥
⎢ . . ⎥
of bypass at Level 1. Whereas for the Levels indexed from k ⎢ ⎥
⎢ .  .  ⎥
= ‘(N−2)’ to ‘((N/2) +1)’, mkl is greater than N. Therefore ⎢   ⎥
⎢ ⎥
from YklN +1 , choose the initial pattern randomly and generate ⎢ Y(N N +1
Y N +1
⎥
⎢  −1)l N ×N (N −1)l N ×N ⎥
the further patterns by bit rotation operation until the ⎢   ⎥
⎢ N +1
YN l N +1
YN l 1×N ⎥
⎡  N +1  ⎤ ⎣ 1×N  ⎦
YN l mN l ×N 
⎢   ⎥ Lower arm U pper arm
⎢ Y(NN +1
⎥
⎢ −1)l m ×N ⎥ For the levels indexed with integer number, the switching pat-
⎢ (N −1)l
⎥
⎢ · ⎥ terns derived for N+1 modulation can be used. For non-integer
⎢ ⎥
⎢ · ⎥
⎢   ⎥ levels, SMs in fraction number can’t be inserted as there is no
⎢ ⎥ PWM mode operation with NLC modulation. Hence, round off
⎢ Y NN+1 ⎥
⎢ ( 2 +1)l m ⎥ the fraction number to the nearest integer using conventional
⎢ N +1 l ×N ⎥
(2 )
⎢   ⎥ round function. For an example, round0.5 (N − 2.5) = N − 3 .
⎢ ⎥
⎢ N +1 ⎥ It means, N-3 SMs are to be inserted. Thus, the switching patterns
⎢ Y N l
( ) ⎥
YlN +1
=⎢ 2
m N ×N ⎥ (8) inserted for Level (N-3) can be used for Level (N−2.5). The same
⎢   (2) l ⎥
⎢ ⎥ can be followed for the
⎢ ⎥   remaining non-integer levels except for
⎢ Y NN+1 ⎥ the Level N2 − 0.5 . Though the round0.5 N2 − 0.5 = N2 ,
⎢ ( 2 −1)l m ⎥
⎢ N −1 l ×N ⎥
(2 ) the phenomenon of switchingpattern insertion process for Level
⎢ ⎥ 
⎢ · ⎥
2 is not applicable at Level 2 − 0.5 . Therefore, choose the
N N
⎢ ⎥
⎢ · ⎥ initial pattern randomly from Y NN+1l excluding the switching
⎢  N +1  ⎥ (2)
⎢ ⎥
⎢ Y1l
 N +1 m1l ×N ⎥ patterns [0101 · · · ·01 10 1 0 · · · ·10]. For the further patterns,
⎢ ⎥
⎣ Y 0l m0l ×N
⎦ perform the bit rotation operation on the preceding switching

Lower arm
pattern until the initial one repeats.
2N ×N
The above procedure for the lower arm reference levels is also
initial one repeats. The complementary of these patterns can be to be followed for the upper arm reference levels. With this, the
inserted for the levels at equidistance from the reference axis i.e., total insertion of SMs at integer and non-integer levels will be
for the levels indexed from k = ‘2’ to ‘((N/2) −1)’, respectively. N and N+1, respectively. Also, the duty cycles of the SMs in
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4370 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023

TABLE I
SINGLE PHASE MMC SYSTEM PARAMETERS

Fig. 11. Simulation results with proposed N+1 and 2N+1 modulation.
(a) Load voltage, (b) load current, (c) total SMs insertion and (d) arm inductor
drop.

Fig. 10. Simulation results with proposed N+1 and 2N+1 modulation.
(a) Upper and lower arm capacitor voltages and (b) arm voltages.
The main objective of proposed method is the output voltage
level enhancement. For t > 2 s, the modified round function
upper arm and lower arm get equal for every N/2 fundamental is applied and intermediate (non-integer) levels are generated
cycles. As a result, the output voltage level number enhances to in the arm references along with the integer levels. By inserting
2N+1 without voltage and current sensors. In the next section, necessary switching patterns to these levels, the upper and lower
the proposed method is verified by simulation and experimental arms are modulated simultaneously. In this case also, the SMs
results. are ensured with equal duty cycles and can be observed from the
SM capacitor voltages shown in Fig. 10(a). However, a decrease
V. SIMULATION AND EXPERIMENTAL RESULTS in the magnitude is seen. This is because the total SMs insertion
varies between 10 and 11, whereas it is always 10 in (N+1)
This section verifies the proposed N+1 and 2N+1 modulation modulation as shown in Fig. 11(c). Due to the variation in total
method based on NLC by simulation and experimental results SMs insertion, the moments of step changes in the arm voltages
as follows. are different as shown in Fig. 10(b), and hence, the step size of
output voltage is halved which increases the number of levels at
A. Simulation Results load side to 21 from 11, without voltage and current sensors, as
A single phase MMC system with 10 SMs per arm is built depicted in Fig. 11(a). As a result, the T.H.D. of output voltage
in the MATLAB/SIMULINK software. The corresponding pa- is improved to 2.83% from 6.41%.
rameters are tabulated in Table I. The corresponding load current is depicted in Fig. 11(b).
The effectiveness of proposed method is illustrated by the re- Further from Fig. 11(d), it is observed that, voltage pulses are
sults depicted in Figs. 10 and 11. Initially, the switching patterns imposed across the arm inductors during 2N+1 modulation.
are derived for N+1 modulation with the process discussed in the
earlier section. These switching patterns inserts the upper and B. Power Loss and Efficiency Analysis
lower arm SMs in complementary manner. With this operation,
The performance of proposed method is analyzed in terms of
the upper and lower arm SM capacitor voltages are shown in
power losses and efficiency in this section. The power losses in
Fig. 10(a). From this it is clear that, the proposed method ensures
MMC are classified as conduction and switching loss. The total
the equal duty cycles for all SMs in the phase leg. As a result, the
power losses in each SM of the MMC are given by (10).
capacitor voltages are well balanced around to the expected value
of 1kV without voltage and current sensors. The arm voltages PSM −loss = PL−S1 + PL−S2 + PL−D1 + PL−D2 (10)
in this case are shown in Fig. 10(b). Since the moments of step
changes are same, a 11-level output voltage with a T.H.D. of where PL-S1, PL-S2, PL-D1 and PL-D2 are the power losses
6.41% is generated at load side as depicted in Fig. 11(a). The in upper IGBT, lower IGBT, upper diode and lower diode,
corresponding load current is shown in Fig. 11(b). respectively. The type of loss takes place in IGBT and diode
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GOBBURI et al.: LEVEL ENHANCED NEAREST LEVEL CONTROL FOR MODULAR MULTILEVEL CONVERTER 4371

Fig. 13. Experimental setup.

Figs. 14 and 15 show the experimental results with proposed

method under steady-state condition. During N+1 modulation,
the total SMs insertion is always 4 and hence, the moments of
step changes in the arm voltages are same. Therefore, a 5-level
output is generated with 4 SMs per arm as shown in Fig. 14(a).
The corresponding load current is depicted in same figure.
Whereas, during 2N+1 modulation, the total SMs insertion
varies between 4 and 5. As a result, distortion in arm voltages is
observed and is shown in Fig. 14(d).
But, due to the shift in the instants of step changes in the
arm voltages, the step size of output voltage is halved and
Fig. 12. Comparison of proposed and conventional 2N+1 approaches. the number of output voltage levels are increased to 9 with same
(a) Power losses with m variation and (b) system efficiency with m variation.
switch count as shown in Fig. 14(d). In the same figure, the load
current is also depicted. It is observed that the shape of load
current waveform is improved.
are given by (11).
Further, the impact of enhanced output voltage levels is ana-
PL−S/D = PCond−S/D + PSw−S + PRec−D (11) lyzed on arm current waveform. Because of the uneven insertion
where PCond-S/D, PSw-S, PL-D1 and PRec-D represent the of SMs with 2N+1 modulation, the shape of arm current wave-
conduction loss in IGBT and diode, switching loss in IGBT form is distorted as shown in Fig. 14(h) compared to the arm
and reverse recovery losses in diode, respectively. The MMC current waveform depicted in Fig. 14(g) with N+1 modulation.
system is built using Si-IGBT SKM75GB123D (1200 V, 75 A) The corresponding rms current spectrum of arm current with
device. N+1 and 2N+1 modulation is depicted in Fig. 14(i). An increase
The power losses are calculated by the methodology presented in the magnitudes of unwanted harmonic components of order
in [23]. The effectiveness of proposed 2N+1 method under such as 2nd, 3rd, 4th and so on 10th is observed with 2N+1
modulation index variation (m) can be seen from Fig. 12. It is modulation compared to N+1 modulation.
observed that, the power losses are less with proposed method The corresponding upper arm SM capacitor voltages are
due to less switching and hence, the system efficiency is high depicted in Fig. 14(b) and (e) with N+1 and 2N+1 modulation,
compared to the earlier reported conventional as well as sensor- respectively. From these, it is confirmed that, the proposed
less 2N+1 approaches. method ensures the equal duty cycles for the SMs in the phase
leg. As a result, the capacitor voltages are balanced well to
C. Experimental Results Under Steady State Condition expected value. But the voltage ripple is slightly increased
because of the deviation in the shape of arm current during 2N+1
For the experimental verification of proposed method, a single modulation. Also, the voltage pulses are imposed across the two
phase MMC laboratory prototype with 4 SMs per arm is built as arm inductors as shown in Fig. 15. This is because of the total
shown in Fig. 13. Each SM is having a pair of IGBT switches SMs insertion variation between 4 and 5. However, the THD
and a Nichicon made capacitor of rating 2200 μF, 100 V. The dc of output voltage is improved to 9.26% from 15.5% and can be
voltage input to the MMC system is supplied by a three-phase seen from the THD spectrums of output shown in Fig. 14(f) and
diode rectifier. The gate pulse signals are generated by using (c), respectively. This proves the efficacy of proposed sensorless
Texas made TMS320F28335 processor and, are boosted to the voltage balancing method.
required level using the buffer circuit and a MIC4425 based
gate driver circuit to trigger the IGBT switches. The results
D. Experimental Results Under Dynamic Condition
are captured from the Tektronix made Digital Storage Oscillo-
scope (TPS2024B). The remaining parameters are tabulated in The performance of proposed 2N+1 method is also verified
Table I. under dynamic conditions such as output voltage and current
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4372 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023

Fig. 14. Experimental results: (a)–(c) with N+1 modulation; (d)–(f) with 2N+1 modulation; (a) load voltage (Va ), vertical 50 V/div; load current (ia ), 2 A/div,
arm voltages (Vu , Vl ) vertical 100 V/div., (b) upper arm capacitor voltages (Vc1u , Vc2u, Vc3u , Vc4u ), vertical 10 V/div., (c) T.H.D. of output voltage, (d) load
voltage (Va ), vertical 50 V/div; load current (ia ), 2 A/div, arm voltages (Vu , Vl ) vertical 100 V/div., (e) upper arm capacitor voltages (Vc1u , Vc2u, Vc3u , Vc4u ),
vertical 10 V/div., (f) T.H.D. of output voltage; horizontal 10 ms/div., (g) upper arm current (iu ) with N+1 modulation, vertical 1A/div, horizontal 10 ms./div.,
(h) upper arm current (iu ) with 2N+1 modulation, vertical 5A/div, horizontal 5 ms./div and (i) Rms current spectrum of upper arm current (iu ).

to 3. However, the number of load voltage levels are 5 due to

the shift in moments of step changes in the arm voltages. But,
due to the reduction in number of output voltage levels from 9
to 5, the reduction in the magnitude of load current is observed
and is depicted in Fig. 16(a). The corresponding upper arm SM
capacitor voltages are shown in Fig. 16(b). It is evident that,
even under output voltage change, the SM capacitor voltages
are balanced well to the value of 50 V with a peak-to- peak
voltage ripple of 6%.
Further, the performance of proposed method is validated
under current dynamic change created by halving the load
resistance value without changing the load inductance value.
There is no change in number of arm voltage levels and out-
Fig. 15. Experimental result with 2N+1 modulation. Arm inductor drop (Vxy ), put voltage levels as modulation index (m) value of the ref-
vertical 50 V/div; load voltage (Va ), vertical 50 V/div; horizontal 5 ms/div.
erence waveform is maintained at ‘1’. But, the magnitude of
load current is increased to twice the value before the load
change as shown in Fig. 17(a). The upper arm three SM
change. For the output voltage change, the modulation index capacitor voltages along with output current change are de-
(m) value of the reference waveform is changed suddenly from picted in Fig. 17(b). It is observed that, even under current dy-
1 to 0.5. The number of arm voltage levels are changed from 5 namic change, the capacitor voltages are maintained well to the
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GOBBURI et al.: LEVEL ENHANCED NEAREST LEVEL CONTROL FOR MODULAR MULTILEVEL CONVERTER 4373

Fig. 16. Experimental results with 2N+1 modulation under modulation index variation; (a) load voltage (Va ), vertical 50 V/div; load current (ia ), 2 A/div, arm
voltages (Vu , Vl ) vertical 100 V/div. and (b) upper arm submodule capacitor voltages (Vc1u , Vc2u, Vc3u , Vc4u ), vertical 10 V/div.; horizontal 10 ms/div.

Fig. 17. Experimental results with 2N+1 modulation under load variation with m =1; (a) load voltage (Va ), vertical 100 V/div; load current (ia ), 2 A/div, arm
voltages (Vu , Vl ) vertical 100 V/div.; horizontal 10 ms/div. and (b) load current (ia ), 2 A/div, upper arm three submodule capacitor voltages (Vc1u , Vc2u, Vc3u, ),
vertical 10 V/div.; horizontal 25 ms/div.

are −50% (1.1 mF), +15% (2.53 mF) and the remaining two
SM capacitors are having a tolerance of 1.93 mF (−12.27%)
and 2mF (−9%). In addition to these, the gate signal pulses
are delayed by providing more dead band time between the
complementary pair devices. The corresponding upper arm SM
capacitor voltages are shown in Fig. 18. It is observed that, the
SM capacitor with a tolerance of −50% is balanced well to the
expected voltage value of 50 V with the ripple content of ±9%.
Whereas, the remaining three SM capacitors are balanced to the
voltage value of 50 V with the ripple content of ±5%. So it is
confirmed that, though the SMs insertion is uneven, the proposed
method performs well under change in capacitor values.

Fig. 18. Experimental result with 2N+1 modulation under capacitor toler- VI. CONCLUSION
ances: upper arm submodule capacitor voltages (Vc1u , Vc2u, Vc3u, Vc4u ),
vertical 10 V/div.; horizontal 10 ms/div. NLC based voltage balancing method is presented for MMC
with increased output voltage levels utilizing same switch count
expected value of 50 V with the peak-to- peak voltage ripple of without deploying sensors. Regardless of N+1 and 2N+1 level
8%. modulation, either of the upper and lower arms can be con-
sidered for deriving necessary switching patterns. The deriving
process needs only simple logical operations and no rank calcu-
E. Performance Under Capacitor Tolerances lation is required. The proposed method is mathematically and
The changes in capacitor value with time are inevitable in graphically represented for the process comprehension. As volt-
multilevel converters [24]. For the experimental verification of age and current sensors are eliminated for the explicit capacitor
proposed 2N+1 method under this case, tolerances are created voltage balancing, the processing time and also the cost will be
by connecting additional capacitors in series as well as in parallel reduced substantially. The implementation is also simple and
with the upper arm SM capacitors in the power circuit. With re- can be extended to any number of sub-modules. The balanc-
spect to the SM capacitance value 2.2 mF, the created tolerances ing of the capacitor voltages of the sub-modules is validated
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4374 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 59, NO. 4, JULY/AUGUST 2023

from the simulation as well as experimentation results. Due [17] Y. Liu and F. Z. Peng, “A modular multilevel converter with self-voltage
to the less switching, the switching losses are low and hence balancing Part II: Y-matrix modulation,” IEEE J. Emerg. Sel. Topics Power
Electron., vol. 8, no. 2, pp. 1126–1133, Jun. 2020.
the system efficiency is high with proposed method. Though [18] N. Tashakor, M. Kilictas, E. Bagheri, and S. Goetz, “Modular multilevel
the submodule insertion is uneven with 2N+1 modulation, converter with sensorless diode-clamped balancing through level-adjusted
the capacitor voltages are well balanced under various case phase-shifted modulation,” IEEE Trans. Power Electron., vol. 36, no. 7,
pp. 7725–7735, Jul. 2021.
studies presented such as modulation index variation, load [19] F. Deng, C. Liu, Q. Wang, R. Zhu, X. Cai, and Z. Chen, “A currentless
variation and capacitor tolerances. Also, the THD of output submodule individual voltage balancing control for modular multilevel
voltage for 4 SMs per arm is substantially improved to 9.26% converters,” IEEE Trans. Ind. Electron., vol. 67, no. 11, pp. 9370–9382,
Nov. 2020.
with 2N+1 modulation, compared to that of 15.5% with N+1 [20] M. D. Islam, R. Razzaghi, and B. Bahrani, “Arm-sensorless sub-module
modulation. voltage estimation and balancing of modular multilevel converters,” IEEE
Trans. Power Del., vol. 35, no. 2, pp. 957–967, Apr. 2020.
[21] H. B. Gobburi, V. B. Borghate, and P. M. Meshram, “Generalized sen-
sorless capacitor voltage balancing technique for modular multilevel con-
verter with increased output voltage levels,” in Proc. IEEE Int. Conf. Power
REFERENCES Electron., Smart Grid Renew. Energy, 2020, pp. 1–7.
[22] H. B. Gobburi, V. B. Borghate, and P. M. Meshram, “Voltage bal-
[1] A. Lesnicar and R. Marquardt, “An innovative modular multilevel con- ancing method for modular multilevel converter with sensorless op-
verter topology suitable for a wide power range,” in Proc. IEEE Bologna eration,” in Proc. IEEE IAS Glob. Conf. Emerg. Technol., 2022,
Power Tech Conf ., 2003, vol. 3, Art. no. 6. pp. 828–833.
[2] P. M. Meshram and V. B. Borghate, “A simplified nearest level con- [23] J. Li, X. Zhao, Q. Song, H. Rao, S. Xu, and M. Chen, “Loss calcula-
trol (NLC) voltage balancing method for modular multilevel converter tion method and loss characteristic analysis of MMC based VSC-HVDC
(MMC),” IEEE Trans. Power Electron., vol. 30, no. 1, pp. 450–462, system,” in Proc. IEEE Int. Symp. Ind. Electron ., 2013, pp. 1–6.
Jan. 2015. [24] I. Polanco and D. Dujić, “Condition health monitoring of modular mul-
[3] R. R. Karasani, V. B. Borghate, P. M. Meshram, H. M. Suryawanshi, and S. tilevel converter submodule capacitors,” IEEE Trans. Power Electron.,
Sabyasachi, “A three-phase hybrid cascaded modular multilevel inverter vol. 37, no. 3, pp. 3544–3554, Mar. 2022.
for renewable energy environment,” IEEE Trans. Power Electron., vol. 32,
no. 2, pp. 1070–1087, Feb. 2017. Hari Babu Gobburi (Student Member, IEEE) was
[4] S. Debnath, J. Qin, B. Bahrani, M. Saeedifard, and P. Barbosa, “Operation, born in Guntur, India. He received the B.Tech. de-
control, and applications of the modular multilevel converter: A review,” gree in electrical and electronics engineering from
IEEE Trans. Power Electron., vol. 30, no. 1, pp. 37–53, Jan. 2015. Jawaharlal Nehru Technological University, Hyder-
[5] R. K. Subroto, Y. C. Chen, K. L. Lian, J. T. Tsai, and C. C. Chu, “An abad, India, in 2007, and M.Tech. degree in electrical
accurate accelerated steady-state model for high-level modular multi- engineering with specialization in power electronics
level converters,” IEEE Trans. Ind. Appl., vol. 57, no. 4, pp. 4278–4293, and drives from the National Institute of Technology
Jul./Aug. 2021. Kurukshetra, Kurukshetra, India, in 2010. He is cur-
[6] S. K. Patro, A. Shukla, and M. B. Ghat, “Hybrid series converter: A DC rently working toward the Ph.D. degree in electrical
fault-tolerant HVDC converter with wide operating range,” IEEE J. Emerg. engineering with the Visvesvaraya National Institute
Sel. Topics Power Electron., vol. 9, no. 1, pp. 765–779, Feb. 2021. of Technology, Nagpur, India. He has worked as an
[7] R. Zeng, L. Xu, L. Yao, and B. W. Williams, “Design and operation of Assistant Professor with Electrical and Electronics Engineering Department,
a hybrid modular multilevel converter,” IEEE Trans. Power Electron., Manipal Institute of Technology, Karnataka, India, from 2010 to 2013, and
vol. 30, no. 3, pp. 1137–1146, Mar. 2015. with Gitam University, Visakhapatnam, India, from 2013 to 2018. His research
[8] R. Aguilar, L. Tarisciotti, and J. Pereda, “Circulating current suppression interests include modular multilevel converters for high and medium voltage
in DAB assisted low-voltage variable frequency MMC,” IEEE Trans. Ind. applications.
Appl., vol. 58, no. 5, pp. 6322–6331, Sep./Oct. 2022.
[9] M. Hagiwara and H. Akagi, “Control and experiment of pulsewidth- Vijay B. Borghate (Senior Member, IEEE) was born
modulated modular multilevel converters,” IEEE Trans. Power Electron., in 1960. He received the B.E. degree in electrical, the
vol. 24, no. 7, pp. 1737–1746, Jul. 2009. M.Tech. degree in integrated power system, and the
[10] Z. Li, P. Wang, H. Zhu, Z. Chu, and Y. Li, “An improved pulse Ph.D. degree from the Visvesvaraya National Institute
width modulation method for chopper-cell-based modular multilevel con- of Technology, (formerly VRCE), Nagpur, India in
verters,” IEEE Trans. Power Electron., vol. 27, no. 8, pp. 3472–3481, 1982, 1984, and 2007, respectively. He has worked as
Aug. 2012. an Engineer during 1984–1985 in Maharashtra State
[11] J. Mei, K. Shen, B. Xiao, L. M. Tolbert, and J. Zheng, “A new selective Electricity Board, India, before joining the Visves-
loop bias mapping phase disposition PWM with dynamic voltage balance varaya National Institute of Technology (VNIT), then
capability for modular multilevel converter,” IEEE Trans. Ind. Electron., VRCE, Nagpur, India, as Lecturer in 1985. He is
vol. 61, no. 2, pp. 798–807, Feb. 2014. currently working as a Professor and the Head of
[12] D. Ronanki and S. S. Williamson, “A novel 2N + 1 carrier-based pulse Electrical Engineering Department, VNIT. He has authored or coauthored more
width modulation scheme for modular multilevel converters with reduced than 80 technical papers. His research interests include resonant converters and
control complexity,” IEEE Trans. Ind. Appl., vol. 56, no. 5, pp. 5593–5602, multilevel converters.
Sep./Oct. 2020.
[13] P. Hu and D. Jiang, “A level-increased nearest level modulation method
for modular multilevel converters,” IEEE Trans. Power Electron., vol. 30, Prafullachandra M. Meshram (Member, IEEE) re-
no. 4, pp. 1836–1842, Apr. 2015. ceived the B.E. degree in electrical, the M.Tech. de-
[14] A. Pérez-Basante, S. Ceballos, G. Konstantinou, J. Pou, J. Andreu, and I. gree in integrated power system, and the Ph.D. degree
M. de Alegría, “(2N+1) selective harmonic elimination-PWM for modular from the Visvesvaraya National Institute of Tech-
multilevel converters: A generalized formulation and a circulating current nology, (formerly VRCE), Nagpur, India, in 1991,
control method,” IEEE Trans. Power Electron., vol. 33, no. 1, pp. 802–818, 2003, and 2015, respectively. He is currently working
Jan. 2018. as an Associate Professor with the Department of
[15] A. Elserougi, M. I. Daoud, A. M. Massoud, A. S. Abdel-Khalik, and S. Electrical Engineering, Yeshwantrao Chavan College
Ahmed, “Investigation of sensorless capacitor voltage balancing technique of Engineering (YCCE), Nagpur, India. His research
for modular multilevel converters,” in Proc. IEEE 40th Annu. Conf. Ind. interests include multilevel converters, modular mul-
Electron. Soc., 2014, pp. 1569–1574. tilevel converters (MMC), and their control aspects.
[16] H. B. Gobburi, V. B. Borghate, and P. M. Meshram, “Sensorless voltage He has authored or coauthored more than 30 publications
balancing method for modular multilevel converter,” Int. J. Circuit Theory He was the recipient of best paper presentation awards for both of his papers
Appl., vol. 50, pp. 1965–1997, 2022. at an International Conference ECTI-CON 2005, Thailand.

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