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DSD ch-9 Sequential Circuits

This document discusses time shared architecture, which includes folded architecture, bit serial architecture, and digit serial architecture. It contrasts time shared architecture with fully dedicated architecture. The document then discusses sequential circuits, including synchronous and asynchronous sequential circuits. It provides examples of implementing finite state machines using Moore and Mealy models.

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ali tariq
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44 views

DSD ch-9 Sequential Circuits

This document discusses time shared architecture, which includes folded architecture, bit serial architecture, and digit serial architecture. It contrasts time shared architecture with fully dedicated architecture. The document then discusses sequential circuits, including synchronous and asynchronous sequential circuits. It provides examples of implementing finite state machines using Moore and Mealy models.

Uploaded by

ali tariq
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Time shared architecture

Ch-9: Book: Dr Shoab


Ch-8,10: Book: Stephen Brown

Dr Usman Ali, NUST College of E&ME


Architecture design
• Nyquist Sampling Theorem
• Fully dedicated architecture
– Unfolded architecture
• Time shared architecture
– Folded architecture
– Bit serial architecture
– Digit serial architecture

Dr Usman Ali, NUST College of E&ME


Fully dedicated architecture
Example

Dr Usman Ali, NUST College of E&ME


Bit serial architecture

Dr Usman Ali, NUST College of E&ME


Digit serial architecture

Dr Usman Ali, NUST College of E&ME


Sequential circuit
• Outputs depend on the past behavior of the
circuit, as well as on the present values of
inputs
• Also known as Finite state machines (FSM)
• Synchronous Sequential circuit
– a clock signal is used to control the operation of
the sequential circuit
• Asynchronous Sequential circuit
– no clock signal is used

Dr Usman Ali, NUST College of E&ME


Sequential circuit realization
• Inputs: W
• Outputs: Z
• States: Q
• Types: Mealy and Moore

Dr Usman Ali, NUST College of E&ME


FSM implementation

Dr Usman Ali, NUST College of E&ME


Design example- Moore
• 1. The circuit has one input, w, and one output, z.
• 2. All changes in the circuit occur on the positive
edge of a clock signal.
• 3. The output z is equal to 1 if during two
immediately preceding clock cycles the input w
was equal to 1. Otherwise, the value of z is equal
to 0.

Dr Usman Ali, NUST College of E&ME


State machine design
• Let the starting state is called state ‘A’. As long as the
input w is 0
• When w becomes equal to 1, the machine move to a
different state ‘B’, keeping output z=0
• When in state B, if w is 0 at the next active clock edge,
the circuit should move back to state A. However, if w =
1 when in state B, the circuit should change to a third
state, C, and it should then generate an output z = 1
• The circuit should remain in state ‘C’ as long as w = 1
and should continue to maintain z = 1.
• When w becomes 0, the machine should move back to
state A

Dr Usman Ali, NUST College of E&ME


State diagram

Dr Usman Ali, NUST College of E&ME


State table

Dr Usman Ali, NUST College of E&ME


Generalized circuit

Present state?
Next state?

Dr Usman Ali, NUST College of E&ME


State assignment

Dr Usman Ali, NUST College of E&ME


Combinational circuit

Dr Usman Ali, NUST College of E&ME


Final implementation

Dr Usman Ali, NUST College of E&ME


Timing diagram

Dr Usman Ali, NUST College of E&ME


• Verilog code
Moore
FSM

Dr Usman Ali, NUST College of E&ME


• Verilog code
Moore
FSM, second version

Dr Usman Ali, NUST College of E&ME


Mealy State Model
• Previous specs
– output z =1 in the clock cycle that follows the
detection of the second occurrence of w = 1

• New specs
– z should be equal to 1 in the same clock cycle
when the second occurrence of w = 1 is detected

Dr Usman Ali, NUST College of E&ME


State diagram

Dr Usman Ali, NUST College of E&ME


State table & Circuit

Verilog
Code

Dr Usman Ali, NUST College of E&ME


Verilog code- Mealy

Dr Usman Ali, NUST College of E&ME


Verilog code- Mealy

Dr Usman Ali, NUST College of E&ME


Timing diagram

Dr Usman Ali, NUST College of E&ME


Serial Adder Example

Dr Usman Ali, NUST College of E&ME


Serial Adder- Mealy FSM

Next state eq.


Dr Usman Ali, NUST College of E&ME
Output eq.
Serial Adder- Mealy FSM

Dr Usman Ali, NUST College of E&ME


Serial Adder- Moore FSM

Dr Usman Ali, NUST College of E&ME


Serial Adder- Moore FSM

Dr Usman Ali, NUST College of E&ME


Counter FSM

Dr Usman Ali, NUST College of E&ME


Counter FSM

Dr Usman Ali, NUST College of E&ME


One hot encoding
• Uses as many state variables as there are
states in a sequential circuit
• for each state all but one of the state variables
are equal to 0
• Example

Dr Usman Ali, NUST College of E&ME


Dr Usman Ali, NUST College of E&ME
Dr Usman Ali, NUST College of E&ME
Algorithmic State Machine (ASM)
Charts

Dr Usman Ali, NUST College of E&ME


Timing diagram

Dr Usman Ali, NUST College of E&ME


State box
• It is equivalent to a node in the state diagram
or a row in the state table.
• The name of the state is indicated outside the
box in the top-left corner
• The Moore-type outputs are listed inside the
box

Dr Usman Ali, NUST College of E&ME


Decision box
• A diamond indicates that the stated condition
expression is to be tested and the exit path is
to be chosen accordingly
• The condition expression consists of one or
more inputs to the FSM

Dr Usman Ali, NUST College of E&ME


Conditional output box
• An oval denotes the output signals that are of
Mealy type
• These outputs depend on the values of the
state variables and the inputs of the FSM
• The condition that determines whether such
outputs are generated is specified in a
decision box

Dr Usman Ali, NUST College of E&ME


Moore/ Mealy ASM charts

Dr Usman Ali, NUST College of E&ME


Example: A Bit-Counting Circuit
• pseudo-code

Dr Usman Ali, NUST College of E&ME


Pseudo code based ASM chart

Dr Usman Ali, NUST College of E&ME


Data-path and control circuits

Dr Usman Ali, NUST College of E&ME


Datapath- Bit counting example

Dr Usman Ali, NUST College of E&ME


ASM chart- Bit counting example

Dr Usman Ali, NUST College of E&ME


Timing diagram

Dr Usman Ali, NUST College of E&ME


Simulation results

Dr Usman Ali, NUST College of E&ME


Verilog code- Bit counting FSM

Dr Usman Ali, NUST College of E&ME


• Verilog
code, Bit
counting
FSM

Dr Usman Ali, NUST College of E&ME


• Verilog code,
Bit counting
FSM

Dr Usman Ali, NUST College of E&ME


• Verilog
code, Bit
counting
FSM

Dr Usman Ali, NUST College of E&ME


• Right to left
shift
register

Dr Usman Ali, NUST College of E&ME


Shift-and-Add Multiplier

Dr Usman Ali, NUST College of E&ME


ASM chart for multiplier

Dr Usman Ali, NUST College of E&ME


• Datapath

Dr Usman Ali, NUST College of E&ME


• ASM chart

Dr Usman Ali, NUST College of E&ME


Multiplier code

Dr Usman Ali, NUST College of E&ME


Multiplier
code
• Control unit

Dr Usman Ali, NUST College of E&ME


FSM outputs

Dr Usman Ali, NUST College of E&ME


Data-path circuit

Dr Usman Ali, NUST College of E&ME


Simulation results for the multiplier
circuit

Dr Usman Ali, NUST College of E&ME


Divider

Dr Usman Ali, NUST College of E&ME


• ASM
• Divider

Dr Usman Ali, NUST College of E&ME


Data path: divider

Dr Usman Ali, NUST College of E&ME


• ASM chart,
Control signals
of data-path

Dr Usman Ali, NUST College of E&ME


Square-root Approximation
• State machine based design for Euclidean
distance calculation
– Multi-threaded architecture
– Resource optimization

Dr Usman Ali, NUST College of E&ME


ASM

Dr Usman Ali, NUST College of E&ME


Variable Usage chart

Dr Usman Ali, NUST College of E&ME


Register assignment

Dr Usman Ali, NUST College of E&ME


Operation usage

Dr Usman Ali, NUST College of E&ME


Computation units
• Absolute value unit

Dr Usman Ali, NUST College of E&ME


Computation units
• Min/max units

Dr Usman Ali, NUST College of E&ME


ASM

Dr Usman Ali, NUST College of E&ME


Data-path

Dr Usman Ali, NUST College of E&ME


Complete data-path circuit

Dr Usman Ali, NUST College of E&ME

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