Tessent® Integrated Flow

Lab2:
IJTAG Introduction; Exercise 2 and 3

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Table of Contents
Before you Begin ...............................................................................................................................2

Lab2: IJTAG Introduction – Exercises 2-3 .............................................................................................4

Objectives ................................................................................................................................................ 4
Introduction ............................................................................................................................................. 4
Exercise 2: Extracting the Block-Level ICL Network from Top-Level Verilog .......................................... 5
Exercise 3: Gaining Access to the IJTAG Test Instrument Using the iProc Command ........................... 11

Notes............................................................................................................................................... 21

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Before you Begin

If this is the first time you are launching this VM (Virtual Machine), you must download and extract
the lab data as described in the "Obtaining Lab Data section below.

Whenever you are using the VM for lab exercises and are finished with your session, please use the
Caution
"Disconnect" feature of the Desktop Viewer before the VM times out to preserve the data from one
session to the next. Failure to do so will remove the VM, and its contents.

If the VM was removed, you will be presented with a new VM requiring you to follow the download
and extract process. This allows you to "refresh" the lab data so you can go through the labs again
with a new database.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed environment variables
already setup.

Obtaining Lab Data

If the flow_data directory, with lab subdirectories, is located in the home directory (e.g. cd ~), please
proceed to the lab exercises as you have already set up the lab database on this VM.

If this is the first time you are starting a session for this VM, the flow_data directory will not be in the
home directory and you will need to download and extract it using the following instructions.

1. Double click on the Desktop icon Download_lab_data, . This launches a web browser.

2. On the resulting web page, select the file named tessent_flow_data_v2020.3_20201025.tgz.

3. In the resultant window, select the Download button, enable the Save File button, then, select the
OK button to download the file.

4. Move the file in the Downloads directory to the home directory. If you are using the terminal
(Applications>Favorites>Terminal) you can use the following command:

mv ./Downloads/tessent_flow_data_v2020.3_20201025.tgz .

5. In a terminal window, extract the files from the compressed tar file using the command:
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tar xzvf ./tessent_flow_ data_v2020.3_20201025.tgz

You should now have a directory named flow_data in your Home directory. That directory contains all
the files you need to perform the exercises, in this learning path.

You are now ready to proceed with lab exercises.

IJTAG Introduction – Exercises 2-3 3

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Lab2:
IJTAG Introduction – Exercises 2-3

Objectives
Upon completing this lab, you should be able to

• Discuss primitive ICL instruments

• Use the commands required to gain access to an instrument

• Create and write out pattern sets

• Perform a basic ICL network extraction

• Retarget PDL and access instruments on the IJTAG network

Introduction
This lab is comprised of several exercises. In one exercise, you will create a basic ICL description for a
PLL and generate a PDL for the PLL ICL.

In exercises 2 and 3, you will invoke Tessent IJTAG within Tessent Shell in order to extract the ICL
network accessing the instruments, then create a pattern set to access an instrument in the IJTAG
network.

IJTAG Introduction – Exercises 2-3 4

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Exercise 2: Extracting the Block-Level ICL Network from

Top-Level Verilog

Overview
In this exercise, you will invoke Tessent Shell and extract the ICL network for block3. You will then run
supplied scripts to extract the ICL for other blocks.

The Design
This lab uses the top-level design module called chip. The hierarchical components of chip are described
in the following schematic. The module contains four different blocks; each block contains different
instruments that need to be tested. The top-level contains a TAP controller at the chip interface that
connects to the SIB network that selects the particular block and instrument to be tested. Instruments
inside each block are accessed differently. Accessing the structure of each instrument is not the focus of
this exercise; however, it is should be noted as follows.
Figure 2-1. Top level Schematic

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Figure 2-2. Block1 Schematic

1. Block1_0, Block1_1

a. Two instruments (raw*) are accessed via Test Data Registers (tdr*).

b. Test instruments can be accessed either serially or in parallel. This will be determined by
the state of the SIBs.

c. The illustration above shows the situation where both instruments are tested in parallel.

Figure 2-3. Block2 Schematic

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2. Block 2
a. There are two instruments to be tested raw1_I1 and raw1_I2.
b. The Test Data Register TDR2_I1 has three functions:
i. It selects the instrument.
ii. It provides the stimuli.
iii. It captures the response.
c. Based on the selection logic, either DR1 or DR2 captures the data from the TDR and
passes it on.
d. The data register that is not selected, keeps its data.
Figure 2-4. Block3 Schematic

3. Block3 - The selection port on the MUX selects each instrument. A test data register (not shown
in the top-level schematic) accesses each instrument.
a. The register connected to SO is a 2-bit IEEE P1687-compliant register.
b. This 2-bit IEEE P1687-compliant register controls the MUX, which selects the instrument
to be tested.
c. IEEE P1687-compliant TDRs access four instruments (tdr1_I1 to tdr1_I4).
d. Only one instrument can be accessed at a time.

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Lab Database
The files that are required for all three exercises are:
 libs - contains the data directories required to run the lab
o atpglib - contains the ATPG libraries used for scan pattern generation
o icl - Contains the ICL descriptions for the blocks
o icl_primitives - Contains the ICL descriptions for the low-level components (SIB,TDR,
TAP, …)
o pdl - Contains iProc definitions
o rtl - Verilog netlist of the top-level design
 results/generated_icl - Repository for the results of the exercises
 Exercise[2-3] – Scripts
 solutions - .tcl files to run labs

Invoke Tessent Shell and extract Block-level ICL network

1. Change directory to $FLOW_LABS/Lab2/Exercise2
$ cd $FLOW_LABS/Lab2/Exercise2
2. Invoke Tessent Shell and save the transcript in the logfiles directory
$ tessent -shell -logfile logfiles/Lab2_ex2.log -replace
3. Set the context for IJTAG pattern
SETUP> set_context patterns -ijtag
4. Load the Verilog gate-level netlist for the top-level design
SETUP> read_verilog design/chip.v
5. Load the ATPG library
SETUP> read_cell_library libs/atpglib/tessent.CellLib
6. Use wildcarding to read in all ICL primitive files
SETUP> read_icl libs/icl_primitives/*.icl
7. Specify how Tessent IJTAG will map the ICL module to the Verilog modules.
SETUP> set_module_matching_options -suffix_pattern_list\
"_\[0-9\]" -regexp
8. Specify that you will only be focusing on Block 3.
SETUP> set_current_design block3
9. Define the test clock (tclk) and the free running clock (ClkA)
SETUP> add_clocks 1 tck
SETUP> add_clocks 0 ClkA -free_running
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If there are additional design constraints required, you would add those
in this section
Note

10. Run DRCs and set the system to analysis mode

SETUP> check_design_rules

11. Report the ICL module to Verilog Module mapping

ANALYSIS> report_module_matching -icl

You can use this command any time after the set_current_design
step above. Verilog and ICL modules are mapped to each other by
Note executing the command, set_current_design.

12. Write out the generated ICL file with and without lower-level model definitions
a) Write out the ICL files. Use the -created option to include the ICL modules that were
generated in this session, and reference the existing ICL modules.
ANALYSIS> write_icl -output_file \
results/generated_icl/generated_chip_block3.wrapper.icl \
–created -replace
b) Write out the ICL files and include all modules definitions:
ANALYSIS> write_icl -output_file \
results/generated_icl/generated_chip_block3.all.icl \
-replace
13. Exit Tessent Shell
ANALYSIS> exit

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Extract ICL for block1, block2, and block3

Scripts and .tcl files are supplied for block1, block2 and block3. These scripts will extract the ICL
networks and store them in the results/generated_icl directory.

1. Run the provided scripts to extract TCL networks for block1 ,block2 and block3.
$ ./1a.run_icl_extraction_block1
$ ./1b.run_icl_extraction_block2
$ ./1c.run_icl_extraction_block3
2. Review the extracted ICL networks in results/generated_icl

This is the end of Exercise 2. Proceed to Exercise 3.

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Exercise 3: Gaining Access to the IJTAG Test Instrument

Using the iProc Command

Overview
In this lab exercise you will invoke Tessent shell to setup and create PDL patterns utilizing some
advanced PDL syntax.

Design Overview
This lab uses the top-level ICL for the design named chip that includes the ICL components as shown on
the schematic.

Schematic for Chip

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Lab Database / icl directory

1. Change directories to $FLOW_LABS/Lab2/Exercise3/

$ cd $FLOW_LABS/Lab2/Exercise3/
Notice the following directories:

 libs - Includes the instrument level ICL and pdl files for this lab.
 solutions - Includes the scripts that will be used during the labs including a completed
script that can be used as a reference.
 design - Includes the ICL for chip.icl

2. Change directory into libs/icl, then, using a text editor, review the ICL files as described
below.

a) $ cd libs/icl
b) sib1.icl - Segment-insertion-bit ICL module. It is the same ICL description for the SIB used
in exercise 2.

c) tdr1.icl - Data register ICL for the TDR used in BLOCK1. This is similar to the one used in
the previous lab, but since it has a parameterized register size, it can be used for
multiple TDR configurations.

i. The following lines define the register length

Parameter Regmax = 3;
Parameter Regmin = 0;

ii. Notice how the parameters are used in the ScanRegister command.

ScanRegister R[$Regmax:$Regmin];

iii. Using an alias allows us to define a shorthand notation of the LSB and the rest of
the register

Alias xBit = R[0];

Alias dataBits[$Regmax:1] = R[$Regmax:1] ;

d) tdr2.icl - ICL for the TDR in Block2. This is similar to the one used in the previous lab. It
uses parameters as we saw in tdr1.tcl, and utilizes an enumeration table as well.

i. Scan Register definition

ScanRegister R[$Regmax:$Regmin] {
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ScanInSource si;
RefEnum OptionalValues ;
}

ii. Enumeration Table

Enum OptionalValues {
reset = 8'b0 ;
set = 8'b11111111 ;
chain = 8'b11001100 ;
green = 8'hee ;
blue = 8'd198 ;
}

iii. Open the file, ../../design/icl/chip.icl - Top-level ICL. This is

similar to the one used in Lab2 of exercise2 with one exception:

Notice that when TDR1 is instantiated, that Parameter is declared.

Parameter Regmax = 5 ;

This declaration will override the value that is declared in the file tdr1.icl. The effect is
that the TDR1 will be a 6-bit register instead of the default 4-bit register defined in the
file tdr1.icl

Lab Database / pdl directory

The pdl directory contains a file tdr2.pdl. This file contains iProc that specifies 2 procedures that will
be accessed by an iCall command.

1. Change directory into the libs/pdl directory

$ cd ../pdl

2. Using a text editor, open the file tdr2.pdl.

a) Notice this file contains the procedures for tdr2.

iProcsForModule tdr2

b) The 2 procedures declared are:

i. write_to_tdr2 - a procedure used to write a data value. The argument

“value” is passed to the procedure from an iCall command. “value” is

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one of the eNum defined in the .tcl model. If no argument is passed, then
the value “set” will be used.

ii. read_from_tdr2 - a procedure used to read data from the scan register. If
there is one argument, value becomes the expected value for testing. If
there is no argument, the default value in “set” becomes the expected value
for the test.

Editing the .tcl file that will be used in Tessent Shell

In this part of the lab, you will edit a .tcl file used to issue commands for Tessent Shell.

1. Edit the file chip_test.tcl, which is a tcl script to run the process. This file includes comments
that will prompt you where to enter commands as well as having some commands already
entered. Complete the file using the following directions:

a) Set the context for IJTAG pattern generation by adding the following command to
the file:
set_context patterns -ijtag

b) Read the required ICL files for the design. This can be done with either individual
commands, or by using a TCL script that utilized a foreach command to read a list of
modules and issue the appropriate read_icl command.

Add the following lines to the Tcl script to perform this step.

read_icl design/icl/chip.icl
set modules {sib1 tdr1 tdr2}
foreach module \
$modules {read_icl libs/icl/${module}.icl}

You will notice when this is run in Tessent Shell, it generates the following
commands:

Note read_icl libs/icl/sib1.icl

read_icl libs/icl/tdr1.icl
read_icl libs/icl/tdr2.icl

Notice that the command to source the file tdr2.pdl file has already been added to
the script. This allows the procedures to be available for use later in the script.

Note

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c) Notice the command which will set the hierarchical level of the design we're
operating on has been specified using the command:

set_current_design

d) Notice the command which will run the DRCs has already been specified. When this
command is executed, Tessent Shell transitions to analysis mode when there are no
errors. If errors exist, you will need to fix them.

check_design_rules

e) In the next few sub-steps, using the parameters, alias and enumerations defined in
tdr1.icl and tdr2.icl, you will add the commands which will open a pattern set,
initialize both TDR1, and TDR2 and close the pattern to the Tcl script.

i. Create a pattern set, set_1, with a tester period of 200ns.

open_pattern_set set_1 -tester_period 200ns

ii. Initialize TDR1 per the information provided in the iNote statements, which
are already in the file and are provided here for completeness.

iNote “Writing xBit of MyTdr1 to zero”

iNote “Writing all data bits of MyTdr1 to 1"
iWrite MyTdr1.xBit 0b0
iWrite MyTdr1.dataBits 0b11111
iApply

iii. Initialize TDR2 per the information provided in the iNote statements,
keeping in mind that set has the value defined in the enumeration table in
the tdr2.icl file.

iNote “Writing 'set' to MyTdr2.R”

iWrite MyTdr2.R set
iApply

iv. Close pattern set set_1.

close_pattern_set

f) Using iCall to utilize the iProc procedures, create a new pattern set, read the
TDR2, with the expected value of “green”, then close the pattern set.

i. Create a pattern set named set_2.

open_pattern_set set_2

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ii. Initialize TDR2 per the information provided in the iNote statements, which
are already in file and are, as well as the comment, provided here for
completeness.

// Reading from TDR 2 the expect value 'green'

iNote “Reading 'green' from MyTdr2.R”
iCall MyTdr2.read_from_tdr2 green

iii. Close pattern set set_2.

close_pattern_set

When creating pattern sets, you can use both iWrite and iCall.

The difference is that iWrite expects one of two things:

Note
(1) An addressable target, like a data input port or a data (or scan)
register
(2) A value to write there.

iCall, on the other hand, calls a PDL procedure (iProc), in pretty

much the same way Tcl calls a Tcl procedure. Inside iProc, you can have
additional iCall commands as well as iWrite commands. iCall by
itself does not send any data to ports or registers.

g) Generate a report regarding the created patterns

report_pattern_set

h) Save the created patterns in both ATE and PDL format.

write_patterns results/pattern_sets_1_2.stil \
-stil -pattern_set set_1 set_2 -replace
write_patterns results/pattern_sets_1_2.wgl\
-wgl -pattern_set set_1 set_2 -replace
write_patterns results/pattern_set_1.pdl \
-pdl -pattern_set set_1 -replace
write_patterns results/pattern_set_2.pdl \
-pdl -pattern_set set_2 -replace
write_patterns results/pattern_set_1_2.pdl \
-pdl -pattern_set set_1 set_2 –replace

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An important note about the created PDL patterns:

- They do not describe the complete patterns that will be generated for
Note
ATE. The ATE patterns may include control values that gain access to
instrument
- Instead, PDL defines patterns at the instrument level, (either at a port or
at a register), and determines where to apply care bit values.
The application tool (Tessent IJTAG) then follows the PDL instructions and
applies the care bits through ICL hierarchy, automatically adding control
values as needed.

i) Save this file.

2. Invoke Tessent Shell and run the .tcl file you just edited.

$ tessent -shell -dofile chip_test.tcl \

-logfile logfiles/Lab2_ex3.log -replace
If there are any errors caused by the .tcl file you created, review the directions above, and make the
necessary edits. Remember that a working version of the file is available to review in the solutions
directory

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Reviewing the created PDL files

You will now review the PDL files that were created and we will explain what is going on. The schematic
for this lab is the same as in exercise 2. The differences occur with the syntax in the .icl files that are
provided

Initialize TDR1

Initialize MyTdr1
Open the file results/pattern_set_1.pdl and notice the following:

1. Even though you do not see an iReset statement, it is implicitly implied by Tessent IJTAG.

2. In order to write to TDR1 (in BLOCK1), the path must be activated. Since we're only initializing TDR1,
we need to make sure that the path to TDR2 is not initialized by confirming the PDL you just
generated has the following statements:
iWrite MySib1.SIB 0b1
iRead MySib1.SIB 0b0
iWrite MySib2.SIB 0b0
iRead MySib2.SIB 0b0
iApply

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Based on IEEE 1687 the order of the commands (iRead/iWrite for

example) prior to an iApply does not make any difference. When the PDL
Note is processed for use on an ATE, the effective pattern will: Shift 10 Expect
00.

3. Confirm the TDR1 is initialized by the presence of the iWrite statement:

iWrite MyTdr1.R[5:0] 0b111110

Initialize MyTdr2
4. Confirm the path to TDR1 is disabled and the path to TDR2 is enabled by the presence of the
following statements:

iWrite MySib1.SIB 0b0

iRead MySib1.SIB 0b0
iWrite MySib2.SIB 0b1
iRead MySib2.SIB 0b0
iApply
5. Confirm the initialization pattern is written to TDR2 by the presence of the following statements:
iNote “Writing 'set' to MyTdr2.R”
iWrite MySib1.SIB 0b0
iRead MySib1.SIB 0b0
iWrite MyTdr2.R[7:0] 0b11111111
iWrite MySib2.SIB 0b1
iRead MySib2.SIB 0b0
iApply
6. If any of the initialization statements in your pattern_set_1.pdl file are not the same as those listed
above, you will need to go back and find, then fix the error and rerun the Tcl script through Tessent
Shell.

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Reading data from MyTdr2

1. Open the results/pattern_set_2.pdl and confirm the presence of the following statements in the
pattern_set_2.pdl file you just generated (statements continue onto the next page).
iNote "Reading 'green' from MyTdr2.R"
iNote "Reading the expect value 'green' from register R
of ICL module tdr2"
iWrite MySib1.SIB 0b0
iRead MySib1.SIB 0b0
iWrite MySib2.SIB 0b1
iRead MySib2.SIB 0b0
iApply
iWrite MySib1.SIB 0b0
iRead MySib1.SIB 0b0
iWrite MyTdr2.R[7:0] 0b00000000
iRead MyTdr2.R[7:0] 0b11101110
iWrite MySib2.SIB 0b1
iRead MySib2.SIB 0b0
iApply
2. If any of the initialization statements in your pattern_set_1.pdl file are not the same as those listed
above, you will need to go back and find, then fix the error and rerun the Tcl script through Tessent
Shell.

This is the end of exercise 3 and completes Lab 2.

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Notes

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