A Multi-Mode Scannable Memory Element for High Test Applica-

tion Efficiency and Delay Testing

E. S. Sogomonyan A.D. Singh
Institute of Control Sciences Department of Electrical Engineering
Russian Academie of Sciences Auburn University
11 78 06 Moscow, Russia Auburn 36849, USA
M. Goessel
Fault Tolerant Computing Group
Institute of Informatics at the University of Potsdam
14415 Potsdam,Germany

Abstract increasing important in sub-micron technologies.

In this paper we present a new multi-mode scannable
This paper introduces a new multi-mode scannable
memory element for use in sequential circuit design that
memory element which allows pseudorandom testing to be
integrated with scan in sequential circuits without the need of overcomes these important limitations of traditional scan
any design changes. As in the case of scan, the new element is design at the expense of modest area and performance
used in place of regular flip-flops in the design library. overhead. Importantly, our approach requires no
Interconnect overhead is comparable to scan with reset. modifications to the design at the logic level. As in the case of
Concurrent with normal operation, the design accumulates a scan, the new multi-mode memory element is used in place of
signature of the state variables in the scan-register configured regular flip-flops in the design library. Interconnect overhead
as a multiple input signature analyzer. Thus virtually is also comparable to scan with reset. While cell area will be
complete state observability is achieved without the need of somewhat larger, this is not expected to be a major limitation
scanning-out the state for each test-input. The pseudorandom in multi-million transistor designs that are usually
states of the MISA can also be utilized as state inputs in interconnect and not area limited. A key feature of the new
circular testing. In this way, most faults are covered in a multi-mode design is the ability to not only configure a serial
pseudorandom, “test per clock” mode. Only a few random scan shift register, but also to accumulate in this register, a
pattern resistant faults require scan, greatly reducing test signature of the circuit states encountered during normal
application time. Pseudorandom delay testing of the true operation. This concurrently operating multiple input
normally active circuit paths is also possible. Two-pattern signature analyzer (MISA) provides virtually complete state
tests are supported. Finally, we show that the new memory observability during test, without the need for scanning out
element can also be used for fault-tolerant design. the state for each test input. The compressed response need be
1. Introduction shifted out only once at the end of the test. Importantly, this
MISA shift register also provides a source for introducing
Scan design is a powerful solution to the testability pseudorandom inputs at the state variables during test
problem in sequential circuits. Here the sequential testing (without the need for scanning in the state). This can
problem is essentially reduced to one of testing the significantly enhance test input controllability in designs with
combinational logic block since the state inputs to the logic unreachable or hard to reach states without the use of scan.
are completely controlled by shifting in any desired test Most of the test set can be run without the need for scanning
pattern through the shift register scan chain. State outputs are in the test inputs and scanning out test results. Scan need be
similarly made fully observable by shifting out the scan chain used only to test for relatively few random vector resistant
[1,3]. However, for large designs, a major disadvantage is that faults, resulting in very high test application efficiency.
test application time can become very long, since each test
vector has to be serially shifted in, and the circuit response We show that large designs employing the new memory
shifted out. To improve this situation different modification of element can potentially obtain up to an order of magnitude
memory elements were proposed (see for instance [4, 8, 9, reduction in test application time over the conventional scan
13]). More recently, the possibility of building in BIST on top approach. This suggests very substantial cost savings at
of scan has been studied [11, 12]. An additional significant manufacture from reduced test application time. Additionally,
problem with traditional scan design is that it can only support our new multi-mode scannable memory element supports
very limited forms of delay testing, which is becoming significantly enhanced delay testing, a key requirement for
high performance testing. In addition the new memory The selection of input (data or scan) to this 2-port flip
element can also be used fault-tolerant design. flop is controlled by two control lines C1 and C2. When C1
and C2 are both low, the OR gate connected to the control
This paper is organized as follows. In Section 2 we
lines ensures that the data input is captured in D2. For all
introduce the new memory element. The four modes of
other cases, the scan input is captured in D2.
operation are described in detail in Section 3. Section 4
discusses how tests for sequential circuits can be generated These control lines also select the data output from the
and applied to take advantage to the capabilities of this new multi-mode memory element to be presented to the circuit
memory element. Also presented in this section is a simple at any time. If C1 is high the output from the primary flip
analysis to evaluate the expected test time reduction from flop D1 is available at the data output; this is the normal
using the new design. Section 5 discusses the application of operation mode. If C1 is low, then the output of D2 is
pseudorandom and deterministic two vector tests for delay presented at the data output.
testing. Section 6 outlines an application of the new Observe that in normal operation mode there exists an
memory element to error detection in reliable and fault independent parallel path through flip flop D2 and the scan
tolerant designs. We conclude in Section 7. output of the memory element. This can be used in two
2. The Multi-Mode Scannable Memory ways as specified by control line C2. For C2 low, the upper
Element input of the EXOR gate at the scan output is forced low.

A gate level schematic for the basic structure of the new In this case the contents of D2 are available unmodified
multi-mode scannable memory element is shown in Figure at the scan output. This is the traditional scan mode. If C2 is
1. It consists of a master slave D flip flop D1, clocked by high, however, we obtain at the scan output the exclusive
two non overlapping clock phases CK1 and CK2. This flip OR of the present functional output of the memory element
flop is primarily responsible for normal operation. from D1 and the contents of the scan flip flop D2. When
Connected in parallel to D1 is a modified 2-port scannable configured in a closed loop chain with N other scannable
master slave D flip flop D2, similar to the traditional IBM elements, the scan register in this case acts as a multi-input
LSSD scannable flip flop design[1,3]. However, unlike the signature analyzer (MISA) with characteristic polynomial
IBM design, where the data or scan input is selected based xN + 1. This sets up a powerful output compression mode
on whether the operational or test clock is activated, both that allows test results from multiple test cycles to be
input latches in D2 are triggered by the same clock CK1. accumulated and observed by shifting out the scan chain
only once at the end of the test.

Data Input Data Output

f3

1P F-F D1

Scan O
f1
CK1 f4

Scan In

f2
CK2 2P F-F D2 Fig. 1

C1
C2
 Note from Figure 1 that the multi-mode scannable design is shown as the source of signals. It is assumed that
memory element is significantly more complex in gate count in general the combinational logic block will also receive
as compared to a standard scan flip flop. However, this is not inputs from other similar memory elements. In addition to
expected to be a major concern for most applications since their usual functional connections, all these memory
designs are generally interconnect and not area limited. This elements are serially connected together to form a SCAN/
remains true even for advanced processes such as IBM’s MISA chain as shown in Figure 3.
0.35 micron CMOS with five metal interconnect layers. The Figure 2(a) and (b) shows the active connections for
Interconnect overhead is a better indicator of layout area the four modes. In mode 1, (C1=1, C2=1) we have normal
penalty. Here our design is comparable to scan, if a reset operation along with concurrent output compression in the
capability is included for each flip-flop. Recall that we MISA register. In this mode the output of the primary D1flip
employ two control signals to configure the memory flop in MEi is connected to the combinational logic, and the
element in the various test modes whereas in IBM’s classical next state output is again captured in D1 of MEi at the next
scan design, an additional test clock is used in conjunction clock time.
with the functional clock to achieve this. Scan requires an
extra line for reset, while we can achieve reset of the SCAN/
N Modes C1 C2 f1 f2 f3 f4
MISA register in three clock cycles using the same two
control lines C1 and C2, as explained in the next section. 1 Normal Operation 11 0111
The multiplexer at the data output imposes some Concurrent MISA
performance penalty in normal operation. The amount of
this added delay will depend to a large extent on how the 2 Pseudorandom Circu- 01 0110
new memory element is implemented and laid out in CMOS, lar Testing
and the application. Nevertheless, we reasonably estimate 3 Normal Operation 10 0101
that these area and performance overheads will be modest SCAN Shift
for most applications, and will be more than justified by the
significantly reduced test costs in multi-million transistor 4 State capture in 00 1000
circuits. SCAN Register
Fig. 2a
3. Operating Modes
Concurrently, the output of D2 in MEi (which is also
Figure 2 summarizes the four operational modes of our active concurrently because it is also clocked by CK1 and
new memory element corresponding to the four possible CK2) is compared with that for D1 in MEi and the new
combinations of the control inputs C1 and C2. The context value is captured in the scan input of D2 in the next memory
for this discussion is the classical model of a sequential element MEi+1 in the SCAN/MISA shift register. Mode 2
circuit comprising of a combinational logic block and with C1=0, C2=1 is the pseudorandom circular testing
memory elements. For simplicity, only a single D flip flop mode. In this mode the inputs to the combinational logic
memory element MEi, implemented using our multi-mode come from the MISA register, while the current state in the

Mode 1 - Normal operation & Concurrent MISA

D1 MEi
+ D1 MEi

D2 MEi CL D2 MEi+1

Mode 2 - Pseudorandom Circular Testing

D1 MEi
+ D1 MEi

D2 MEi CL D2 MEi+1
 Mode 3 - Normal operation & SCAN Shift
D1 MEi
+ D1 MEi

D2 MEi CL D2 MEi+1

Mode 4 - State Capture in SCAN Register

D1 MEi
+ D1 MEi

D2 MEi CL D2 MEi

Fig. 2b

primary D1 flip flops is compared with the current same values. These are compared in the EXOR gate in
signature in the MISA register in the EXOR gate and the mode 2 in the next clock cycle. Thus the SCAN/MISA flip-
next MISA register state generated. While the xN + 1 flops D2 in each element will get a ‘0’ at their scan input.
characteristic polynomial for the MISA register is, in Going back to mode 4 at the next clock applies the ‘0’ state
general, not primitive, it has been shown [5, 6, 7, 9] that the to the combinational logic. Normal operation can continue
states for this MISA are analogous to pseudorandom from this reset state as desired.
patterns. In conventional circular BIST [7] the states of the Figure 3 shows a sequential circuit implemented by use
data registers are applied to the combinational block. of the new memory element. In addition to the Data-In input
Unlike that in the proposed pseudorandom circular BIST and to the Data-Out output, every memory element has a
the compacted pseudorandom states of the scan registers Scan-In input and a Scan-Out output. The Scan-Out output
acting as a MISA with feedback polynomial xN + 1 are of the memory element MEi is connected to the scan-In-
applied to the combinational block where N is the number input of the next memory element MEi+1. The internal
of memory elements. structure of the memory elements illustrates the
In mode 3 operation with C1=1, C2=0 we have normal possibilities for the different modes of operation.The
operation combined with scan shift. This is very similar to different modes of the memory elements are controlled by
mode 1 except that in this case the D2 output is serially the control signals C1 and C2.
shifted unchanged to the next memory element. This mode,
along with mode 4 (state capture in scan register) can be
4. Test Generation and Application
used to implement classical scan using our memory As in traditional scan, our new approach views the
element. problem of testing sequential circuits as that of testing the
combinational logic block with restricted access to the state
Mode 4 with C1=0, C2=0 captures the sequential circuit
inputs and state outputs of this block.
state in the scan register during scan based testing. The
input to the combinational logic comes from the SCAN/ A key capability of the new scannable memory element
MISA register element D2 in MEi, and the output is also is that it can be configured to accumulate a signature of the
captured in D2 in MEi (in addition to D1). This state can circuit states encountered during normal operation (mode
now be scanned out using mode 3. 1). This concurrently operating multiple input signature
analyzer (MISA) provides virtually complete state
Finally, reset of the SCAN/MISA register can be
observability during test, without the need for scanning out
achieved in three cycles by first going to mode 4, then to
the state for each test input. The compressed response need
mode 2, and finally back to mode 4. During the first clock
be shifted out only once at the end of the test. Further, this
cycle in mode 4, independent of the state of the machine,
MISA shift register also provides a source for introducing
both D1 and D2 flip-flops in all memory elements get the
pseudorandom inputs at the state variables during test
(without the need for scanning the state) (mode 2). This can 4. If new faults are detected, eliminate the faults from
significantly enhance test input controllability in designs the fault list and add the test vector to the test set. Go
with unreachable or hard to reach states. to step 7.
Note that the test set for a sequential circuit employing 5. Else, if possible, pick a different pseudorandom
the new memory element must be carefully selected to take vector for the primary inputs and go to step 3.
advantage of these features. By mostly using strings of test 6. If all choices for pseudorandom vectors for the
vectors whose state variables are sequentially generated by primary inputs are exhausted, pick an arbitrary choice
the MISA register, tests can be designed to run in mode 2 for primary inputs, add the test vector to the test set,
(circular testing). The need for shifting in scan patterns and go to step 7. (Note: This vector will not increase
canbe limited to those faults for which tests cannot be found fault coverage but is needed to move the MISA
in this mode. Primary inputs values for the test vectors can, register to a new state without the need for scan.)
of course, be freely controlled to maximize the number of
faults detected for each input vector. 7. Simulate and update the MISA register.
4.1 A Basic Test Generation Algorithm 8. If the last M vectors have not uncovered a new fault,
go to 10. (M is a user supplied threshold).
A simple test generation approach is to first pick
pseudorandom primary inputs to go with each state variable 9. Go to 2.
sequentially produced by the MISA register. New vectors 10. Use ATPG methods to generate tests for the
are added as long as fault simulation finds that new faults remaining faults in the combinational logic block
are covered. This part of the test can be applied to the circuit assuming full scan. (These tests are applied as in the
without the need for scanning in test vectors or scanning out traditional scan approach.)
results (except for one scan out of the final MISA
signature). Tests for the remaining random pattern resistant 4.2 Improvements
faults are generated by ATPG programs, and applied using A number of obvious improvements can be made. First,
the traditional scan approach which is also supported in our if ATPG based test generation is employed to select the
design. The basic algorithm is outlined below. primary inputs to go with each sequential state variable
Pseudorandom Input based Test Generation vector obtained from the MISA register, the overall test set
can be made much more compact, while still executable
1. Reset D2 flip flops in all memory elements. Include without scanned inputs. Also, such an ATPG based
required primary inputs and control/clock inputs in approach will find tests for some random pattern resistent
the test set. faults using sequential state variable values from the MISA
2. Pick a pseudo random vector for the primary inputs. register. Thus, the number of patterns requiring full scan
application will also be reduced.
3. Fault simulate this vector and with state inputs from
appropriate bits of the MISA register. Other possibilities for improved test generation include

X Combinational Logic Y

ME1 MEN
Data In Mx
Data Out Data In Data Out
Mx
D1 D1

Scan In Scan Out Scan In Scan Out

D2 + D2 +

CK1
CK2 Fig. 3
C1
C2
the use of the next state variables, instead of the MISA scan. Thus test application time will be reduced directly in
register, to provide the state variable inputs in situations proportion to the fraction of the original ATPG generated
where no test can be found with the latter. The idea here is test set that is essential to detect random pattern resistent
to continue obtaining tests for new uncovered faults during faults. For large designs, experience indicates q between
test generation using test sequences that do not need to be 0.05 and 0.25. This suggests that test application time
scanned in. This change would likely be needed for only a savings of up to an order of magnitude can be reasonably
single test cycle, although longer and frequent changes expected by using our proposed approach.
between the two modes can be explored. At test application,
this would involve changing the test mode with the help of
5. Delay Testing
the control signals from mode 2 (pseudorandom circular The new memory element can also support two pattern
testing) to mode 1 (normal operation with MISA). Also, tests needed for CMOS open fault testing and delay fault
seeding the MISA with one or more new scanned-in testing in both pseudorandom, as well as deterministic
patterns to go after many of the hard to detect faults without modes. Pseudorandom delay testing appears destined to
additional scanning may be more efficient than employing gain in importance because of the difficulties associated
completely unrelated ATPG derived test vectors which will with developing meaningful delay fault models for CMOS
all need to be scanned in. Finally, traditional approaches for technology. For CMOS, the true coverage for realistic delay
overlapping scan vectors required for the random pattern faults of compact delay test sets based on the available
resistent faults can also be employed to speed up test delay fault models is the subject of much debate [10]. Long
application for the difficult faults. pseudorandom tests can ensure that many types of delay
faults are detected. However, while performing such tests
4.3 Analysis
with on chip hardware support, it is important that true
A very simple estimate of the potential reduction in test delays through paths active during normal operation be
time by using the new multi-mode memory element can be measured. This is a major problem with using approaches
obtained as follows. such as classical BIST or Circular Test because of the added
Consider a design with N scan flip flops. Let the test set EXOR delay in the path leading to the MISR which only
size required to achieve the desired coverage for this design exists in the circuit only in the test mode. No BIST
using the traditional full scan approach be Ts. approach, to our knowledge, can overcome this
fundamental problem.
Then the test application time for the traditional scan
approach = (Ts + 1)N. In our structure, in modes 1 and 2, see Figure 2(b), used
for delay testing, the output compression path through the
Now let the fraction of test vectors in the test set Ts that EXOR gate is independent of the circuit path through the
cover pseudorandom pattern resistant faults be q; (q<1) combinational logic block. In mode 1, normal operation, it
Then the faults covered by (1-q)Ts vectors in the original is obvious that the real delay for the operational path is
test set can be detected by pseudorandom patterns. excited by the test stimulus. The output response is
However, the length of the corresponding pseudorandom compressed using the other path in the next clock cycle. In
test set can be expected to be much larger. Let this test set mode 2, used during pseudorandom circular testing, the test
size be pTs; where p may typically range from 1 to 10. stimulus comes from the D2 flip-flop, instead of D1.
However the slave stages of both master slave flip-flops are
In our new approach the pseudorandom test patterns do identical, and the output selection is done by the multiplexer
not have to be scanned in and only a single result signature inside the memory element standard cell so that all
has to be scanned out. Thus test application time ta for the interconnect paths outside the cell are the same. The two
new approach is ta= (pTs + N) + (qTs +1)N. paths then should have very similar delays; either can be
For the test application time reduction factor tr we obtain used to test delays in the combinational logic. Of course,
pT s + N + ( qT s + 1 ) N faults in D1 must be tested by applying at least a few delay
t r = -----------------------------------------------------
-. (eq. 1) tests in mode 1.
( Ts + 1) N Thus our new structure allows, for the first time, realistic
pseudorandom delay testing.
For large designs with N >> 1; N >> p and Ts >> N the A form of pseudorandom delay testing can be carried out
test application time reduction factor tr is tr ≈ q. using the proposed memory element by alternately placing
What this simple analysis indicates is that the time for the circuit in modes 2 and 1 during alternate clock cycles.
executing the non scanned part of the test in our scheme is The idea is to first apply a pseudorandom initial pattern V1
quite small when compared to the part that requires regular to the combinational logic from the MISA register (and the
primary inputs) in mode 2. In the next clock cycle the number of critical paths will be so tested in practice.
second vector V2 in the two-vector pattern is applied in
mode 1 from the D1 flip flop. This second vector is not
6. Fault Tolerant Design
strictly random but reflects the state under a pseudorandom The inherent redundancy of the new memory element
input captured at the last clock time. Note that the transition also makes it attractive for use in low cost fault tolerant
being observed for delay is the transition between the first design. Figure 4 shows how the concurrent MISA feature in
and second vectors, with any errors arising from delay normal operation can be exploited for error detection in a
faults to be captured in the D1 flip flop during the second duplicated fault tolerant systems. All flip flops in the two
clock period. The paths active at this time are those from D1 units are implemented using the proposed memory element.
through the combinational logic block to D1 at the next Thus in normal operation, any permanent or transient error
clock instance. Thus it is delays in the normal operation will be captured in the MISA register. Note that it is not only
path that are tested. As before, the test result is compressed errors in the state variables that affect the signature.
in the MISA register. Because input and output signals are typically buffered in
registers close to the chip interface, most errors in even
As a second approach for delay testing we propose an
these signals will be captured by the MISA.
algorithm consisting of two steps. In the first step a
relatively short pseudorandom input sequence is applied to A low cost fault tolerance approach would compare only
the primary inputs of the circuit in normal operation mode. these execution signatures between the two units. While
The D1 element and the upper path of the multiplexer of the some error latency is possible in such an approach, leading
memory elements MEi are checked. to possible incorrect outputs before error detection, such a
design may be acceptable for low cost controllers for
In the second step a long pseudorandom sequence is
mechanical systems where the control time constants are
applied to the primary inputs of the circuit in pseudorandom
relatively large (order of milliseconds). The advantage of
circular test mode (mode 2). Now the paths through the
such an approach is saving of substantial custom hardware
combinational block are extensively tested by good quality
as compared to current duplicated microprocessor based
pseudorandom sequences consisting of the pseudorandom
approaches (e.g. Stratus) where all output signals between
states of the MISA and the pseudorandom primary inputs.
the two units are compared. Recovery from transient errors
In both steps the states are compacted by the MISA. only requires a rollback to the previous checkpoint upon
Application of deterministic two pattern tests in our error detection. If this is unsuccessful (due to a permanent
structure involves applying the first vector V1 through fault) the units can be made to execute a test program whose
conventional scan shift, while generating and applying the signature is precomputed and available in the switch block.
second vector V2 by driving the circuit to the appropriate Upon completion of this test, the switch reconfigures the
state. The normal operation with scan shift, mode 3, is outputs to use the correctly operating unit.
employed to set up the two vectors. Now in mode 1 the In some situations, when the input patterns have regular
second vector V2 is processed by the combinational block properties, or if the sequence of input patterns is known, as
into V2′ and V2′ is stored in the D1 memory elements of may the case for some control systems, the MISA signature
MEi. Simultaneously V2 and the vector V1 are added can be predicted during normal operation. Then an error can
modulo 2, shifted one bit position and the resulting vector be detected and a faulty unit identified, without the need for
V1′ = shift (V1 ⊕ V2 ) is stored in the memory elements D2 testing.
of MEi+1.
Additional comparision of the scanned out signature can
Now in mode 2 V1′ is processed by the combinational lead to early detection on internal upsets not yet visible at
block into V1′′ and stored in the memory elements D1 of the outputs. This can greatly assist rollback recovery in
MEi. V2 and V1′ are added modulo 2, shifted one bit multiprocessor systems.
position and the resulting vector V3 = shift (V2 ⊕ V1′ ) is
stored in the memory elements D2 of MEi+1. 7. Conclusion
Again in mode 1 the vectors V3 and V1′′ are added In this paper a new multi-mode scannable memory
modulo 2, shifted one bit position and the compacted vector element for the design of easily testable and fault-tolerant
V4 = shift (V3 ⊕ V1′′) is stored in the memory elements D2 sequential circuits was introduced. In addition to normal
of MEi+1. Now the vector V4 can be shifted out. operation- and scan-modes a signature of the states in the
multi-input linear shift register MISA can be concurrently
Such test application will be slow, and will require determined at the expense of a modest area and
considerable test generation effort to correctly sequence the performance overhead. This concurrent signature provides
two inputs. However, it is expected that only a limited virtual complete state observability during test whithout
 1

Switch Block
Rollback or
Testing

Comparator
Encoded Input 1 Unit 1 r1
n
Scan In 1 Scan Out 1 r2
Normal operation &
Concurrent MISA

Signature 1
1 f
Encoded Input 2 Unit 2 n
Scan In 2 Scan Out 2 Signature 2
Normal operation &
Concurrent MISA

Fig. 4

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