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Chapter 3 ISA

The document discusses the principles and characteristics of the MIPS Instruction Set Architecture (ISA), a RISC design that emphasizes simplicity, small size, and making common cases fast through the use of a load/store architecture, fixed-length instructions, and limited addressing modes. It describes the MIPS register set, memory organization, instruction formats including R-type, I-type, and J-type, procedure calls using a stack, and contrasts it with Intel's IA-32 CISC architecture.

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53 views4 pages

Chapter 3 ISA

The document discusses the principles and characteristics of the MIPS Instruction Set Architecture (ISA), a RISC design that emphasizes simplicity, small size, and making common cases fast through the use of a load/store architecture, fixed-length instructions, and limited addressing modes. It describes the MIPS register set, memory organization, instruction formats including R-type, I-type, and J-type, procedure calls using a stack, and contrasts it with Intel's IA-32 CISC architecture.

Uploaded by

shahzadktk133
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We take content rights seriously. If you suspect this is your content, claim it here.
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Instruction Set Architecture(ISA) and MIPS

1. ISA principles of RISC


● Simplicity favors regularity( For example, every arithmetic instruction of MIPS has three
operands and all instructions have the same length 32 bits)

● Smaller is faster( For example Limited number of registers 32 registers for


MIPS. A very large number of registers would increase the clock cycle time
because it takes longer for an electronic signal to reach its destination.)

● Good design demands a compromise ( It is preferred to have a single


instruction format and all instructions of the same length. But there is a
conflict between these two desired properties . MIPS' designers had to
make a compromise and chose the second property.)

● Make the common case fast.(For example the use of immediate addressing)

2. Two RISC goal are mentioned in this chapter:


● Simple hardware design
● Good Performance(low average CPI( # of clock cycles per instruction)and
high clock rate)

3. The following are the most important characteristic of MIPS' registers


● 32 32-bit general purpose registers(R0 always contains 0), 32 FP registers and two registers
Hi Lo for multiplication and division.
● Program Counter(PC): holds the address of the next instruction to be executed.
● Each register has a number and a name

MIPS Register Conventions


● $s0,$s1,…$s7 map to registers 16-23: used for values that must maintained across
function calls and usually used by the main program to save values that do not change
during the functions execution.
● $t0,$t1,….$t7 map to registers 8-15:used for storing temporary values for functions
and main program.
● $t8 - $t9 map to 24-25: used for storing temporary values for functions
and main program.
● Register$0 always contains 0.
● Register $1 ($at) is reserved for the assembler.
● Register $31($ra) holds return address.
● Register $29($sp) is the stack pointer.
● Registers $4-$7($a0,$a1,$a2,$a3) are for passing parameters to functions.
● Registers $2-$3($v0,$v1) are for return values from functions and also for results and
expression evaluation.
● The two registers Hi and Lo are used to hold the result of multiplication and division
operations.
● Registers $26 and $27( $k0 and $k1) are reserved for the operating system.
● Register $28($gp) is used to hold the global pointer.
● Register$30($fp) is used to hold the frame pointer.

4. The memory of MIPS is byte-addressable;and the word length is 32 bits and the
address length is also 32 bits. Words must always start at byte addresses that are multiples
of 4. This property is called alignment. MIPS is a big-endian machine ( IBM36/370,
Motorola, SPARC, and Mac are also big-endian machines). This means when a multi- byte
data is stored in memory , the lsb is at the highest address and msb is at the lowest
address. A little-endian machine stores such data in the reverse order ( intel 80x86, DEC
Vax,DecAlpha are little-endian machines). Suppose

x: .word 3 ,

Big-endian machine Little-endian machine


100 [00000000] x: 100 [00000011]
101 [00000000] 101 [00000000]
102 [00000000] 102 [00000000]
103 [00000011] 103 [00000000]

In both cases the address of x is 100.

5. The most important characteristics of MIPS' instructions are :

● Only few instruction for accessing the memory: lw and sw( and lh,sh,lb,sb).
● Only two conditional branches, beg and bne. Other branches are implemented
using slt instruction.
● lui needed to load immediate values larger than 16 bits.
● Fixed instruction size (32 bits) and three simple formats
R-format, I-format and J- format
● R-format instructions:

op(6 bits) rs( 5 bits) rt( 5 bits) rd(5 bits) shamt( 5 bits) funct (6 bits)

Examples of this type are the arithmetic and logical instructions. rs and rt
are the operands and the result will be in rd; the field shamt is set to zero ;
and the two fields op and funct are used to indicate the type of arithmetic
operation. add rd , rs, rt rd  rt+ rs
Also this format is used for some branch instructions,

jr rs jump to the instruction whose address is in rs.

For this instruction rt , rd, and shamt are set to zero.

Also is used for some conditional instructions,

slt rd, rs,rt if (rs<rt) set rd to 1 else set rd to 0

For all a these instruction shamt is set to zero The field shamt is used to indicate
the #of bits to be shifted.

● I-format instruction(immediate –format or data transfer- format )

op(6 bits) rs(5 bits) rt(5 bits) address/immediate(16 bits)

Examples of this format

lw rt, immediate(rs) rt  M[ rs+ immediate] // load one word


sw rt, immediate(rs) M[ rs+ immediate]  rt // store one word
beq rs, rt, label(immediate address) if (rs==rt) branch to label
bnq rs, rt, label if(rs!= rt) branch to label
slti rt,rs, immediate if (rs< immediate) rt=1 else rt= 0

● J-format instruction(jump-format)

op( 6bits) target address(26 bits)

j label(target address)

jal label jump to label and save the address of the next instruction in the
register $ra= PC +4.

6. MIPS has many other instructions and macros. Macros are also called pseudo
instructions and has a format similar to the assembly language format of
instructions but each macro is equivalent to one ore more instructions.
During the assembly process the assembler replaces each micro by its
equivalent. In this way the assembly language is extended to provide new
operations. For example b label( branch unconditionally to the instruction at
the label).
7. The addressing modes of MIPs):

Register addressing: where the operand is a register;


Base or displacement addressing: where the operand is the memory location
whose address is the sum of a register and a constant in the instruction;

Immediate addressing: where the operand is a constant within the instruction


itself;

PC-relative addressing: where the address is the sum of the PC and a constant
in the instruction;

Pseudodirect addressing: where the jump address is the 26 bits of the


instruction with the upper bits of the PC.

8. procedure calls

At address 400 we have


call procAddr

It is implemented by the caller

jal procAddr // jump and store the return address404 in the register $ra

At the end of the calle(the return statement) ,the instruction jr $ra is executed.

9. For nested calls , the stack is used . The stack grows toward low memory
addresses. Push and pop are implemented by lw, sw, add, and sub. For push
decrement the stack pointer and for pop , increment the stack pointer.

9. Read Section 2.16(Text#2) that describes the Intel IA-32 one of the most
popular CISC processor.

10. Fallacies:
 More powerful instructions mean higher performance.
 Write in assembly language to obtain the highest performance.

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