CENTRAL

PROCESSING
UNIT
Computer Architecture & Organization
OBJECTIVES
• Identify the components of the central
processing unit and how they work
together and interact with memory
• Describe how program instructions are
executed by the computer
• Differentiate between CISC and RISC
architectures.
Introduction to CPU

• A PIECE OF HARDWARE THAT CARRIES OUT THE

INSTRUCTIONS OF A COMPUTER PROGRAM
• PERFORMS THE BASICS:
• ARITHMETIC
• LOGIC
• I/O

• EVERY INSTRUCTIONS, NO MATTER HOW SIMPLE or BIG

IS THE PACKAGE, HAS TO GO THROUGH THE CPU
Introduction to CPU
• The CPU is the primary component of a
computer that processes instructions.
• It runs the operating system and applications,
constantly receiving input from the user or active
software programs.
• It processes the data and produces output,
which may stored by an application or displayed
on the screen.
INTRODUCTION TO CPU

“Brain” of the computer system

~COMBINATION OF CPU & MEMORY

Converts data into information

INTRODUCTION TO CPU
For a large machine:
• A printed circuit board
For a personal computer:
• Housed in a single chip called microprocessor
• Located inside the computer case on the motherboard.
Contains tens of millions of tiny transistors
Resides inside a box known as the system unit, along
with various support devices and tools for storing
information
INTRODUCTION TO CPU

CPUs aren’t only found in desktop or laptop

computers, many electronic devices now rely on
them for their operation.
Mobile phones, DVD players and washing
machines are examples of equipment that have a
CPU.
Introduction to CPU : Why CPU?
It is processor because it
processes (moves and
It is central because it is the
calculate ) data
centre of data processing

Central Processing Unit

It is a unit because it is a
chip which contains
millions of transistors
CPU PROCESS DATA CYCLE

Store
 CPU PROCESS DATA CYCLE

Fetch Decode Execute Store

 CPU PROCESS DATA CYCLE
• Processor level • Register level
• Architectural Features specified • Specify internal operation of
processor-level components at the
word level
• Category:
» Interfaces • Category:
» Instruction sets » Registers
» Data Representation » Counters
» Memories
» ALUs
» Clocks
» Combinational logic
addressing modes in processor

AddressingModes
Immediate
Direct
Indirect
Register
RegisterIndirect
Displacement
Stack
Components of CPU
 Components of CPU
 Control Unit
 Controls the operation of the CPU and hence the
computer
 Arithmetic and Logic Unit (ALU)
 Performs the computer’s data processing function
 Registers
 Provide storage internal to the CPU
 CPU Interconnection
 Some mechanism that provides for communication
among the control unit, ALU, and registers
Components of CPU
Control unit
• Moves data and instructions between main memory
and registers
• coordinates the components of a computer system.
• It reads program instruction .
• Regulate the timing of all operations carried out in the
CPU.
• Control the sequence in which the instructions are to
be executed.
• It uses registers to temporarily store the data it needs.
Components of CPU
Arithmetic logic unit (ALU)
• Definition : digital circuit that performs integer arithmetic
and logical operations
• Performs computation and comparison operations
• Computation / Arithmetic operations:
• E.g : + , - , * , /
• Logical operations:
• Not, And, OR, >, <, >=, <=, =
• performs its operations on whole numbers only.
Components of CPU
Registers
Storage locations that hold inputs and
outputs for the ALU
• Is a Small, temporary storage locations within the CPU
• Can be accessed more quickly .
• CPU load data from a larger memory into registers
• used for
• arithmetic,
• manipulated, or
• tested,
• Can hold data, an address or an instruction
• Manipulated data is then often stored back in main memory.
Components of CPU
Registers
• Registers are temporary storage areas for program instructions
or data.
• They are not a part of memory; rather they are special additional
storage locations that offer the advantage of speed.
• Registers work under the direction of the control unit to accept,
hold, and transfer instructions or data and perform arithmetic or
logical comparisons at high speed.
• The control unit uses a data storage register the way a store
owner uses a cash register-as a temporary, convenient place to
store what is used in transactions.
Types of CPU Registers

General – • Hold data for currently executing

Purpose program that is needed quickly or
frequently
Register

Special- • Store information about currently

Purpose executing program
• Store information about status of CPU
Register
 Special-Purpose Registers
• Program Count Register (PC)
• Also called instruction pointer, contains the address of the next instruction
pair to be fetched from memory
• Instruction Register (IR)
• Stores instruction fetched from memory, Contains the 8-bit opcode instruction
being executed
• Memory Address Register (MAR) –
• Specifies the address in memory of the word to be written from or read
into the MBR
• Memory Buffer Register (MBR)
• Contains a word to be stored in memory or sent to the I/O unit
• Also used to receive a word from memory or from the I/O unit
• Status Registers
• Status of CPU and currently executing program
• Flags (one bit Boolean variable) to track condition like arithmetic
carry and overflow, power failure, internal computer error 7-28
Register Operations
• Stores values from other locations (other registers and memory)
• Addition and subtraction
• Shift or rotate data
• Test contents for conditions such as zero or positive

7-29
 Bus Structures
Computer Architecture describes the way these components are connected
and the manner in which they communicate
Input
Output Memory Processor

Single-bus structure.

n - bits (a word) of data are transferred in parallel by the bus

In addition the bus have lines for address and control purposes.
- Address lines determine which two devices can use the bus
- Control lines determine the type of operation
Basic Operational Concepts

• Program consists of list of instructions stored in memory

• Data to be used also stored in memory
• Individual instructions brought from memory into
processor to be executed
Add LOCA, R0
• Fetch the instruction from memory
• Address of the memory location for the instruction
• The operand at LOCA is fetched and added to contents
of R0
• The resulting sum is stored in R0
What is a Cache?
• The cache is a very high speed, expensive piece of memory , which is
used to speed up the memory retrieval process.
• Due to it ’s higher cost, the CPU comes with a relatively small amount of
cache compared with the main memory.
• Without cache memory, every time the CPU requests for data, it would
send the request to the main memory which would then be sent back
across the system bus to the CPU. This is a slow process.
• The idea of introducing cache is that this extremely fast memory would
store data that is frequently accessed and if possible, the data that is
around it.
• This is to achieve the quickest possible response time to the CPU.
Components of CPU

Cache
• To reduce the average time to access memory .
• The cache is:
• a smaller ,
• faster memory
• stores copies of most frequently used data from
the main memory.
 Types of Cache
• Internal cache
• Level 1 (L1)
• Built into microprocessor
• Up to 128KB
• External cache
• Level 2 (L2)
• Separate chips
• 256KB or 512 KB
• SRAM technology
• Cheaper and slower than L1
• Faster and more expensive than memory
Process Flow
 An Example: Multi-Core Systems

L2 CACHE 1
L2 CACHE 0
SHARED L3 CACHE

DRAM INTERFACE
Multi-Core

DRAM BANKS
Chip CORE 0 CORE 1

DRAM
MEMORY
CONTROLLER

L2 CACHE 2

L2 CACHE 3
CORE 2 CORE 3

*Die photo credit: AMD Barcelona

Increasingly Complex Systems

Past systems

Microprocessor Main Memory Storage (SSD/HDD)

 FPGAs Increasingly Complex Systems
Modern systems

Hybrid Main Memory

Heterogeneous Persistent Memory/Storage

Processors and
Accelerators

(General Purpose) GPUs

Factors that affect the performance of a CPU

1. Number of existing transistors

2. Data bus width and word size
3. Clock speed
4. Operations per microprocessor cycle
5. Use of parallel processing
6. Type of chip
 RISC and CISC Architectures
• Hardware designers invent numerous technologies & tools to
implement the desired architecture in order to fulfill these
needs.
• Hardware architecture may be implemented to be either
hardware specific or software specific, but according to the
application both are used in the required quantity.
• As far as the processor hardware is concerned, there are 2 types
of concepts to implement the processor hardware architecture.
First one is RISC and other is CISC.
• Hardware of the Intel is termed as Complex Instruction Set Computer
(CISC)
• Apple hardware is Reduced Instruction Set Computer (RISC).
CISC Architecture
 CISC stands for Complex Instruction Set Computer
 CISC is a instruction set architecture (ISA) in which each instruction
can execute several low-level operations, such as a load from memory,
an arithmetic operation, and a memory store , all in a single instruction.
 CISC are chips that are easy to program and which make efficient use
of memory.
 Examples of CISC processor families are
 IBM 370/168 – It was introduced in the year 1970. CISC design is a 32 bit
processor and four 64-bit floating point registers.
 VAX 11/780 – CISC design is a 32-bit processor and it supports many
numbers of addressing modes and machine instructions which is from
Digital Equipment Corporation.
 Intel 80486 – It was launched in the year 1989 and it is a CISC processor,
which has instructions varying lengths from 1 to 11 and it will have 235
instructions.
CHARACTERISTICS OF CISC ARCHITECTURE
• Instruction-decoding logic will be
Complex.
• One instruction is required to support
multiple addressing modes.
• Less chip space is enough for general
purpose registers for the instructions
that are 0operated directly on
memory.
• Various CISC designs are set up two
special registers for the stack pointer,
handling interrupts, etc.
• MUL is referred to as a “complex
instruction” and requires the
programmer for storing functions.
RISC Architecture
• RISC Stands for Reduced Instruction Set Computer
• RISC is a type of microprocessor architecture that utilizes a small,
highly- optimized set of instructions, rather than a more specialized
set of instructions found in other types of architectures.
• RISC represents a CPU design to make instructions execute very
quickly.
• RISC processors take simple instructions and are executed within a
clock cycle
• Example, Apple iPod and Nintendo DS.
 RISC ARCHITECTURE CHARACTERISTICS
• Simple Instructions are used in RISC architecture.
• RISC helps and supports few simple data types and synthesize
complex data types.
• RISC utilizes simple addressing modes and fixed length
instructions for pipelining.
• RISC permits any register to use in any context.
• One Cycle Execution Time
• The amount of work that a computer can perform is reduced
by separating “LOAD” and “STORE” instructions.
• RISC contains Large Number of Registers in order to prevent
various number of interactions with memory.
• In RISC, Pipelining is easy as the execution of all instructions
will be done in a uniform interval of time i.e. one click.
• In RISC, more RAM is required to store assembly level
instructions.
• Reduced instructions need a less number of transistors in
RISC.
• RISC uses Harvard memory model means it is Harvard
Architecture.
• A compiler is used to perform the conversion operation
means to convert a high-level language statement into the
code of its form.
ARCHITECTURE COMPARISONS
 CISC RISC

Emphasis on hardware Emphasis on software

Includes multi-clock complex instructions Single-clock, reduced instruction only

Memory-to-memory: Register to register:

"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions

Small code sizes large code sizes

Transistors used for storing complex Spends more transistors on memory
instructions registers

High cycles per second Low cycles per second

Variable length Instructions Equal length instructions which make

pipelining possible

Primary goal is to complete a task in as Primary goal is to speedup individual

few lines of assembly as possible instruction
 Instruction Set:
• Group of instructions given to execute the program and they direct
the computer by manipulating the data.
• Instructions are in the form of Opcode (operational code) and
Operand .
• Opcode is the instruction applied to load and store data, etc.
• The operand is a memory register where instruction applied.
 This underlines the importance of the instruction set architecture.
There are two prevalent instruction set architectures
Thus..
• CPU performance is given by the fundamental law

• Thus, CPU performance is dependent upon Instruction Count, CPI

(Cycles per instruction) and Clock cycle time. And all three are
affected by the instruction set architecture.
 Instruction Representation
• CPU operation is determined by the instruction it executes
• Collection of these instructions that a CPU can execute forms its Instruction
Set
• An instruction is represented as sequence of bits, for example:
1001 0010 0000 0011 1011 1011 1000 0001

9 2 0 3 B B 8 1

Opcode Operand1 Operand2

• Instruction is divided into fields

• Opcode indicates the operation to be performed, eg., 92 above indicates a
copy operation – we need two operands – one source and other
destination
• Opcode represents
• nature of operands (data or address), operand 1 is address and operand 2 is data
• mode (register or memory), operand 1 is memory, and operand 2 is immediate data
 Basic Instruction Types
Not all instructions require two operands
• 3-address instructions
Operation Source1, Source2, Destination
e.g. Add A, B, C ;C=A+B
• 2-address instructions
Operation Source, Destination
e.g. Move B, C ;C=B
Add A, C ;C=C+A
Here Source2 is implicitly the destination
• 1-address instructions
e.g. Load A
Store C
• 0-address instructions
e.g. Stop
 Simple Instruction Set
Assume we have a processor whose Instruction Set consists of four
machine language instructions
• Move from a memory location to a data register in CPU
• Move from a data register in CPU to a memory location
move $0000 0000
• Add the contents of a memory location to a data register add
• Stop move

Suppose our program for Z = X + Y looks like: stop

Move X, D0
Add Y, D0
Move D0, Z
Stop
This program is coded into machine instruction and suppose is loaded into memory
starting at location $0000 0000
• How does the CPU know which instruction to execute?
• There is a dedicated register in CPU called Program Counter (PC)
that points to the memory location where next instruction is
stored
Therefore, at start PC = $0000 0000
• Instruction is in Main Memory – it is to be transferred
(fetched) to CPU to be executed
• CPU has an Instruction Register (IR) that holds the instruction
• What kind of instruction is to be executed?
• CPU has its own Instruction Interpreter (Decoder)
• Followed by Instruction execution
• Next instruction follows. PC is incremented by length of
instruction just completed
 Mechanism of Transferring Data from MM to CPU
CPU has an external bus that connects it to the Memory and I/O devices.
The data lines are connected to the processor via the Memory Data
Register (MDR)
The address lines are connected to the processor via the Memory Address
Register (MAR)
• Memory address from where the instruction/data is to be accessed is copied into
MAR
• Contents of MAR are loaded onto address bus
• Corresponding memory location accessed MAR
Address bus

• Contents of this location put onto data bus

Data bus
• Data on data bus loaded into MDR MDR

Control bus
CPU MM
R/W
 General Purpose Register (GPR)Architecture
Its functional units are:
Data Registers : D0, D1, D2,..., D7 for arithmetic operations – holds any kind of data
Address Registers : A0, A1, A2,..., A7 serve as pointers to memory addresses
Working Registers : several such registers – serve as scratch pads for CPU
Program Counter (PC) holding the address in memory of the next instruction to be
executed. After an instruction is fetched from memory, the PC is automatically
incremented to hold the address of, or point to, the next instruction to be executed.
Instruction Register (IR) holds the most recently read instruction from memory while it
is being decoded by the Instruction Interpreter.
Memory Address Register (MAR) holds the address of the next location to be accessed
in memory.
Memory Buffer Register (MBR or MDR) holds the data just read from memory, or the
data which is about to be written to memory. Buffer is referring to temporarily holding
data.
Status Register (SR) to record status information
 GPR CPU

Data bus
0 Register MBR
1
File
2 IR

3 Address bus
MAR

Interprete
ALU r

PC
Memory
Control

16 bit Incremen
8 bit t
CPU Memory
 Program Execution
Fetch Cycle:
• Processor fetches one instruction at a time from successive memory locations
until a branch/jump occurs.
• Instructions are located in the memory location pointed to by the PC
• Instruction is loaded into the IR
• Increment the contents of the PC by the size of an instruction
Decode Cycle:
• Instruction is decoded/interpreted, opcode will provide the type of operation to
be performed, the nature and mode of the operands
• Decoder and control logic unit is responsible to select the registers involved and
direct the data transfer.
Execute Cycle:
• Carry out the actions specified by the instruction in the IR
Execution for add D1,D2 in a GPR processor
MAR  PC

MDR  M[MAR]

Fetch
PC  PC + 2

IR  MDR

Decode

D2  D1 + D2
Execute
 GPR CPU

Data bus
0 Register MBR
1
File
2 IR

3 Address bus
Type equation here. MAR

Interprete
ALU r

PC
Memory
Control

16 bit Incremen
8 bit t
CPU Memory
 Execution for add X,D0 in a GPR processor
MAR  PC

MDR  M[MAR]

Fetch
PC  PC + 2

IR  MDR

Decode

Address X extracted from IR MAR  IR (X)

Contents of Address X
transferred to MDR MDR  M[MAR] Execute

Contents of Address X added to

D0 D0  MDR + D0
 GPR CPU

Data bus
0 Register MBR
1
File
2 IR

3 Address bus
Type equation here. MAR

Interprete
ALU r

PC
Memory
Control

16 bit Incremen
8 bit t
CPU Memory
 Instruction Execution Time
Clock Cycles (P) – regular time intervals
defined by the CPU clock
Clock Rate, R = 1/P cycles per second (Hz)
500 MHz => P = 2ns
1.25 GHz => P = 0.8ns MicroStepNumberofClockCycles

RegisterTransfer1

For each instruction: Decoding2

Add2
Fetch: Total 12 clock cycles
Multiply5
MAR  PC 1
MemoryAccess10
MDR  M[MAR] 10
IR  MBR 1
Decode: 2 clock cycles
Execute: depends on instruction
 Accumulator(Acc) Architecture
• Its functional units are same as GPR architecture, except there is only
ONE register – accumulator (Acc) – instead of the Register File
Ex: Z = X + Y
Move contents of location X to Acc
Add contents of location Y to Acc
Move from Acc to location Z
Stop
• All operations and data movements are on this single register
• Most of the instructions in the instruction set require only one Operand
• Destination and Source are implicitly Acc
• Leads to shorter instructions but program may be slower to execute since
there are more moves to memory for intermediate results (to free Acc)
• May lead to inefficiency
 Accumulator Architecture CPU

Data bus
Acc MBR

IR

Address bus
MAR

Interprete
ALU r

PC
Memory
Control

16 bit Incremen
10 bit t
CPU Memory
 Execution for Add Y in an Acc Architecture
MAR  PC

MDR  M[MAR]

Fetch
PC  PC + 2

IR  MDR

Decode

Address X extracted from IR MAR  IR (X)

Contents of Address X
transferred to MDR MDR  M[MAR] Execute

Contents of Address X added to

Accumulator Acc  MDR + Acc
 GPR vs Acc
Let the following instructions be allowed:
For GPR machine (with 4 data reg) For Accumulator machine
• Move 𝑅 𝑖 , 𝑅 𝑗 ; 𝑅𝑖 ← 𝑅𝑗 • Add x ; 𝐴𝑐𝑐 ← 𝐴𝑐𝑐 + M[X]
Move 𝑅 𝑖 , M[X] ; 𝑅 𝑖 ← M[X] • Sub x ; 𝐴𝑐𝑐 ← 𝐴𝑐𝑐 − M[X]
Move M[X] , 𝑅 𝑖 ; M[X] ← 𝑅 𝑖 • Mult x ; 𝐴𝑐𝑐 ← 𝐴𝑐𝑐 ∗ M[X]
• Add 𝑅 𝑖 , M[X] ; 𝑅 𝑖 ← 𝑅 𝑖 + M[X]
• LD x ; 𝐴𝑐𝑐 ← M[X]
Add 𝑅 𝑖 , 𝑅 𝑗 ; 𝑅𝑖 ← 𝑅𝑖 + 𝑅𝑗
• ST x ; M[X] ← 𝐴𝑐𝑐
• Sub 𝑅 𝑖 , M[X] ; 𝑅𝑖 ← 𝑅𝑖 −
M[X] • Stop
Sub 𝑅 𝑖 , 𝑅 𝑗 ; 𝑅𝑖 ← 𝑅𝑖 − 𝑅𝑗
• Mult 𝑅 𝑖 , 𝑅 𝑗 ; 𝑅𝑖 ← 𝑅𝑖 ∗ 𝑅𝑗 Note that M[X] = x
• Stop
 GPR vs Acc
Assembly Program for a <- (x + y) * (x – y)

For GPR machine (with 4 data reg) For Accumulator machine

Move 𝐷0, 𝑋 LD X
Add 𝐷0, 𝑌 ADD Y
Move 𝐷1, 𝑋 ST C
Sub 𝐷1, 𝑌 LD X
Mult 𝐷0, 𝐷1 SUB Y
Move 𝐴, 𝐷0 MULT C
Stop ST A
STOP
THANK YOU