EEE 204

Microcomputer
Organization
Asst. Prof. Dr Mahmut AYKAÇ

CHAPTER 3
3.5 MSP430 Memory Organization
Big Endian: In the big endian convention, data is stored with the most significant
byte in the lowest address and the least significant byte in the highest address.
Little Endian: In the little endian convention, data is stored with the least significant
byte in the lowest address and the most significant byte in the highest address.

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3.5 MSP430 Memory Organization
Most hardware memory words nowadays are one byte length. As explained above,
each memory word has an address attached to it, referred to as its physical address,
which is encoded by the group of the MCU address bus bits. Memory blocks one
byte length are called banks.

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3.5 MSP430 Memory Organization
Example: The debugger of a certain microcontroller presents memory information
in chunks of words in the list form shown below, where the first column is the
address of the word in the second column. Following the debuggers’ conventions,
all numbers are in hex system. If more than one word is on the line, the address is
for the first word only. Assuming that all data is effectively 16-bit wide, break the
information into bytes with the respective address, (a) assuming little endian
convention, and (b) assuming big endian convention.
F81E: E0F2 0041 0021
F824: 403F 5000
F828: 831F

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3.6.1 Anatomy of an I/O Interface
Control Registers: Allow for configuring the operation of the device and the interface
itself. One or several control registers can be provided depending on the complexity of the
interface. Sometimes this type of register is called Mode or Configuration Register.
Status Register: Allow for inquiring about the device and interface status. Flags inside
these registers indicate specific conditions such as device ready, error, or other condition.
Data Registers: Allow for exchanging data with the device itself. Unidirectional devices
might have only one data register (Data-in for input devices or Data-out for output devices).
Bi-directional I/O interfaces include both types.

Fig. Anatomy of an I/O interface

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3.6.1 Anatomy of an I/O Interface
Direction Register (PxDIR): Selects in or out direction function for pin, with 1 for output
direction and 0 for input direction.
Input Register (PxIN): This is a read-only register. The value changes automatically when
the input itself changes.
Output Register (PxOUT): to write signal to output. This is a read-and-write register.
Function Select Register (PxSEL): Used to select between I/O port or peripheral module
function. With PxSEL.n = 0, pin Px.n operates as an I/O pin port; with PxSEL.n = 1, as a
module pin.
Fig. Basic IO Pin hardware configuration:
a) Basic I/O register’s functions
b) Pull-down
resistor for inputs
c) Pull-up resistors

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3.6.1 Anatomy of an I/O Interface
Let’s say for example, pins 7 to 3 of port 6 are to be used as output pins, and pin 2
for operating the module, then we should use appropriate CPU instructions to write
0xF8 in the P6DIR register and 04h in the P6SEL register.
Since the input port goes through a three-state buffer, it is not advisable to leave it
floating when the pin operates in input mode. It is necessary to connect a pull-up or
a pull-down resistor.
Additional configuration registers might be included as part of an I/O port.
Examples include registers to configure interrupt capabilities in the port, or to use
internal pull-up/pull-down resistors, and other functions.

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3.7.1 Register Transfer Notation
It is important for the programmer to have a notation available for operations in
MCU environments, independent of the specific MCU architecture but taking into
consideration the features of the systems. One such notation is the register transfer
notation (RTN).
After executing an instruction, the contents of a register or cells in memory may be
written upon with a new datum. In this case, the register or cell being modified is
called destination. The source causing the change at destination may be a datum
being transferred (copied) or the result of an operation. This process is denoted in
abstract form as

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3.7.1 Register Transfer Notation
The notation in programmer’s model for the different operands that may be used
in RTN are as follows:
1. Constants: These are expressed by their value or by a predefined constant name,
for example 24, 0xF230, MyConstant. Constants cannot be used in destination.
2. Registers: These are referred to by their name. If it is in abstract form without
reference to a particular CPU, it is customary to use Rn, where n is a number or
letters.
3. Memory and I/O: These are referred to by the address in parenthesis, as
in(0x345E), which means “The data in memory at address 0x345E.” Notice that it is
data address, not physical address. If the address information is contained in
register Rn we write (Rn), meaning by that “The data in memory at address given by
Rn”. We also say that the register points to the data.

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3.7.1 Register Transfer Notation
Example: The following transactions illustrate RTN for memory operands. For these
examples, let us assume word-size data at addresses before each transaction as
[0246h] = 32AFh and [028C] = 1B82h. Moreover, let us assume little endian storage.

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3.7.1 Register Transfer Notation
Example: Assume two 16-bit registers, R6 and R7, with contents R6 = 4AB2h and
R7 = 354Fh, respectively. Moreover, assume words at addresses [4AB2h] = 02ACh,
[4C26h] = 94DFh and [4AB8h] = 3F2Ch. Assume little endian convention when
necessary. The following examples illustrate more RTN expressions:

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3.7.5 Addressing Modes
Addressing modes can be defined as the way in which an operand is specified
within an instruction so as to indicate where to find the data with which the
operation is executed.
In general, the data to be used or stored in a transfer or in an arithmetic or logic
instruction can be located in only one of the following possible places:
1. It may be explicitly given,
2. It may be stored in a CPU register,
3. It may be stored at a memory location, or
4. It may be stored in an I/O port or peripheral register.

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ADDRESSING MODE USAGE

Image Courtesy of
Recording Connection of Canada
Register Mode
The operand is the CPU register Rn and the datum (data) is contained in Rn.

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Immediate Mode
In this mode, the value of the operand Number is the datum. Immediate mode is
reserved only for source operands, since a number cannot be changed by an
operation.

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Absolute Mode

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Symbolic Mode
Mode—syntax: Number. “Number” is the address where the datum is located.

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Indirect (Register )Mode
The datum is found in the memory location whose address is given by the
contents of register Rn. We say that the register points at the datum.

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Indexed Mode
The datum is found in the memory location whose address is given by the contents
of register Rn. We say that the register points at the datum.

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Examples
Initial Condition After

mov R8, R6

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Examples
Initial Condition After

mov @R8, R6

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Examples
Initial Condition After

mov R10, 56h(R6)

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Examples
Initial Condition After

mov #0x025A, R10

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Examples
Initial Condition After

mov 0x025A, R10

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Examples
Initial Condition After

R6←R6 + R8 in RTN, means “add the contents of registers R8 and R6,

and store the result in Register R6”. Since 0200h + 0252h = 0452h,
add R8, R6 Then R6 = 0452h after this instruction.

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Examples
Initial Condition After

R6←R6 − (R8) in RTN, means “subtract from the contents of R6 the

data in memory located at the address provided by register R8, and
sub @R8, R6 store result in Register R6”. Since R8=0252h, we search for address
0252h in the memory space where we see [0252h] = 2ABEh.
Now 0200h − 2ABEh = D742h.
Therefore, R6 = D742h after this instruction.

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Examples
Initial Condition After

(R6 + 56h) ← R10.xor.(R6 + 56h) in RTN, means “perform a

bitwise XOR operation with the contents of register R10 and the
xor R10, 56h(R6) content of the memory location whose address is found by
adding 56h to the contents of register R6, and store the result
in the same memory location”.
Since R10 = 32FCh and (R6+56h)=(0256h)=1234h

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