FDP038AN06A0 / FDI038AN06A0

February 2005

FDP038AN06A0 / FDI038AN06A0
N-Channel PowerTrench® MOSFET
60V, 80A, 3.8mΩ
Features Applications
• rDS(ON) = 3.5mΩ (Typ.), VGS = 10V, ID = 80A • Motor / Body Load Control
• Qg(tot) = 95nC (Typ.), VGS = 10V • ABS Systems
• Low Miller Charge • Powertrain Management
• Low QRR Body Diode • Injection Systems
• UIS Capability (Single Pulse and Repetitive Pulse) • DC-DC converters and Off-line UPS
• Qualified to AEC Q101 • Distributed Power Architectures and VRMs

Formerly developmental type 82584 • Primary Switch for 12V and 24V systems

SOURCE
DRAIN DRAIN D
(FLANGE) SOURCE
GATE
DRAIN
GATE G

TO-220AB DRAIN TO-262AB S

FDP SERIES (FLANGE) FDI SERIES

MOSFET Maximum Ratings TC = 25°C unless otherwise noted

Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 60 V
VGS Gate to Source Voltage ±20 V
Drain Current
Continuous (TC < 151oC, VGS = 10V) 80 A
ID
Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 62oC/W) 17 A
Pulsed Figure 4 A
EAS Single Pulse Avalanche Energy (Note 1) 625 mJ
Power dissipation 310 W
PD
Derate above 25oC 2.07 W/oC
TJ, TSTG Operating and Storage Temperature -55 to 175 oC

Thermal Characteristics
o
RθJC Thermal Resistance Junction to Case TO-220, TO-262 0.48 C/W
o
RθJA Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2) 62 C/W

This product has been designed to meet the extreme test conditions and environment demanded by the automotive
industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality
systems certification.

©2005 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. B

 FDP038AN06A0 / FDI038AN06A0
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDP038AN06A0 FDP038AN06A0 TO-220AB Tube N/A 50 units
FDI038AN06A0 FDI038AN06A0 TO-262AB Tube N/A 50 units

Electrical Characteristics TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 60 - - V
VDS = 50V - - 1
IDSS Zero Gate Voltage Drain Current µA
VGS = 0V TC = 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 2 - 4 V
ID = 80A, VGS = 10V - 0.0035 0.0038
ID = 40A, VGS = 6V - 0.0049 0.0074
rDS(ON) Drain to Source On Resistance Ω
ID = 80A, VGS = 10V,
- 0.0071 0.0078
TJ = 175oC

Dynamic Characteristics
CISS Input Capacitance - 6400 - pF
VDS = 25V, VGS = 0V,
COSS Output Capacitance - 1123 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 367 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V 96 124 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 2V VDD = 30V - 12 15 nC
Qgs Gate to Source Gate Charge ID = 80A - 26 - nC
Qgs2 Gate Charge Threshold to Plateau Ig = 1.0mA - 15 - nC
Qgd Gate to Drain “Miller” Charge - 27 - nC

Switching Characteristics (VGS = 10V)

tON Turn-On Time - - 175 ns
td(ON) Turn-On Delay Time - 17 - ns
tr Rise Time VDD = 30V, ID = 80A - 144 - ns
td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 2.4Ω - 34 - ns
tf Fall Time - 60 - ns
tOFF Turn-Off Time - - 115 ns

Drain-Source Diode Characteristics

ISD = 80A - - 1.25 V
VSD Source to Drain Diode Voltage
ISD = 40A - - 1.0 V
trr Reverse Recovery Time ISD = 75A, dISD/dt = 100A/µs - - 38 ns
QRR Reverse Recovered Charge ISD = 75A, dISD/dt = 100A/µs - - 39 nC
Notes:
1: Starting TJ = 25°C, L = 0.255mH, IAS = 70A.
2: Pulse Width = 100s

©2005 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. B

 FDP038AN06A0 / FDI038AN06A0
Typical Characteristics TC = 25°C unless otherwise noted
1.2
250

1.0 CURRENT LIMITED

POWER DISSIPATION MULTIPLIER

BY PACKAGE
200

ID, DRAIN CURRENT (A)

0.8
150
0.6

100
0.4

0.2 50

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175

TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs

Ambient Temperature Case Temperature

2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
THERMAL IMPEDANCE

0.02
ZθJC, NORMALIZED

0.01
PDM
0.1

t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
SINGLE PULSE PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

3000
TC = 25oC
TRANSCONDUCTANCE
MAY LIMIT CURRENT FOR TEMPERATURES
1000 IN THIS REGION ABOVE 25oC DERATE PEAK
IDM, PEAK CURRENT (A)

CURRENT AS FOLLOWS:

I = I25 175 - TC

VGS = 10V 150

100

10
10-5 10-4 10-3 10-2 10-1 100 101
t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

©2005 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. B

 FDP038AN06A0 / FDI038AN06A0
Typical Characteristics TC = 25°C unless otherwise noted

2000 100
10µs
1000
STARTING TJ = 25oC

IAS, AVALANCHE CURRENT (A)

100µs
ID, DRAIN CURRENT (A)

100
1ms
STARTING TJ = 150oC
OPERATION IN THIS
AREA MAY BE 10
10 LIMITED BY rDS(ON)

10ms
1 DC If R = 0
SINGLE PULSE tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
TJ = MAX RATED If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
TC = 25oC
0.1 1
1 10 100 0.01 0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)

Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability

160 160
PULSE DURATION = 80µs VGS = 20V VGS = 10V
DUTY CYCLE = 0.5% MAX
VDD = 15V
ID , DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)

120 120
VGS = 6V
VGS = 5V

80 TJ = 175oC 80

TJ = 25oC
40 40

TJ = -55oC PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX TC = 25oC
0 0
3.0 3.5 4.0 4.5 5.0 5.5 6 0 0.5 1.0 1.5
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

6 2.5
PULSE DURATION = 80µs PULSE DURATION = 80µs
DRAIN TO SOURCE ON RESISTANCE(mΩ)

DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX

NORMALIZED DRAIN TO SOURCE

VGS = 6V
2.0
ON RESISTANCE

1.5

1.0

VGS = 10V
VGS = 10V, ID =80A
3
0.5
0 20 40 60 80 -80 -40 0 40 80 120 160 200
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (oC)

Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On
Current Resistance vs Junction Temperature

©2005 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. B

 FDP038AN06A0 / FDI038AN06A0
Typical Characteristics TC = 25°C unless otherwise noted

1.4 1.2
VGS = VDS, ID = 250µA ID = 250µA

NORMALIZED DRAIN TO SOURCE

1.2

BREAKDOWN VOLTAGE
THRESHOLD VOLTAGE
NORMALIZED GATE

1.0 1.1

0.8

0.6
1.0

0.4

0.2
0.9
-80 -40 0 40 80 120 160 200
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)

Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature

10000 10
VDD = 30V
VGS , GATE TO SOURCE VOLTAGE (V)

CISS = CGS + CGD 8

COSS ≅ CDS + CGD
C, CAPACITANCE (pF)

1000 CRSS = CGD

4

WAVEFORMS IN
2 DESCENDING ORDER:
ID = 80A
ID = 40A
VGS = 0V, f = 1MHz
100 0
0.1 1 10 60 0 25 50 75 100
VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)

Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant
Voltage Gate Current

©2005 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. B

 FDP038AN06A0 / FDI038AN06A0
Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+
VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0.01Ω 0

tAV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

VDS
VDD Qg(TOT)

L VDS
VGS
VGS = 10V
VGS
+

VDD Qgs2
-

DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs Qgd

Ig(REF)
0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

VDS tON tOFF

td(ON) td(OFF)

RL tr tf
VDS
90% 90%

+
VGS
VDD
10% 10%
- 0

DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2005 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. B

 FDP038AN06A0 / FDI038AN06A0
PSPICE Electrical Model
.SUBCKT FDP038AN06A0 2 1 3 ; rev July 04, 2002
Ca 12 8 1.5e-9
Cb 15 14 1.5e-9 LDRAIN
Cin 6 8 6.1e-9 DPLCAP 5 DRAIN
2
10
Dbody 7 5 DbodyMOD RLDRAIN
RSLC1
Dbreak 5 11 DbreakMOD 51 DBREAK
Dplcap 10 5 DplcapMOD RSLC2
+
5
51 ESLC 11
Ebreak 11 7 17 18 69.3 -
Eds 14 8 5 8 1 50 +
-
Egs 13 8 6 8 1 RDRAIN 17 DBODY
6 EBREAK 18
Esg 6 10 6 8 1 ESG 8
EVTHRES -
Evthres 6 21 19 8 1 + 16
+ 19 - 21
Evtemp 20 6 18 22 1 LGATE EVTEMP MWEAK
8
GATE RGATE + 18 - 6
It 8 17 1 1 22 MMED
9 20
RLGATE MSTRO
Lgate 1 9 4.81e-9 LSOURCE
CIN SOURCE
Ldrain 2 5 1.0e-9 8 7 3
Lsource 3 7 4.63e-9
RSOURCE
RLSOURCE
RLgate 1 9 48.1 S1A S2A
RLdrain 2 5 10 12 RBREAK
13 14 15
17 18
RLsource 3 7 46.3 8 13
S1B S2B RVTEMP
Mmed 16 6 8 8 MmedMOD 13 CB 19
Mstro 16 6 8 8 MstroMOD CA
14 IT -
+ +
Mweak 16 21 8 8 MweakMOD VBAT
EGS 6 EDS 5
8 8 +
Rbreak 17 18 RbreakMOD 1 - - 8
Rdrain 50 16 RdrainMOD 1e-4 22
Rgate 9 20 1.36 RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2.8e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))}

.MODEL DbodyMOD D (IS=2.4E-11 N=1.04 RS=1.65e-3 TRS1=2.7e-3 TRS2=2e-7

+ CJO=4.35e-9 M=5.4e-1 TT=1e-9 XTI=3.9)
.MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.7e-9 IS=1e-30 N=10 M=0.47)

.MODEL MmedMOD NMOS (VTO=3.3 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.36 T_abs=25)
.MODEL MstroMOD NMOS (VTO=4.00 KP=275 IS=1e-30 N=10 TOX=1 L=1u W=1u T_abs=25)
.MODEL MweakMOD NMOS (VTO=2.72 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13.6 RS=0.1 T_abs=25)

.MODEL RbreakMOD RES (TC1=9e-4 TC2=-9e-7)

.MODEL RdrainMOD RES (TC1=4e-2 TC2=3e-4)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-5)
.MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-6.7e-3 TC2=-1.5e-5)
.MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1)
.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2005 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. B

 FDP038AN06A0 / FDI038AN06A0
SABER Electrical Model
rev July 4, 2002
template FDP038AN06A0 n2,n1,n3 = m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=2.4e-11,nl=1.04,rs=1.65e-3,trs1=2.7e-3,trs2=2e-7,cjo=4.35e-9,m=5.4e-1,tt=1e-9,xti=3.9)
dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.7e-9,isl=10e-30,nl=10,m=0.47)
m..model mmedmod = (type=_n,vto=3.3,kp=9,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.00,kp=275,is=1e-30, tox=1)
LDRAIN
m..model mweakmod = (type=_n,vto=2.72,kp=0.03,is=1e-30, tox=1,rs=0.1) DPLCAP 5 DRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-1.5) 2
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-4) 10
RLDRAIN
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5) RSLC1
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1) 51
RSLC2
c.ca n12 n8 = 1.5e-9
c.cb n15 n14 = 1.5e-9 ISCL
c.cin n6 n8 = 6.1e-9 50 DBREAK
-
6 RDRAIN
dp.dbody n7 n5 = model=dbodymod ESG 11
8 DBODY
dp.dbreak n5 n11 = model=dbreakmod + EVTHRES 16
dp.dplcap n10 n5 = model=dplcapmod + 19 - 21
LGATE EVTEMP MWEAK
8
GATE RGATE + 18 - 6
spe.ebreak n11 n7 n17 n18 = 69.3 1 MMED EBREAK
9 22 +
spe.eds n14 n8 n5 n8 = 1 20
RLGATE MSTRO 17
spe.egs n13 n8 n6 n8 = 1 18 LSOURCE
spe.esg n6 n10 n6 n8 = 1 CIN - SOURCE
8 7
spe.evthres n6 n21 n19 n8 = 1 3
spe.evtemp n20 n6 n18 n22 = 1 RSOURCE
RLSOURCE
S1A S2A
i.it n8 n17 = 1 12 RBREAK
13 14 15
17 18
8 13
l.lgate n1 n9 = 4.81e-9
l.ldrain n2 n5 = 1.0e-9 S1B S2B RVTEMP
l.lsource n3 n7 = 4.63e-9 13 CB 19
CA
14 IT -
+ +
res.rlgate n1 n9 = 48.1 6 5 VBAT
EGS 8 EDS 8 +
res.rldrain n2 n5 = 10
- - 8
res.rlsource n3 n7 = 46.3 22
RVTHRES
m.mmed n16 n6 n8 n8 = model=mmedmod, temp=m_temp, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, temp=m_temp, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, temp=m_temp, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-9e-7

res.rdrain n50 n16 = 1e-4, tc1=4e-2,tc2=3e-4
res.rgate n9 n20 = 1.36
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.8e-3, tc1=5e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-6.7e-3,tc2=-1.5e-5
res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10))
}

©2005 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. B

 FDP038AN06A0 / FDI038AN06A0
PSPICE Thermal Model
REV 23 July 4, 2002 th JUNCTION

FDP038AN06A0T

CTHERM1 TH 6 6.45e-3
CTHERM2 6 5 3e-2
CTHERM3 5 4 1.4e-2
CTHERM4 4 3 1.65e-2 RTHERM1 CTHERM1
CTHERM5 3 2 4.85e-2
CTHERM6 2 TL 1e-1
6
RTHERM1 TH 6 3.24e-3
RTHERM2 6 5 8.08e-3
RTHERM3 5 4 2.28e-2
RTHERM4 4 3 1e-1 RTHERM2 CTHERM2
RTHERM5 3 2 1.1e-1
RTHERM6 2 TL 1.4e-1
5

SABER Thermal Model

RTHERM3 CTHERM3
SABER thermal model FDP035AN06A0T
template thermal_model th tl
thermal_c th, tl
{ 4
ctherm.ctherm1 th 6 =6.45e-3
ctherm.ctherm2 6 5 =3e-2
ctherm.ctherm3 5 4 =1.4e-2
ctherm.ctherm4 4 3 =1.65e-2 RTHERM4 CTHERM4
ctherm.ctherm5 3 2 =4.85e-2
ctherm.ctherm6 2 tl =1e-1
3
rtherm.rtherm1 th 6 =3.24e-3
rtherm.rtherm2 6 5 =8.08e-3
rtherm.rtherm3 5 4 =2.28e-2
rtherm.rtherm4 4 3 =1e-1 RTHERM5 CTHERM5
rtherm.rtherm5 3 2 =1.1e-1
rtherm.rtherm6 2 tl=1.4e-1
}
2

RTHERM6 CTHERM6

tl CASE

©2005 Fairchild Semiconductor Corporation FDP038AN06A0 / FDI038AN06A0 Rev. B

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PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. I15