Ex.

No:1A) DESIGN AND ANALYSIS OF CURRENT SERIES FEEDBACK AMPLIFIER

AIM:

To design and test the Current series and voltage shunt Feedback Amplifier and to
calculate the following parameters with and without feedback.
1. Mid band gain.
2. Bandwidth and Cutoff frequencies.
3. Input and output impedance.

APPARATUS REQUIRED:

S.NO ITEM RANGE Q.TY

1 TRANSISTOR BC 107 1
2 RESISTOR 58kΩ, 10kΩ, 1.5kΩ Each 1
RESISTOR 4.7kΩ 2
3 CAPACITOR 1µf, 5µf, 22µf Each 1
4 CRO 1
5 RPS (0-30) V 1
FUNCTION
6 GENERATOR (0 – 20)MHZ 1

THEORY:

An amplifier whose function fraction of output is fed back to the input is called feed
back amplifier. Depending upon whether the input is in phase or out of phase with the feed
back signal, they are classified in to positive feed back and negative feed back. If the feed
back signal is in phase with the input, then the wave will have positive gain. Then the
amplifier is said to have a positive feed back.

If the feed back signal is out of phase with the input ,then the wave will have a negative
gain. The amplifier is said to have a negative feed back. The values of voltage gain and
bandwidth without feed back.
The Current Series Feedback Amplifier is characterized by having Shunt Sampling and
series mixing . In amplifiers there is a network which samples the output and gives to the
feedback network, the feedback signal is mixed with input signal by either shunt or series
mixing technique. Due to Shunt sampling the output resistance increases by a factor of ‘D’
and the input resistance is also increased by the same factor due to series mixing. This is
basically transconductance amplifier. Its input is Voltage which is Amplified as Current

1
PROCEDURE:

 The connections are made as shown in the circuit.

 The amplifier is checked for its correct operation.
 Set the input voltage to a fixed value. Keeping the input voltage Vary the input
frequency from 0Hz to 1MHz and note down the corresponding output voltage. plot
the graph : gain (dB) vs frequency .
 Find the input and output impedances.
 Calculate the bandwidth from the graph.
Remove RE and follow the same procedure.
CIRCUIT DIAGRAM:

A) Current Series with Feedback

B) Current Series without Feedback

2
MODEL GRAPH:

DESIGN:
i) (Without Feedback ):

Vcc = 12V ,fL = 50Hz, Ic=1mA, S=2, RL = 4.7K, hfe = re = 26mV/ Ic =26 Ω
Vcc Vcc
hie= hfe re = Vce = 2 (transistor active) = VE = IE RE = 10
Applying KVL to the output loop, we get
Vcc= IC RC + V CE + IE RE
Rc = 1.66 kΩ
Since IB is very small when compare with Ic
Ic≈ IE
VE
R = I E = 1.2k
E
RB
S= 1+ R E = 2
RB = 1.4
V CC∗R 2
V = ( R1 + R 2 )
B

RB= R1 ||R2 , R1 = 1.62 kΩ, R2 = 10.30 kΩ

Zi hfe||R E
Xci = 10 = 10 = 1.735
1
Ci= (2 πf ∗Xci) = 12.804 × 10-3
R L||R L
Xco = 10 = 1.226

3
 1
Co = (2 πf ∗Xco ) = 2.596 × 10-3
RE
XCE = 10 = 0.12
1
Ce = (2 πf ∗X CE ) = 0.026

ii) With Feedback (Remove the Emitter Capacitor, CE)

Feedback Factor, β = - RE = -1.2
−hfe
Gm = ( hie + R E ) = -4.332 × 10-3
Desensitivity Factor, D = 1+ β Gm = 1.008
Gm
Transconductance with Feedback, Gmf = D = -4.310 × 10-3
Input impedance with Feedback, Zif = ZiD = 1.129
Output impedance with Feedback, Zof = Zo.D

TABULATION: (Without Feedback) Vin =

Output
Frequency Voltage (Vo) Gain = V0/ Vin Gain = 20 log (Vo/ Vin)
S.No (Hz) Volts dB

4
5
TABULATION : (With Feedback) Vin =

Output
S.No Frequency (Hz) Voltage (Vo) Gain = V0/ Vin Gain = 20 log (Vo/ Vin)
Volts dB

RESULT:

Thus the Current Series Feedback Amplifier is designed and constructed.

6
 Ex.No:1B) DESIGN AND ANALYSIS OF VOLTAGE SHUNT FEEDBACK
AMPLIFIER

AIM:

To design and test the current series and voltage shunt Feedback Amplifier and to
calculate the following parameters with and without feedback.
1. Mid band gain.
2. Bandwidth and cutoff frequencies.
3. Input and output impedance.

APPARATUS REQUIRED:

S.NO ITEM RANGE Q.TY

1 TRANSISTOR BC 107 1
2 RESISTOR 58kΩ, 68kΩ, 10kΩ, 1.5kΩ Each 1
RESISTOR 4.7kΩ 2
3 CAPACITOR 5uf , 0.2uf, 1f 1

4 CRO 1
5 RPS (0-30) V 1
6 FUNCTION (0 – 20)MHZ 1
GENERATOR

THEORY:

In Voltage Shunt Feedback Amplifier, the feedback Signal voltage is given to the
base of the transistor in shunt through the base resistor Rb. This Shunt Connection tends
to decrease the input resistance and the voltage Feedback tends to decrease the Output
resistance. In the Circuit Rb Appears directly across the input back terminal and Output
Collector terminal.
A Part of Output is feedback to the input through Rb and increases in Ic decreases
Ib. Thus Negative Feedback exists in Circuit. So this circuit is also called Voltage
Feedback Bias Circuit. This feedback Amplifier is known as transresistance Amplifier. It
amplifies the input Current to required voltage levels. The feedback path consists of a
resistor and a Capacitor

PROCEDURE:

7
  The connections are made as shown in the circuit.
 The amplifier is checked for its correct operation.
 Set the input voltage to a fixed value. Keeping the input voltage Vary the input
frequency from 0Hz to 1MHz and note down the corresponding output voltage.
plot the graph : gain (dB) vs frequency .
 Find the input and output impedances.
 Calculate the bandwidth from the graph.
 Remove RE and follow the same procedure.
CIRCUIT DIAGRAM:

A) Voltage Shunt Without Feedback

B) Voltage Shunt with Feedback

8
MODEL GRAPH:

TABULATION: (without Feedback) Vin =

Output
Frequency (Hz) Voltage (Vo) Gain = V0/ Vin Gain = 20 log (Vo/ Vin)
S.No Volts dB

TABULATION: (with Feedback)

9
 Vin =

Output
Frequency Voltage (Vo) Gain = V0/ Vin Gain = 20 log (Vo/ Vin)
S.No (Hz) Volts dB

RESULT:

Thus the Current Series Feedback Amplifier is designed and Constructed.

10
Ex.No:2A) DESIGN AND ANALYSIS OF RC PHASE SHIFT OSCILLATOR

AIM:
To design and construct the transistor Phase shift oscillator.

APPARATUS REQUIRED:

S.NO ITEM RANGE Q.TY

1 TRANSISTOR BC 107 1
2 RESISTOR 4.7kΩ, 58kΩ, 1.5kΩ, 10kΩ 2,1,1,4
3 CAPACITOR 0.01u µf, 1 µf, 5 µf 3,1,1
4 CRO ( 0 – 30 ) MHz 1
5 RPS (0-30) V 1
6 FUNCTION (0-20 )MHz 1
GENERATOR

THEORY:

The Transistor Phase Shift Oscillator produces a sine wave of desired designed
frequency. The RC combination will give a 60 0 phase shift totally three combination will
give a 1800 phase shift. . The BC107 is in the common emitter configuration. Therefore
that will give a 1800 phase shift totally a 3600 phase shift output is produced. The
capacitor value is designed in order to get the desired output frequency. Initially the C
and R are connected as a feedback with respect to input and output and this will maintain
constant sine wave output. CRO is connected at the output.

PROCEDURE:
1. The circuit is constructed as per the given circuit diagram.
2. Switch on the power supply and observe the output on the CRO( sine wave)

Note down the practical frequency and compare it with the theoretical frequency.

11
 CIRCUIT DIAGRAM:

MODEL GRAPH:

12
TABULATION:

Theoretical Practical
Amplitude (V) Time Period (ms)
Frequency Frequency

RESULT :

Thus the RC Phase shift Oscillator is designed and constructed and the Output sine wave
frequency.

13
Ex.No: 2B) DESIGN AND ANALYSIS OF WEIN BRIDGE OSCILLATOR

Aim :
To Design and construct a Wein – Bridge Oscillator for a given cut-off frequency .

APPARATUS REQUIRED:

S.NO ITEM RANGE Q.TY

1 TRANSISTOR BC107 2
47kΩ, 2.2kΩ, 4.7kΩ, 10kΩ, 1kΩ,
2 RESISTOR 560Ω 2,2,1,2,1,1
3 CAPACITOR 10 µf, 1 µf, .60 µf Each1

4 CRO - 1
5 RPS DUAL(0-30) V 1

THEORY:
In wein bridge oscillator, wein bridge circuit is connected between the amplifier
input terminals and output terminals. The bridge has a series rc network in one arm and
parallel network in the adjoining arm. In the remaining 2 arms of the bridge resistors
R1and Rf are connected . To maintain oscillations total phase shift around the circuit must
be zero and loop gain unity. First condition occurs only when the bridge is balanced .
Assuming that the resistors and capacitors are equal in value, the resonant frequency of
balanced bridge is given by

F0 = 0.159 RC
PROCEDURE:

1. The circuit is constructed as per the given circuit diagram.

2. Switch on the power supply and observe the output on the CRO( sine wave)
3. Note down the practical frequency and compare it with the theoretical
frequency.

14
CIRCUIT DIAGRAM:

VCC
12V

R1 R3 R6 R8
47kΩ 2.2kΩ 47kΩ 2.2kΩ C4
C1
C2
10µF
Q1 10µF Q2 .1µF
R5

R4 C3
BC107BP BC107BP 1kΩ
.01µF
50 %
Key=A
R7
R2 4.7kΩ R9
50 % 10kΩ
10kΩ Key=A 560Ω

R11

10kΩ
Key=A 50 %

MODEL GRAPH:

15
TABULATION:

Theoretical Practical
Amplitude (V) Time Period (ms) Frequency Frequency

RESULT :

Thus a Wien Bridge oscillator is designed and the Output Waveform is drawn

16
 Ex.No:3A) DESIGN AND ANALYSIS OF HARTLEY OSCILLATOR

AIM :

To Design and construct the given Oscillator at the given operating

frequency.

APPARATUS REQUIRED:

S.NO ITEM RANGE Q.TY

1 TRANSISTOR BC 107 1
2 RESISTOR 56 kΩ,6 kΩ, 10 kΩ, 1.5 kΩ,1 kΩ Each1

3 CAPACITOR 5 µf, 1 µf, 22 µf, 0.01 µf Each1

4 CRO (0 – 30)MHZ 1
5 RPS (0-30) V 1

6 FUNCTION (0- 1 ) MHz 1

GENERATOR
7 DlB, DRB 1

THEORY:

LC oscillator consisting of a tank circuit for generating sine wave of required

frequency. Rectifying Barkhausen criteria A for a circuit containing reactance A
must be positive and greater than or equal to unity.

PROCEDURE :

 The circuit connection is made as per the circuit diagram.

 Switch on the power supply and observe the output on the CRO
(sine wave ).
 Note down the practical frequency and compare it with the theoretical
frequency.

17
THEORETICAL FREQUENCY FOR HARTLEY OSCILLATOR:
1
f C = 2 π |(L1 + L2 )C
CIRCUIT DIAGRAM :

MODEL GRAPH:

TABULATION:

Theoretical Practical
Amplitude (V) Time Period (ms)
Frequency Frequency

RESULT:
Thus the Hartley Oscillator is designed for the given frequency and the
output response is verified.

18
 Ex.No: 3B) DESIGN AND ANALYSIS OF COLPITTS OSCILLATOR

AIM :

To Design and construct the given Oscillator at the given operating

frequency.

APPARATUS REQUIRED:

S.NO ITEM RANGE Q.TY

1 TRANSISTOR BC 107 1
2 RESISTOR 10k,15k,6k,58k 1

3 CAPACITOR 1uf, 5uf, 22uf, 0.1uf,300uf 1

4 CRO (0 – 30)MHZ 1
5 RPS (0-30) V 1

6 FUNCTION (0- 1 ) MHz 1

GENERATOR
7 DlB, DRB 1

THEORY:

Colpitt’s oscillator is very popular and is commonly used as local oscillator in radio receivers.
The collector voltage is applied to the collector through inductor L whose reactance is high
compared with X2 and may therefore be omitted from equivalent circuit, at zero frequency; The
circuit operates as Class C. the tuned circuit determines basically the frequency of oscillation.

PROCEDURE :

 The circuit connection is made as per the circuit diagram.

 Switch on the power supply and observe the output on the CRO (sine wave).
 Note down the practical frequency and compare it with the theoretical
frequency.

19
THEORETICAL FREQUENCY FOR COLPITT OSCILLATOR:

fC √
1 ( C1 + C2 )
= 2 π LC 1 C 2

TABULATION:

Theoretical Practical
Amplitude (V) Time Period (ms) Frequency Frequency

CIRCUIT DIAGRAM:

20
MODEL GRAPH:

RESULT :

Thus the Colpitts oscillator is designed for the given frequency and the output
response is verified.

21
 IC 741 - General Description
The IC 741 is a high performance monolithic operational amplifier
constructed using the planar epitaxial process. High common mode voltage range and
absence of latch-up tendencies make the IC 741 ideal for use as voltage follower. The
high gain and wide range of operating voltage provides superior performance in
integrator, summing amplifier and general feedback applications.
Pin Configuration:

Block Diagram of Op-Amp:

APPLICATIONS:-
1. AC and DC amplifiers.
2. Active filters.
3. Oscillators.
4. Comparators.
5. Regulators., etc.,

22
FEATURES:
1. No frequency compensation required.
2. Short circuit protection
3. Offset voltage null capability
4. Large common mode and differential voltage ranges
5. Low power consumption
6. No latch-up

SPECIFICATIONS:-

1. Voltage gain A = ∞ typically 2,00,000

2. Input resistance RL = ∞ Ω, practically 2MΩ
3. Output resistance R =0, practically 75Ω
4. Bandwidth = ∞ Hz. It can be operated at any frequency
5. Common mode rejection ratio (Ability of op amp to reject noise voltage)
6. Slew rate + ∞ V/μsec
(Rate of change of O/P voltage with respect to applied I/P)
7. When V1 = V2, VD=0
8. Input offset voltage (Rs ≤ 10KΩ) max 6 mv
9. Input offset current = max 200nA
10. Input bias current : 500nA
11. Input capacitance : typical value 1.4pF
12. Offset voltage adjustment range : ± 15mV
13. Input voltage range : ± 13V
14. Supply voltage rejection ratio : 150 μV/V
15. Output voltage swing: + 13V and – 13V for RL > 2KΩ
16. Output short-circuit current: 25mA
17. supply current: 28mA
18. Power consumption: 85mW
19. Transient response: rise time= 0.3 μs

23
Ex.No: 4 INTEGRATOR AND DIFFERENTIATOR USING OP-AMP

AIM:
To design an Integrator and Differentiator using op-amp IC 741 and to test
their characteristics & Performance.

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 --- 01
100 Ω, 1KΩ Each 02
2. RESISTORS
10KΩ Each 01

3. CAPACITOR
0.1μf, 0.01μf Each 01
4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

PROCEDURE:
 From the given frequency fa & fb, the values of Rf, Cf, R1 & Rcomp are calculated as
given in the design procedure.
 Connect the circuit as shown in the circuit diagram.
 Apply the sinusoidal input as the constant amplitude to the inverting terminal of op-amp.
 Gradually increase the frequency & observe the output amplitude.
 Calculate the gain with respect to frequency & plot its graph.

24
INTEGRATOR:-

CIRCUIT DIAGRAM:-
Rf = 10K

R1 = 1k Cf = 0.01F

+12V
7
Vin
2 -
6
3 A741
+
IC 741

Rcomp = Rf=1K 4 Vout

-12V

TABULATION:

Input Output

Amplitude

Time Period

MODEL GRAPH:
Model graph
Vin

t
t

Vo

t
t

25
DIFFERENTIATOR:-

CIRCUIT DIAGRAM:

0.01µf

R1=100ΩC1=0.1µf
Rf

+12V
7
Vin
2 -
6 Vo = -Rf C1[dVin/dt]
3 +
IC 741

Rcomp=1kΩ 4 RL
-12V

0
TABULATION:

Input Output

Amplitude

Time period

MODEL GRAPH:

(i) FOR SINE WAVE INPUT (ii) FOR SQUARE WAVE INPUT

Model graph Model graph

Vin
Vin
IV
IV

t
t

-IV

-IV

Vo
Vo
2V

-2V

26
27
RESULT

Thus an Integrator and Differentiator using op-amp are designed and their performance
was successfully tested using op-amp IC 741.

28
 EXP.NO: 5 DESIGN & ANALYSIS OF WAVESHAPING CLIPPER AND CLAMPER
CIRCUITS

AIM :
To observe the clipping waveform in different clipping configurations.

APPARATUS REQUIRED:

S.NO ITEM RANGE Q.TY

1 DIODE IN4007 1
2 RESISTOR 1K, 10k 1

3 CAPACITOR 0.1µF 1

4 FUNCTION GENERATOR (0-1) MHz 1

5 CRO - 1

THEORY:
CLIPPER:
A Clipper is a circuit that removes either the positive or negative part of a waveform. For a positive
clipper only the negative half cycle will appear as output.

Procedure:
1. Connections are given as per the circuit .
2. Set input signal voltage (5v,1kHz ) using function generator.
3. Observe the output waveform using CRO.
4. Sketch the observed waveform on the graph sheet.

29
CIRCUIT DIAGRAM

NEGATIVE CLIPPER

MODEL GRAPH

NEGATIVE CLIPPER

Input OUTPUT
Amp(V) Time(ms) Amp(V) Time(ms)

30
POSITIVE CLIPPER
CIRCUIT DIAGRAM

Input OUTPUT

Amp(V) Time(ms) Amp(V) Time(ms)

31
CLAMPER
CIRCUIT DIAGRAM

Model Graph

32
 Input OUTPUT
Amp(V) Time(ms) Amp(V) Time(ms)

Result :
Thus the waveforms are observed and traced for clipper and clamper circuits.

33
EXP.NO: 6 INSTRUMENTATION AMPLIFIER

AIM:
To construct and test the CMRR (Common Mode Rejection Ratio) of a 3 op-amp
Instrumentation amplifier using op-amp IC741.

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 03
1KΩ., 10KΩ 06
2. RESISTORS
22KΩ 01
3. DIGITAL TRAINER KIT --- 01
4. SIGNAL GENERATOR (0-3)MHz 02
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW

PROCEDURE:

1. Select the entire resistor with same value of resistance R. Let RG be the gain varying
resistor with different values of resistance. For simplicity, let RG be a constant
value.
2. Connect the circuit as shown in the circuit diagram.
3. Give the input V1 & V2 to the non-inverting terminals of first & second
Op-amp respectively.

4. By varying the value of RG, measure the output voltage for common mode and
differential mode operation. Since RG is selected as constant value, provide
different input value of V1 & V2.
5. Calculate the differential mode gain Ad and common mode gain Ac to calculate the

CMRR=20 log Ad
Ac
CMRR as

34
CIRCUIT DIAGRAM:

+12v

3 7
+ Rf=10K Ω
IC
-
741
4
6
+12v
2
-12v R2=10K Ω

R1=1K Ω 2 - 7
IC 741
6
RG=22K Ω 3 + 4
+ R1=1K Ω
12V
1 -12v
R2=10K Ω
- +

+12v R1=10K Ω V
-
2 - 7
IC 741
6
+ 3 + 4
12V
-12v
-

TABULATION:

COMMON MODE GAIN CALCULATION - AC

V
RG V1 V2 Vo Ac = o

S.No V V
(KΩ) (Volts) (Volts) (Volts) 1 2
2

1.

2.

3.

4.

5.

35
 DIFFERENTIAL MODE GAIN - AD & CMRR CALCULATION.

V1 V2 Vo
Ad =
S.NoRG (K Ω)(Volts) (Volts) (Volts)
1.
2.

3.

4.
5.

RESULT:
Thus a 3 op-amp instrumentation amplifier was constructed and CMRR is
tested using op-amp IC 741.

23
 EXP.NO: 7 ACTIVE LOW PASS, HIGH PASS AND BAND PASS
FILTER USING OP-AMP
AIM:
To design an Active Low Pass, High Pass and Band Pass Filter using op-amp and to test
their performance

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 --- 02
1.5 KΩ,5.6KΩ,1 K Ω 02
2. RESISTORS 10KΩ 03
22KΩ 04
3. CAPACITORS 0.1μf 02
4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

DESIGN PROCEDURE: (ACTIVE HPF):

Design a HPF at cutoff frequency fL of 1KHZ & P.B gain of 2. Follow the same procedure
as LPF & interchange the R & C position with capacitor first & resistor in parallel to capacitor
where the other end connected to ground.
In high pass filter Theoretical gain is given as Vo = Af ( f / f L )
Vin
1(f/ H )2
PROCEDURE - (LPF & HPF):
1. Connect the circuit as shown in the circuit diagram.
2. Select the corresponding cut-off frequency (higher or lower) and determine the
value of C & R. select the value of R1 & Rf depending on desired passband gain Af..
3. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of
op- amp.
4. Tabulate the output voltage Vo with respect to different values of input frequency.
5. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.

24
 LOWPASS FILTER:-
CIRCUIT DIAGRAM:-
R1=10K Ω Rf=5.6K Ω

+12v
2 - 7
Signal Generator IC 741
+ 1.5K Ω + 6
3 4
Vin~ RL=10K Ω
+ CRO
-
0.1uf -12v

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

25
MODEL GRAPH:

CIRCUIT DIAGRAM - (HIGH PASS FILTER):-

R1=1K Ω Rf=10K Ω

+12v

2 - 7
Signal Generator
0.1μf IC 741
4 6
3 + + CRO
+
Vin ~ 1.5K Ω -12v
RL=10K Ω -

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No (Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

26
MODEL GRAPH:

CIRCUIT DIAGRAM: (BANDPASS FILTER)

R1=1K Ω Rf=10K Ω
R1=1K Ω Rf=10K
Ω
+12v

+12v
2 - 7
2 - 7
IC 741
Signal C=0.1uf 6
Generator
IC 741
3 + 4
6 R=10K Ω
+ 3 + 4 +
CRO
Vin ~ R=10K
-12v
C=0.01uf -12v
RL=10K Ω -
- Ω

First Order High Pass Filter First Order Low Pass Filter

TABULATION:

Frequency Output Voltage Gain = 20 log (V0 /Vin)

S.No (Hz) (Volts) (dB)
1
2
3
4
5
6
7
8

27
 MODEL GRAPH:

PROCEDURE:
1. Select the lower

2. and higher cut-off frequency and calculate the value of R & C for the given
frequencies.
3. Design for LPF & HPF separately and then combine the circuit by first placing
the HPF followed by a LPF (i.e.) HPF in series with LPF.
4. Connect the circuit as shown in the circuit diagram.
5. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of op-amp.
6. Tabulate the output voltage Vo with respect to different values of input frequency.
7. Calculate passband gain and plot the graph of frequency versus voltage gain & check
the graph to get approximately the same characteristic as shown in the model graph.

28
29
RESULT:
Thus an Active Lowpass, High pass and Band Pass Filters are designed and tested using
op-amp IC 741.

PLL IC 565
The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE 560, 561,
562, 564, 565, & 567 differ mainly in operating frequency range, power supply requirements and
frequency and bandwidth adjustment ranges. The device is available as 14 Pin DIP package and
as 10-pin metal can package. Phase comparator or phase detector compare the frequency of input
signal fs with frequency of VCO output fo and it generates a signal which is function of
difference between the phase of input signal and phase of feedback signal which is basically a
d.c voltage mixed with high frequency noise. LPF remove high frequency noise voltage. Output
is error voltage. If control voltage of VCO is 0, then frequency is center frequency (f o) and mode
is free running mode. Application of control voltage shifts the output frequency of VCO from f o

30
 to f. On application of error voltage, difference between f s & f tends to decrease and VCO is said
to be locked. While in locked condition, the PLL tracks the changes of frequency of input signal.

Block Diagram of IC 565

PROCEDURE:
1. Determine the component values using the design procedure given here.
2. Connect the components as shown in the circuit diagram.
3. Note down the readings of output waveform with respect to input signal.

31
PIN CONFIGURATION:

SPECIFICATIONS:
1. Operating frequency range : 0.001 Hz to 500 KHz
2. Operating voltage range : ±6 to ±12V
3. Inputs level required for tracking : 10mV rms minimum to 3v (p-p) max.
4. Input impedance : 10 KΩ typically
5. Output sink current : 1mA typically
6. Drift in VCO center frequency : o
300 PPM/ C typically
(fout) with temperature
7. Drif in VCO centre frequency with : 1.5%/V maximum
supply voltage
8. Triangle wave amplitude : typically 2.4 VPP at ± 6V
9. Square wave amplitude : typically 5.4 VPP at ± 6V
10. Output source current : 10mA typically
11. Bandwidth adjustment range : <±1 to >± 60%
Center frequency fout = 1.2/4R1C1 Hz
= free running frequency
FL = ± 8 fout/V Hz
V = (+V) – (-V)
 f
fc =  L 3 /2
±  2(3.6) x10 1
APPLICATIONS: xC2
1. Frequency multiplier
2. Frequency shift keying (FSK) demodulator
3. FM detector

32
 CIRCUIT DIAGRAM

NE 565 PLL CONNECTION DIAGRAM

DESIGN PROCEDURE:-
If C= 0.01μF and the frequency of input trigger signal is 2KHz, output pulse width of 555

in Monostable mode is given by

1.1RAC = 1.2T =1.2/f
RA= 1.2/(1.1Cf)=54.5KΩ
fIN=fOUT/N
Under locked conditions,
fOUT = NfIN = 2fIN = 4KHz

33
 EX.No. 8 PLL CHARACTERISTICS AND ITS USE AS FREQUENCY MULTIPLIER, CLOCK
SYNCHRONIZATION

AIM:

To design & test the characteristics of PLL and to construct and test frequency
multiplier using PLL IC565.

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT VALUE QUANTITY

1 IC 565 --- 01
2 IC 555/I C 7490 --- 01

3 RESISTORS 10KΩ, 4.7 KΩ, 6.8K Each one

0.01μF 4
CAPACITORS
4
0.1 μf, 10μf, 1 μf EACH 01

5 DIGITAL TRAINER KIT --- 01

6 REGULATED POWER SUPPLY (0 -30V), 1A 1

7 CATHODE RAY OSCILLOSCOPE (0 – 30MHz) 1
8 CONNECTING WIRES --- FEW

34
 PLL as Frequency Multiplier

(a) : Input
(b) : PLL output under locked conditions without 555
©: Output at pin4 of 565 with 555 connected in the feedback

35
 THEORY:
The frequency divider is inserted between the VCO and the phase comparator of PLL.
Since the output of the divider is locked to the input frequency fIN, the VCO is actually running
at a multiple of the input frequency .The desired amount of multiplication can be obtained by
selecting a proper divide– by – N network ,where N is an integer. To obtain the output frequency
fOUT=2fIN, N = 2 is chosen. One must determine the input frequency range and then adjust the
free running frequency fOUT of the VCO by means of R 1 and C1 so that the output frequency of
the divider is midway within the predetermined input frequency range. The output of the VCO
now should be 2fIN . The output of the VCO should be adjusted by varying potentiometer R 1. A
small capacitor is connected between pin7 and pin8 to eliminate possible oscillations. Also,
capacitor C2 should be large enough to stabilize the VCO frequency.

PARAMETER INPUT OUTPUT

Amplitude (Vp-p)

Frequency (KHz)

PROCEDURE:-
1. The circuit is connected as per the circuit diagram.
2. Apply a square wave input to the pin2 of the 565
3. Observe the output at pin4 of 565 under locked condition.
4. Give the output of 565 to the pin2 of 555 IC.
5. Observe the output of 555 at pin3.
6. Now give the output of 555 as feedback to the pin5 of the 565.
7. Observe the frequency of output signal fo at pin4 of 565 IC.
8. Plot the waveforms in graph.

RESULT:
Thus the PLL characteristics are designed and tested and Frequency multiplier using IC
565 is constructed and tested.

36
 EXP.NO: 9 R-2R LADDER TYPE D- A CONVERTER USING OP-AMP

AIM:

To design a 4-bit R-2R ladder type DAC using OP-AMP.

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT VALUE QUANTITY

1 IC 741 --- 01
2 RESISTOR 2.2KΩ, 1KΩ 05, 04

3 DIGITAL MULTIMETER METER

4 DIGITAL TRAINER KIT --- 01

5 REGULATED POWER SUPPLY (0 -30V), 1A 1

6 CATHODE RAY OSCILLOSCOPE (0 – 30MHz) 1
7 CONNECTING WIRES --- FEW

THEORY:

In R-2R ladder network only two values of resistors are required. Consider 4 bit
DAC, where switch position d1, d2, d3, d4 corresponding to binary words.

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. The inputs are given through b0,b1,b2,b3.
3. The inputs are given from (0-15)V and observe the outputs in voltmeter.
4. The graph is drawn.

37
CIRCUIT DIAGRAM:

TABULATION:

Equivalent Binary Practical

Decimal Voltage
(V)
b3 b2 b1 b0

38
 DESIGN PROCEDURE:

Vo = -Rf (b3/2R + b2/4R + b1/8R + b0/16R)Vref Rf = R

Vo = -Vref (b3/2 + b2/4 + b1/8 + b0/16) Assume R =10K

2R = 22K

RESULT:

Thus the 4-bit R-2R ladder type DAC is designed

51
Ex.No: 10 SPICE SIMULATION OF TUNED COLLECTOR OSCILLATOR

Aim:
To simulate a Tuned collector oscillator circuit and to plot the frequency
response characteristics.

Apparatus required :

i)Personal Computer
ii) SPICE (PSPICE 9.0 v& above or MULTISIM 10.0 v & above) Software.

Procedure:
i) Draw the circuit diagram after loading components from library.

ii) A DC source with 0 V is place as the dummy voltage source to obtain the current
waveform.

iii) Wiring and proper net assignment has been made. The circuit is preprocessed. The VI
characteristics may be obtained by performing DC transfer function Analysis. Place the
current waveform marker at the positive terminal of the dummy voltage source
(voltage =0 volts).

iii) For placing waveform markers, select tools instruments set wave form cotnent current
waveform click on the required net and place the waveform marker.The sweep parameter
(voltage) for input source is set in the Analysis window.

iv) The applied voltage is swept from an initial value to final value with the steps
provided To get VI characteristics, the currents corresponding to varying input voltages are
noted.

vi) The VI graph is observed in the Waveform Viewer

52
Tuned Collector Oscillator

Result :
Thus the Tuned collector oscillator is simulated successfully.

53
Ex. No: 10 A SPICE SIMULATION OF WEIN BRIDGE OSCILLATOR

Aim:

To simulate a Wein Bridge oscillator circuit and to plot the frequency response
characteristics.

Apparatus required :

i)Personal Computer
ii) SPICE (PSPICE 9.0 v& above or MULTISIM 10.0 v & above) Software.

Procedure:

v) Draw the circuit diagram after loading components from library.

vi) A DC source with 0 V is place as the dummy voltage source to obtain the current
waveform.

iii) Wiring and proper net assignment has been made. The circuit is preprocessed. The VI
characteristics may be obtained by performing DC transfer function Analysis. Place the
current waveform marker at the positive terminal of the dummy voltage source
(voltage =0 volts).

vii) For placing waveform markers, select tools instruments set wave form cotnent current
waveform click on the required net and place the waveform marker.The sweep parameter
(voltage) for input source is set in the Analysis window.

viii) The applied voltage is swept from an initial value to final value with the steps
provided To get VI characteristics, the currents corresponding to varying input voltages are
noted.

vi) The VI graph is observed in the Waveform Viewer

54
Wein Bridge Oscillator

Result :

Thus the Wein Bridge oscillator circuit is simulated successfully.

55
Ex.No:10 B) SPICE SIMULATION OF TWIN T OSCILLATOR

Aim:
To simulate a Twin T oscillator circuit and to plot the frequency response
characteristics.

Apparatus required :
i)Personal Computer
ii) SPICE (PSPICE 9.0 v& above or MULTISIM 10.0 v & above) Software.

Procedure:
ix) Draw the circuit diagram after loading components from library.

x) A DC source with 0 V is place as the dummy voltage source to obtain the current
waveform.

iii) Wiring and proper net assignment has been made. The circuit is preprocessed. The VI
characteristics may be obtained by performing DC transfer function Analysis. Place the
current waveform marker at the positive terminal of the dummy voltage source
(voltage =0 volts).

xi) For placing waveform markers, select tools instruments set wave form cotnent current
waveform click on the required net and place the waveform marker.The sweep parameter
(voltage) for input source is set in the Analysis window.

xii) The applied voltage is swept from an initial value to final value with the steps
provided To get VI characteristics, the currents corresponding to varying input voltages are
noted.

vi) The VI graph is observed in the Waveform Viewer

.

56
Twin T Oscillator

OUTPUT:

Result :

Thus the Twin T oscillator circuit is simulated successfully.

57
Ex.No:11 SPICE SIMULATIONS OF DOUBLE TUNED AMPLIFIERS

Aim:

To simulate a Double Tuned Amplifiers circuit and to plot the frequency response
characteristics.

Apparatus Required :

i) Personal Computer
ii) SPICE (PSPICE 9.0 v& above or MULTISIM 10.0 v & above) Software.

Procedure:
i) Draw the circuit diagram after loading components from library.

ii) A DC source with 0 V is place as the dummy voltage source to obtain the current
waveform.

iii) Wiring and proper net assignment has been made. The circuit is preprocessed. The VI
characteristics may be obtained by performing DC transfer function Analysis. Place the
current waveform marker at the positive terminal of the dummy voltage source
(voltage =0 volts).

iii) For placing waveform markers, select tools instruments set wave form cotnent current
waveform click on the required net and place the waveform marker.The sweep parameter
(voltage) for input source is set in the Analysis window.

iv) The applied voltage is swept from an initial value to final value with the steps
provided To get VI characteristics, the currents corresponding to varying input voltages are
noted.

vi) The VI graph is observed in the Waveform Viewer

58
DOUBLE TUNED AMPLIFIERS

OUTPUT:

Result :

Thus the Double tuned Amplifier were simulated successfully.

59
Ex. No: 12 SPICE SIMULATION OF BISTABLE MULTIVIBRATOR

Aim:
To simulate a Bistable Multivibrator circuit and to plot the frequency response
characteristics.

Apparatus required :

i) Personal Computer
ii) SPICE (PSPICE 9.0 v& above or MULTISIM 10.0 v & above) Software.

Procedure:

i) Draw the circuit diagram after loading components from library.

ii) A DC source with 0 V is place as the dummy voltage source to obtain the current
waveform.

iii) Wiring and proper net assignment has been made. The circuit is preprocessed. The
VI characteristics may be obtained by performing DC transfer function Analysis. Place
the current waveform marker at the positive terminal of the dummy voltage source
(voltage =0 volts).

iv) For placing waveform markers, select tools instruments set wave form content current
waveform click on the required net and place the waveform marker. The sweep parameter
(voltage) for input source is set in the Analysis window.

v) The applied voltage is swept from an initial value to final value with the steps provided
To get VI characteristics, the currents corresponding to varying input voltages are noted.

vi) The VI graph is observed in the Waveform Viewer

Bistable Multivibrator:

60
Result :

Thus the Bistable Multivibrator was simulated successfully.

61
Ex.No:13 SPICE SIMULATION OF SCHMITT TRIGGER

Aim:
To simulate a Schmitt trigger circuit and to plot the frequency response characteristics.

Apparatus required :

i) Personal Computer
ii) SPICE (PSPICE 9.0 v& above or MULTISIM 10.0 v & above) Software.

Procedure:

i) Draw the circuit diagram after loading components from library.

ii) A DC source with 0 V is place as the dummy voltage source to obtain the current
waveform.
iii) Wiring and proper net assignment has been made. The circuit is preprocessed. The VI

characteristics may be obtained by performing DC transfer function Analysis. Place the

current waveform marker at the positive terminal of the dummy voltage source
(voltage =0 volts).

iv) For placing waveform markers, select tools instruments set wave form content current
waveform click on the required net and place the waveform marker. The sweep parameter
(voltage) for input source is set in the Analysis window.

v) The applied voltage is swept from an initial value to final value with the steps provided
To get VI characteristics, the currents corresponding to varying input voltages are noted.

vi) The VI graph is observed in the Waveform Viewer

62
Schmitt Trigger

OUTPUT

Result :

Thus the Schmitt Trigger was simulated successfully.

63
Ex.No: 14A) SPICE SIMULATION OF CLASS A POWER AMPLIFIER
Aim:
To simulate a Class A Power Amplifier Circuit and to plot the output characteristics.

Apparatus required :

i) Personal Computer
ii) SPICE (PSPICE 9.0 v& above or MULTISIM 10.0 v & above) Software.

Theory:
The power amplifier is said to be Class A amplifier if the Q point and the input signal are
selected such that the output signal is obtained for a full input signal cycle.
For all values of input signal, the transistor remains in the active region and never enters into
saturation region. When an a.c signal is applied, the collector voltage varies sinusoidally
hence the collector current also varies sinusoidally. The collector current flows for 360 0 (full
cycle) of the input signal. ie., the angle of the collector current flow is 3600
Procedure:
i) Draw the circuit diagram after loading components from library.
ii) A DC source with 0 V is place as the dummy voltage source to obtain the current
waveform.

iii) Wiring and proper net assignment has been made. The circuit is preprocessed. The
VI characteristics may be obtained by performing DC transfer function Analysis. Place
the current waveform marker at the positive terminal of the dummy voltage source
(voltage =0 volts).

iv) For placing waveform markers, select tools instruments set wave form content current
waveform click on the required net and place the waveform marker. The sweep parameter
(voltage) for input source is set in the Analysis window.

v) The applied voltage is swept from an initial value to final value with the steps provided
To get VI characteristics, the currents corresponding to varying input voltages are noted.

64
Class A Power Amplifier

Result :
Thus the Class A Power Amplifier circuit was simulated successfully.

65
Ex.No: 14B) SPICE SIMULATION OF CLASS B POWER AMPLIFIER
Aim:
To simulate a Class B Power Amplifier circuit and to plot the output characteristics.

Apparatus required :
i) Personal Computer
ii) SPICE (PSPICE 9.0 v& above or MULTISIM 10.0 v & above) Software.

Theory:
A power amplifier is said to be Class B amplifier if the Q-point and the input signal are
selected such that the output signal is obtained only for one half cycle for a full input cycle. The
Q-point is selected on the X-axis. Hence, the transistor remains in the active region only for the
positive half of the input signal.
There are two types of Class B power amplifiers: Push Pull amplifier and complementary
symmetry amplifier. In the complementary symmetry amplifier, one n-p-n and another p-n-p
transistor is used. The matched pair of transistor are used in the common collector
configuration. In the positive half cycle of the input signal, the n-p-n transistor is driven into
active region and starts conducting and in negative half cycle, the p-n-p transistor is driven into
conduction. However there is a period between the crossing of the half cycles of the input
signals, for which none of the transistor is active and output, is zero

Procedure:
1. Draw the circuit diagram after loading components from library.
2. A DC source with 0 V is place as the dummy voltage source to obtain the current
waveform.
3. Wiring and proper net assignment has been made. The circuit is preprocessed. The VI
characteristics may be obtained by performing DC transfer function Analysis. Place the
current waveform marker at the positive terminal of the dummy voltage source (voltage
=0 volts).
4. For placing waveform markers, select tools instruments set wave form content current
waveform click on the required net and place the waveform marker. The sweep
parameter (voltage) for input source is set in the Analysis window.

5. The applied voltage is swept from an initial value to final value with the steps provided
To get VI characteristics, the currents corresponding to varying input voltages are noted.

66
 Class B Power Amplifier

OUTPUT

Result :
Thus the Class B Power Amplifier circuit was simulated successfully.

67