IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 5, NO.

4, DECEMBER 2015 561

A Scaling-Friendly Low-Power Small-Area

ADC With VCO-Based Integrator and Intrinsic
Mismatch Shaping Capability
Kyoungtae Lee, Yeonam Yoon, and Nan Sun, Member, IEEE

Abstract—This paper presents a first-order scaling-friendly The advent of nanometer CMOS technology calls for a new
VCO-based closed-loop ADC. It uses the VCO as both quan- design framework for multibit ADCs that not only do not
tizer and integrator, and thus, obviates the need for power-hungry suffer from reduced power supplies and transistor intrinsic
scaling-unfriendly OTAs and precision comparators. It arranges
two VCOs in a differential manner, which cancels out even-order gains, but actually take advantage of the strengths of CMOS
distortions. Most importantly, it has an inherit mismatch shaping scaling. One clear merit of CMOS scaling is that the tran-
capability that automatically addresses the DAC mismatches. The sistor speed keeps increasing and the logic delay keeps
prototype ADC in 130 nm CMOS occupies a small area of decreasing. Thus, it is highly desirable to process the analog
only 0.03 and achieves 66.5 dB SNDR over 2 MHz BW while signal in the time domain or phase domain.
sampling at 300 MHz and consuming 1.8 mW from a 1.2 V power
supply. It can also operate with a low analog supply of 0.7 V and There have been emerging efforts in the research community
achieves 65.8 dB SNDR while consuming 1.1 mW. to use ring voltage-controlled oscillators (VCOs) to construct
phase-domain ADCs [1]–[6], [15]. Ring VCOs provide
Index Terms—Analog-to-digital converter (ADC), clocked aver-
aging, continuous-time ADC, mismatch shaping, phase-do- intrinsic integration and quantization capability in the phase
main analog signal processing, ring oscillator, time-domain ADC. domain. Its natural integration from frequency to phase pro-
vides infinite gain at DC, which is better than conventional
OTA-based integrators with only finite gain. Its phase is also
I. INTRODUCTION naturally quantized, and thus, a multibit quantizer can be
simply built by sampling the output nodes of a multistage ring

C ONVENTIONAL ADCs rely on the use of opera-

tional transconductance amplifiers (OTAs). This well-es-
tablished design methodology may encounter difficulties in ad-
VCO. There is no need to generate an array of evenly spaced
comparison voltages. The metastability rate is also much lower
[3], [4]. In addition, there are several other advantages for
vanced nanometer-scale CMOS processes due to reduced power using VCOs to replace conventional integrator and multibit
supply voltages and transistor intrinsic gains. First, since the quantizer: 1) they contain only simple inverters, and thus, are
analog signal is represented and processed in the voltage do- easy to design; 2) they are area and power efficient; 3) they
main, a smaller power supply directly leads to a smaller signal operate well under low power supply; and more importantly 4)
swing and decreased dynamic range. Second, the conventional they are scaling friendly. As technology advances, the inverter
integrator depends on the high gain of the OTAs to guarantee delay decreases and the timing resolution increases. As a result,
precision and linearity. However, the required high gain is very the performance of VCO-based ADCs improves naturally
hard to achieve with a small transistor intrinsic gain. A low with CMOS scaling.
power supply further increases the difficulty, as it prevents the Despite the many advantages mentioned above, VCO-based
use of gain boosting techniques that require stacking transistors ADCs suffer from the VCO's nonlinear voltage-to-fre-
vertically. Hence, in order to obtain the required voltage gain, quency conversion. Typically, the linearity of an open-loop
long-channel transistors, large analog supplies, and multistage VCO is limited to 6-bit or below 40 dB. To overcome this
amplifier topologies have to be used, leading to significant per- nonlinearity problem, several design techniques have been
formance penalties in chip power, area, and speed. In addition, proposed. One way as shown in Fig. 1(a) is to use digital back-
the reduced power supply voltage also makes it harder to design ground calibration to correct the nonlinearity of the VCO [1],
a multibit quantizer. Its offset requirement becomes tougher to [2]. The merit of this scheme is that it is mostly digital, but the
meet and the comparator metastability rate increases. drawback is that it requires accurate replica matching, which
is hard to guarantee under process, voltage, and temperature
(PVT) variations. The other way to solve the VCO nonlinearity
Manuscript received May 19, 2015; revised August 18, 2015; accepted
September 27, 2015. Date of current version December 23, 2015. This paper problem is to put the VCO in a closed loop with an analog
was recommended by Guest Editor K.-P. Pun. filter preceding it [see Fig. 1(b)] [3]. The gain provided
The authors are with the Department of Electrical and Computer Engi-
by helps suppress the VCO nonlinearity. Moreover, this
neering, University of Texas at Austin, Austin, TX 78712 USA (e-mail:
[email protected]; [email protected]; [email protected]). scheme has an intrinsic dynamic element matching (DEM)
Color versions of one or more of the figures in this paper are available online capability. Due to the digital differentiation at the VCO output,
at http://ieeexplore.ieee.org.
the elements in the feedback DAC are naturally selected in
Digital Object Identifier 10.1109/JETCAS.2015.2502166

2156-3357 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 562 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 5, NO. 4, DECEMBER 2015

a barrel-shifted fashion, which implicitly implements data

weighted averaging (DWA) [8]. As a result, the DAC mis-
matches are automatically shaped to the first-order. However,
the disadvantage of this scheme is that the analog filter
is scaling unfriendly and consumes large power and area. In
addition, because of the digital differentiation, the integration
capability of the VCO is canceled out. As a result, the VCO,
together with the differentiator, acts only as a quantizer, instead
of an integrator. The overall transfer function gain from the
VCO input to the ADC output is limited. Thus, the VCO input
still sees a large signal swing, which results in large distortions
and limits the overall ADC linearity. To address this issue,
the authors of [4] propose to use the VCO phase, instead of
its frequency, as the output [see Fig. 1(c)]. The VCO phase
is measured by comparing it with a reference phase derived
from the sampling clock. Since there is no differentiation in
the loop, the VCO acts as an integrator, which increases the
loop gain. The VCO input swing is substantially reduced, and
thus, its nonlinearity problem is solved. The price for using
this technique is that the intrinsic DEM capability is lost, as the
VCO phase output is thermometer coded. To address the DAC
mismatch problem, an explicit DEM block has to be used,
which leads to additional design complexity, increased loop
delay, as well as more power and area.
To simultaneously use the VCO as an integrator and main-
tain an intrinsic DEM capability, we propose a novel first-order
VCO-based ADC architecture shown in Fig. 1(d). We ar-
range two VCOs in a differential manner. The phase output of
the dual VCO is measured by comparing the phase of one VCO
with that of the other. The advantage of this scheme is that the
feedback loop operates only on the difference between the two
VCO phases and does not control the VCO center frequency.
As a result, unlike [4], the VCO center frequency does not have
to be locked to a fraction of the sampling frequency; it can be
freely chosen. As a result, we can lower the VCO frequency to
Fig. 1. (a) Open-loop VCO-based ADC with nonlinearity correction;
save power and reduce phase noise [9]. More importantly, as (b) closed-loop ADC using VCO-based quantizer; (c) closed-loop
will be explained in Section III-A, the proposed scheme results ADC using VCO-based integrator; (d) proposed closed-loop ADC using
in a natural rotation of the DAC selection pattern with the speed VCO-based integrator with intrinsic CLA.
of twice of the VCO center frequency. This effectively realizes
the data-independent DEM scheme of clocked averaging (CLA)
[10]. In other words, the proposed ADC architecture has an in- 0.03 . It achieves 66.5 dB SNDR over 2 MHz bandwidth
trinsic CLA capability. CLA modulates the DAC mismatch er- (BW) while consuming only 1.8 mW from a 1.2 V power
rors to the twice of the VCO center frequency and moves them supply. It can also work with a low analog supply of 0.7 V and
out of the signal band. As a result, no explicit DEM technique achieves 65.8 dB SNDR while consuming only 1.1 mW.
is needed. Furthermore, because the dual VCO is used as an in- We have reported part of this work at conferences [11], [12].
tegrator, it provides a large loop gain to suppress the VCO non- However, due to page limitation, many important details and
linearity. Its pseudo-differential structure also helps cancel out measurement results are omitted. The contribution of this paper
even-order distortions. Additionally, a large number (e.g., 25) is that it provides thorough analyses on the proposed ADC op-
of VCO stages can be used to increase the effective phase quan- eration and covers all the key design considerations. This paper
tizer resolution and further suppress the signal swing at the VCO is organized as follows. Section II explains the proposed ADC's
input. As a result, the analog filter is no longer needed phase-domain operation. Section III discusses its intrinsic CLA
from the linearity point of view. and PWM behavior. Section IV presents the detailed circuit de-
The proposed ADC architecture does not need any sign. Section V shows the measurement results. The conclusion
analog filter, external DEM, or calibration. It is only comprised is in Section VI.
of VCOs, phase quantizers, and DACs. Thus, it is highly
scaling friendly; it occupies a small area and consumes low II. ADC PHASE DOMAIN OPERATION
power, especially in advanced processes. A prototype ADC In the proposed closed-loop ADC, the subtraction be-
implemented in 130 nm CMOS occupies an active area of only tween the ADC input and the DAC output is realized in the cur-

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 LEE et al.: A SCALING-FRIENDLY LOW-POWER SMALL-AREA ADC 563

Fig. 2. Three possible scenarios during initial ADC power up for 5-stage CCOs: (a) CCO1 leads CCO2 by ; (b) CCO1 leads CCO2 by ; and (c) CCO1
lags CCO2 by . and represent the frequency and the phase of . represents the th unit DAC element.

TABLE I
SUMMARY OF THE CCO OPERATION ASSUMING A DC INPUT circle shown at the center of Fig. 2 corresponds to the CCO
phase range from to , not from to .1
The DACs after the XOR gates are the feedback current-
steering unary DAC elements [see Fig. 1(d)]. If the XOR output
is 1, the corresponding unit DAC drains current away from
CCO1, decreasing its frequency. By contrast, if XOR output is
0, it decreases CCO2 current and frequency.
rent domain. The integration and quantization are realized by When the ADC is initially powered up, the phase of the two
two ring oscillators in the phase domain. Since it is easier to CCOs are placed at random locations. There are three possible
view the ADC operation in the current domain, we consider the scenarios for the relationship between the initial phases of the
oscillators as current controlled oscillators (CCOs), even though two CCOs: 1) CCO1 leads CCO2 by less than ; 2) CCO1
it is also valid to view them as VCOs. The ADC digital output leads CCO2 by more than ; and 3) CCO1 lags CCO2, which
corresponds to phase difference between the two CCOs, which is an unstable situation, as the XOR-based phase detector has a
can be simply taken out by letting them refer to each other. In negative gain.
steady state, the feedback loop ensures that the center frequen- Fig. 2(a) shows an example of case 1) where CCO1 leads
cies for the two CCOs are the same and their phase difference is CCO2 by . The digital output , which is the sum of
proportional to the analog input . If the ADC digital output all XOR outputs, is 1. Only DAC5 draws current from CCO1
increases, CCO1 current decreases while CCO2 current while all other DAC elements draw current from CCO2. Thus,
increases. The detailed relationship for the two CCOs are sum- the CCO1 frequency is higher than that of CCO2. This makes
marized in Table I. CCO1 phase propagate faster than CCO2 phase. As a result,
To understand how the ADC works, let us first consider a their phase difference increases until it reaches , which is
zero input and two 5-stage CCOs for simplicity. As the steady state where oscillates between 2 and 3.
shown in Fig. 2, the inner and outer loops are CCO1 and CCO2, Fig. 2(b) illustrates case 2) where CCO1 leads the CCO2 by
respectively. The outputs of the two CCOs are compared with and the digital output is 4. Since only DAC4 input is 0
each other using XOR gates. and all other DAC inputs are 1, there is more current flowing
When inverters are not flipping, their inputs and outputs are through CCO2, making its frequency greater than that of CCO1.
opposite. Since there is an odd number (e.g., 5) of inverters in Thus, the phase difference decreases, and eventually, the loop
the VCO ring, one inverter must have the same input and output also goes into the steady state where the phase difference of the
(both high or both low), and is in transition. This transitioning two CCOs stays around .
point indicates that the CCO phase has propagated to that in- Fig. 2(c) corresponds to case 3) where CCO1 lags CCO2 by
verter. . Only DAC4 input is 1 and all others' inputs are 0. This
Note that an entire CCO period corresponds to going around means that the current flowing into CCO1 is higher than that for
the CCO ring twice. This is because an inverter's output is CCO2. Thus, CCO1 phase propagates faster than that of CCO2.
flipped after only one transition. Two transitions are needed to After certain time, CCO1 phase catches up and surpasses CCO2
return to the original state. Since one CCO period corresponds 1This may appear inconsistent with the convention that going around one
to the phase of , going around the CCO ring once means cycle should be instead of . Note that here the phase label is referring to
that the CCO phase has only propagated by . Thus, the phase the global CCO phase instead of the CCO ring.

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 564 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 5, NO. 4, DECEMBER 2015

Fig. 3. Example phase domain operation for the proposed ADC with 25-stage CCOs and zero input.

Fig. 4. (a) Phase diagram of the proposed ADC with 25-stage CCOs and nonzero input; (b) example phase domain operations.

phase, and thus, the state goes into case 1). Thus, the loop even- CCOs, which propagates at the speed of
tually goes into the steady state even if the initial state is un- [see Fig. 4(a)]. Note that the ADC input does not change
stable. because the input current feeds into the two CCOs in a differ-
Each 1-bit DAC element can be mapped to a CCO ential manner. When input changes, it speeds up one CCO but
phase. Assuming there are CCO stages and DAC elements, slows down the other. What varies with input is the phase differ-
is mapped to the CCO phase of for ence between CCO1 and CCO2, or the differential-mode phase
and for . The input to is 1 if its . Fig. 4(b) shows an example of the phase do-
corresponding phase is between the phases of CCO1 and CCO2. main operation with a sinusoidal input. The CCO phase differ-
In our prototype ADC, each CCO consists of 25 stages. The ence is proportional to the input, but its center phase
phase diagram is shown in Fig. 3. As explained earlier, assuming propagates with a constant speed independent from the input.
and the loop is in steady state, CCO1 leads CCO2 by At every clock cycle, is sampled and quantized, producing
, and oscillates between 12 and 13. the ADC digital output. The understanding of the phase domain
We can consider CCO1 and CCO2 together as a dual CCO. operation is critical for understanding the intrinsic DEM capa-
Its common-mode phase is the center phase of the two bility for the proposed CCO-based ADC.

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 LEE et al.: A SCALING-FRIENDLY LOW-POWER SMALL-AREA ADC 565

Fig. 5. DAC element selection pattern and ADC output spectrum with (a) ther-
mometer coding and (b) intrinsic CLA with . The solid box in
the selection pattern means that its corresponding element is selected. Fig. 6. (a) PWM behavior of the phase quantizer; (b) simplified PWM be-
havior; (c) DAC1 input PWM waveform.

III. INTRINSIC DAC MISMATCH SHAPING CAPABILITY

is quite different from that of a conventional voltage-domain
A. Intuitive Explanation quantizer. For a DC input, the conventional quantizer always
outputs a fixed value. By contrast, for the proposed phase quan-
DAC mismatch is a major issue for multi-bit ADC. Since
tizer, even if its equivalent quantizer input, which is the differ-
the mismatch error directly adds to the input, it can severely de-
ential phase , stays unchanged, its output oscil-
grade the ADC linearity. To see this, we simulated a first-order
lates between two adjacent levels. This is because the common-
ADC with a 25-element DAC selected in a thermometer-
mode phase constantly moves ahead at
coded way. In the absence of mismatch, the SNDR at the over-
.
sampling ratio (OSR) of 75 is 80 dB. However, as shown in
The proposed dual-CCO phase quantizer essentially performs
Fig. 5(a), the SNDR decreases to only 54 dB with 1% element
a pulse width modulation (PWM) of its input . To explain
mismatch. There are large in-band harmonic distortions.
it clearly, let us examine the CCO phase dynamics shown in
The proposed ADC has an intrinsic CLA capability that effec-
Fig. 4. The input to DAC1 (i.e., the output of the single-bit phase
tively addresses the DAC mismatch issue without any hardware
quantizer XOR1) is 1 when its corresponding phase, which is 0,
cost. One intuitive way to understand it is as follows. As dis-
is in between and . Mathematically speaking, this means
cussed in Section II and shown in Fig. 4, the middle point of the
DAC selection pattern corresponds to the dual CCO common- (1)
mode phase . Since one CCO period means going around
(2)
the ring twice, the DAC middle point rotates at . This
leads to the DAC selection pattern shown in Fig. 5(b), where which combines into
we assume . This selection pattern matches the
behavior of the CLA technique [10]. The DAC mismatch er- (3)
rors are up-converted to and moved out of the signal
band [see Fig. 5(b)]. Thus, the SNDR is significantly improved The time domain waveforms for and are
to 77 dB, which is only 3 dB lower than the ideal case with no plotted in Fig. 6(a). As explained in Section II, in steady state,
mismatch. This intrinsic CLA allows the use of small DAC el- always leads , and their difference oscillates around .
ements. It reduces the design complexity, shortens the excess Thus, is centered around and is bounded by
loop delay, and saves chip area and power. . The shaded region in Fig. 6(a) is where the inequality
of (3) is satisfied, leading to DAC1 input being 1. This can
B. Comprehensive Analysis of Dual-CCO-Based Quantizer be simplified to Fig. 6(b), in which are merged
The prior subsection intuitively explains the intrinsic CLA into one triangular wave. The corresponding DAC1 input is in
scheme. To understand it thoroughly, we need to investigate Fig. 6(c). It can be considered as the output of a comparator that
the behavior of the proposed dual-CCO phase quantizer, which compares with the triangular wave. Such operations

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 566 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 5, NO. 4, DECEMBER 2015

Fig. 7. Equivalent circuit diagram for the phase quantizer.

Fig. 10. Equivalent block diagram of the proposed ADC.

mismatches, the overall DAC output still has PWM tones, as

Fig. 8. Simulated single DAC element input waveform. shown earlier in Section III-A. However, there is no distortion
in band due to the PWM behavior. Thus, as long as the up-con-
verted tones are out of the signal band, the DAC mismatch issue
is solved in the proposed ADC architecture. By contrast, in the
ADC architecture of [4], since the is locked to , the
DAC middle point rotates at in the DAC selection pat-
tern. This means that the modulated DAC mismatch tones at
overlap at DC, leading to large in-band distortions and
requiring an external DEM block to address the DAC mismatch
errors.

C. DAC Dynamic Error Analysis for CLA

In addition to the static mismatch error, another major error
source for DAC is the dynamic switching error during DAC
element transitions. Different from the static mismatch error, the
dynamic switching error is present even for a single-bit DAC.
Fig. 9. Simulated single DAC element input spectrum. It arises from clock feedthrough, clock skew, device parasitic
capacitance, and memory effects. It can be considered as a form
of inter-symbol-interference (ISI) [17]–[19].
exactly matches the natural sampling PWM scheme shown in
In general, the amount of dynamic error is proportional to
Fig. 7.
the DAC element transition rate. Thermometer coding has the
For a PWM signal, its information is captured in the pulse
smallest dynamic error due to its lowest transition rate, but it
width. Fig. 8 shows a simulated digital input of a single DAC
cannot handle the static mismatch error [17]. By contrast, DWA
element for a sinusoidal ADC input. Its spectrum is shown in
is effective at addressing the static mismatch error, but it has
Fig. 9. As is well known, PWM does not produce distortions
the largest dynamic error. Its DAC transition rate is the highest
in the signal band, but has tones around the carrier frequency
among all DEM techniques [18], [19]. This is because DWA
and its higher order harmonics.
generally turns off previous selected elements and turns on new
Other DAC elements operate in the same way as DAC1. For
ones. Moreover, its transition rate is highly dependent on the
example, DAC2, whose corresponding CCO phase is , has
DAC input . It is easy to derive the average transition rate
an input of 1 when is greater than the same trian-
for DWA as (including both up (0 1) and down (1 0)
gular wave but phase shifted by . Thus, we can build a
transitions) [18]
voltage-domain model that accurately describes the behavior of
the proposed ADC, which is shown in Fig. 10. Negative ports of if ,
(4)
the comparators are the phase shifted triangular waves. When 25 if .
digital outputs are summed up, the up-converted PWM tones do where and are normalized values in between 0 and 1.
not show up in the output spectrum assuming perfect matching This relationship is plotted in Fig. 11. At , during every
in the CCO stages and DACs. This is because the PWM tones clock cycle, half DAC elements are switched off and the rest are
have the same magnitude but with evenly spaced phase offsets; turned on. Thus, all DAC elements are in transition, leading to
their vector sum is 0. Nevertheless, because DAC elements have the peak . The triangular relationship between

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 LEE et al.: A SCALING-FRIENDLY LOW-POWER SMALL-AREA ADC 567

Fig. 12. Simulated ADC output spectrum with 0.1% dynamic error using (a)
DWA and (b) CLA.

Fig. 11. Simulated DAC element transition density versus input level.
IV. PROPOSED ADC DESIGN AND ANALYSIS

and (see Fig. 11) leads to a large second-order distortion [20], A. Circuit Implementation
[21]. As a result, DWA is hardly used in high-resolution contin-
Fig. 13(a) shows the circuit implementation of the proposed
uous-time modulators. Instead of being a nonlinearity sup-
ADC. The input voltage is converted to a current by a resistor
presser, it can act as a tone generator [17]–[19].
, which is placed off-chip for tunability. is chosen to be
The proposed intrinsic CLA has much smaller DAC dynamic
large enough (2.4 ) so that it allows a large input swing of
error compared to DWA. The reasons are as follows. First, its 2.4 V Vpp and contributes a small noise current. The input cur-
number of DAC element transitions is much fewer than that for rent flows into two 25-stage CCOs. Each delay cell consists of
DWA. As shown in Fig. 5(b), the intrinsic CLA keeps the ma- 4 inverters [see Fig. 13(b)]. The inner cross-coupled inverters,
jority of the DAC inputs unchanged. There are large overlaps whose width is one third of that of the outer ones, ensure differ-
between adjacent selected elements. Since the DAC element ro- ential operation and a sharp transition edge. The replica buffers
tation speed is , and there are 2 transitions (1 up and 1 are used to isolate kickback noise from the comparators. Its
down) for each DAC element during every rotation, the average schematic is similar to that of the delay cell except that it has
DAC element transition rate for CLA is given by (as long as the a tail transistor with a fixed bias [see Fig. 13(c)]. The compara-
DAC input level is not too low or too large) tors, which adopt a two-stage topology for faster regeneration
[see Fig. 13(d)], sample the output of the replica buffers. XORs
(5) then take the phase difference. The digital output feeds back to
the input by a 25-element current-steering DAC. Most of the
feedback DAC current are pulled from the CCO, assuming
Hence, having a small mitigates the dynamic error. The
is large enough. The bias current to the CCOs and the feed-
proposed ADC allows to be changed without affecting
back DAC is supplied by the PMOS current sources and the
the feedback loop operation, and thus, we can decrease
common-mode current through .
to reduce the dynamic error. For example, if we set
Interestingly, if the CCO center frequency is set to be low
and as in the prototype ADC, the DAC
enough to reduce its power consumption, the PMOS current
transition rate is only 6%, which is much smaller than
sources are no longer required, and thus, all DC current needed
, as shown in Fig. 11. Furthermore, unlike DWA, by the DAC and CCOs can be supplied by . In this case,
does not depend on . This leads to much smaller harmonic dis- since the CCO only requires a low voltage of 400 mV, the analog
tortion. Note that although the average transition rate is power supply can be lowered to 0.7 V. This bias setup will be
input independent, its instantaneous number of DAC transitions referred to as the low-power mode. In this case, the ADC input
is still input dependent. Thus, CLA cannot completely avoid dy- common mode is set to 0.7 V, which is the analog power supply.
namic error induced distortion. In practice, the relationship be- This significantly reduces the analog power consumption. Being
tween the dynamic error and the instantaneous DAC transition able to operate under a low power supply of 0.7 V is another
rate is nonlinear. Thus, generally, it is preferred to lower the merit for using CCOs to construct ADCs. The trade-off for
DAC element transition rate, so that not only the total amount using a 0.7 V analog supply is that to provide enough DC cur-
of dynamic error but also its nonlinear portion are reduced. rent, needs to be small, which reduces the input swing from
The analyses above are confirmed via behavioral simulations 2.4 V Vpp to 0.95 V Vpp. A smaller leads to increased input
in MATLAB. Fig. 12 shows the simulated ADC output spectra referred noise current. It also reduces the amount of feedback
with 0.1% dynamic switching error. When DWA is used, there DAC current going into the CCO, which lowers the loop gain.
is a large second-order distortion, limiting the SFDR to only They together result in a slight degradation in the SNR (see the
67 dB. By contrast, when CLA is used, the in-band distortion measurement result in Section V).
is much smaller, which is due to its significantly reduced DAC The reason for using current to control frequency is that it is
transition rate and input dependence. more linear than using voltage, which is shown in the measured

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 568 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 5, NO. 4, DECEMBER 2015

Fig. 13. Schematics of (a) ADC architecture; (b) delay cell; (c) VCO output buffer; (d) comparator; and (e) die photo.

B. CCO Mismatch Analysis

Because the proposed ADC uses two CCOs, their mismatch
may cause performance degradation. To focus our analysis on
the CCO mismatch, let us assume that the ADC input is fully
differential and the DAC elements are matched. Thus, the input
current to the dual CCO is fully differential, and the CCO fre-
quencies can be expressed as follows:

(6)
Fig. 14. Measured CCO tuning characteristics: (a) voltage versus frequency;
(b) current versus frequency; and (c) current versus voltage.
where ( ,1) is the CCO center frequency, is the CCO
current to frequency gain, is the CCO current, and is the
coefficient for the dominant second-order distortion. Thus, the
CCO tuning curves of Fig. 14(a) and (b). A qualitative explana-
differential mode frequency for the dual CCO is given by
tion is that there is a direct relationship between the CCO fre-
quency and current. For a ring oscillator, its frequency is propor-
tional to how fast charges move in and out of its internal nodes, (7)
which is directly related to the CCO current. When choosing the
CCO center frequency , we want it to be small to reduce The mismatch in the CCO center frequency and acts
power and DAC dynamic error, but we also want it to be large like an offset. It does not cause distortion, but it decreases the
enough so that: 1) the frequency tuning is linear; 2) the up-con- differential signal swing. However, as long as and are
verted DAC mismatch errors are out of the signal band; and close, the signal swing attenuation is negligible. The variation
3) the CCO input impedance, inversely proportional to in and only slightly changes the differential current to
[see Fig. 14(c)], is small enough to receive the majority of feed- frequency gain. This does not cause distortion either. Since the
back DAC current. After balancing these tradeoffs, we set it to proposed ADC is first-order, small variations in differen-
be around 4.5 MHz which leads to a low current consumption tial CCO gain have only minor effects on the overall ADC per-
of 130 A, a small control voltage of 400 mV, and the input formance. The mismatch between and causes the imper-
impedance of 1 . During the ADC testing, we set by fect cancelation of the second-order distortion. Nevertheless,
adjusting the CCO current using the bias voltages of the PMOS as long as and match reasonably well, the majority of
current sources (see M1 to M4 in Fig. 13). the second-order distortion is still canceled out, which is much
The effective quantizer resolution for a 25-stage CCO is 4.6- better than using a single CCO without any distortion cance-
bit. The loop gain is proportional to the CCO current-to-fre- lation. Also, the ADC feedback loop minimizes . As a re-
quency gain and the DAC current. The measured is about sult, the proposed ADC architecture is reasonably robust against
200 GHz/A and the unit DAC current is 26 A. This leads to an CCO mismatches. As shown in the measurement results (see
estimated SQNR of 78 dB at the OSR of 75. Section V), without any CCO calibration, the ADC is able to

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 LEE et al.: A SCALING-FRIENDLY LOW-POWER SMALL-AREA ADC 569

TABLE II
INPUT REFERRED CURRENT NOISE POWER SPECTRAL DENSITY

Fig. 17. Measured 65536 point FFT plot of the ADC output in low-power
mode.

Fig. 15. Measured time domain ADC output.

Fig. 18. Measured SNR and SNDR versus input amplitudes for both normal
and low-power modes.

Fig. 16. Measured 65536 point FFT plot of the ADC output in normal mode.

achieve 73 dB SFDR while using small area VCO cells with

large mismatches.

C. Thermal Noise Analysis

The thermal noise in the proposed ADC comes from four
components: the input resistor, the bias current source, the feed-
back DAC, and the CCO. Since the circuit works in the current
domain, it is more straightforward to compute input referred Fig. 19. Measured 65536 point FFT plot when 100 mV 94.5 kHz signal is
noise current. The power spectral density (PSD) of the noise injected in analog power supply.
current produced by the input resistor is given by , and is
computed to be 3.71 for two resistors. The bias PMOS
current sources (see M1-M4 in Fig. 13) and the DAC current . Their SPICE simulated values are 6.94 and
sources produce channel thermal noise whose PSD formula is 6.56 , respectively.

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 570 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 5, NO. 4, DECEMBER 2015

Fig. 20. Measured 65536 point FFT plot for of (a) 0.9 MHz (b) 1.2 MHz (c) 2 MHz.

Fig. 21. Measured 65536 point FFT plot for of (a) 3.3 MHz; (b) 5 MHz; (c) 8.5 MHz.

For the CCO, its phase variance over one clock period is to a thermal noise limited SNR of 83 dB assuming a 2 MHz
given by signal bandwidth and a 2.4 V peak-to-peak differential input
signal swing.
(8)
V. ADC MEASUREMENT RESULTS
where is the phase diffusion constant and can be obtained A. Normal and Low-Power Mode Measurement Results
from phase noise simulation [22]. To compute the input referred
CCO noise current, we need to divide (8) by the overall gain The prototype ADC is implemented in 0.13- CMOS
from the CCO input current to the CCO phase propagation over process with an active area of only 0.03 as shown in
one clock period, which is Fig. 13(e). The sampling frequency and the signal bandwidth
are 300 MHz and 2 MHz, respectively. We choose the OSR of
75 to balance the trade-off between the signal bandwidth and
(9) the SNDR. Fig. 15 shows the measured time domain output
waveform. The full digital output swing is from 0 to 25, as the
Finally, using Parseval's theorem, we can derive the PSD of the CCO consists of 25 delay cells. There is an offset of about 2
input referred CCO noise current LSB due to mismatches between the two CCOs.
Fig. 16 shows the ADC output spectrum in the normal mode
with a 1.2 V analog power supply and a 0.9 dBFS 661.5 kHz
(10)
input. The 20-dB/dec first-order noise shaping is clearly seen.
There are tones centered around the CCO harmonics, which is
Based on the SPICE simulated at , we cal- the effect of the intrinsic CLA as explained in Section III. The
culate the dual CCO input referred noise current PSD to be 4.8 hump at around 40 MHz is due to the excess loop delay [23]
. It is well known that the CCO phase noise decreases and the parasitic pole at the CCO input node [5], which alter
as the CCO operating frequency decreases [9]. Therefore, this the loop transfer function. The excess loop delay comes from
is another merit of the proposed dual-CCO based architecture the comparator, the XOR, and the DAC. It is about 20% of the
where can be decreased to minimize the phase noise. clock period. It does not affect the in-band performance of the
Table II summarizes the thermal noise values. The total input proposed ADC as it is only first order. To simplify the cir-
referred current noise PSD is 11.3 , which translates cuit, we choose not to compensate the excess loop delay [24].

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 LEE et al.: A SCALING-FRIENDLY LOW-POWER SMALL-AREA ADC 571

TABLE III
COMPARISON WITH RECENT CT ADCS USING VCOS AND/OR HAVING SIMILAR BW

The measured SFDR of 73 dB is limited by the second-order ratio of the input tone injected at the supply over the detected
distortion, which is likely due to DAC mismatches and CCO tone at the ADC output, and thus, we compute the PSRR as
mismatches that cause imperfect cancelation of even order dis-
tortions. The measured SNDR and SNR are 66.5 dB and 68 dB, (11)
respectively. The in-band noise consists of quantization noise, This shows that the proposed ADC can attenuate power supply
thermal noise, DAC mismatch noise, and noise due to clock noise by around 100 times. Thus, it is reasonably robust against
jitter and signal dependent comparator delay [23]. The main power supply noise. Even if there are 10-mV rms noise on the
contributor is the DAC mismatch error. Based on the height of analog supply line, the SNDR degradation is negligible.
up-converted DAC mismatch tones, the estimated DAC element
mismatch is about 2%, which by itself limits the SNR to about C. Experimental Studies of CLA
71 dB. The DAC mismatch arises mainly from transistor To experimentally study the intrinsic CLA behavior,
variations, limited by the small unit DAC element area of only and are varied. Fig. 20 shows the output spectra with
6 by 4.5 . varying while keeping all other conditions the same. As
The ADC output spectrum in the low-power mode with a increases, the gap between the tones located near
0.7 V analog power supply and a 0.9 dBFS 661.5 kHz input increases, but the gap size is always equal to . Fig. 21 shows
is shown in Fig. 17. SNDR slightly decreases to 65.8 dB for the the output spectra with varying . As expected, the fre-
reasons explained in Section IV, but the total power is reduced quencies of the PWM tones increase as increases. These
to 1.06 mW which includes the current supplied by the off-chip measured results match well with the PWM behavior, which
input resistor. firmly validates the analyses in Section III.
The measured SNDR and SNR with varying input amplitudes
for both normal and low-power modes are shown in Fig. 18. It D. Performance Summary
can be seen that the ADC maintains a good performance over In the normal mode, the measured analog power is 1.13 mW,
a wide signal range. The peak SNDR is achieved at the input which includes the CCOs, the DAC, the replica buffers, and the
amplitude of 0.9 dBFS. comparators. The measured digital power is 0.62 mW, which
includes the XORs, flip-flops, and the thermometer-to-binary
B. PSRR Measurement encoder. When operating in the low-power mode, the analog
Since the core of the ADC is a ring oscillator, a major concern power drops to 0.45 mW. The corresponding Walden figure-of-
is its power supply rejection ratio (PSRR). To test it, a 100-mV merits (FOMs) with 1.2 V and 0.7 V analog power supplies are
( 27.6 dBFS) 94.5 kHz sinusoidal signal is injected into the 0.25 pJ/conversion-step and 0.17 pJ/conversion-step, respec-
1.2 V analog power supply. Fig. 19 shows the ADC output spec- tively. Table III compares this work with other VCO-based
trum. A tone at 94.5 kHz with the amplitude of 67 dBFS (i.e., ADCs and recently published conventional ADCs. In terms
1.1 mV when referred to the ADC input) is clearly seen. Ac- of FOM, this work achieves the comparable performance es-
cording to the convention, we define the PSRR as the amplitude pecially considering its relatively old technology of 130 nm.

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 572 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 5, NO. 4, DECEMBER 2015

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IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 172–173. received NSF Career Award in 2013.

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