Electronic Circuits Experiment Department of Electrical Engineering

National Taiwan University

Laboratory Exercise 1

Introduction of Device and Program Interface

I. Objectives
The purpose of this exercise is to know the program Vivado and the development board
EGO1. First, we will know the Vivado design flow, and then some examples will be
introduced for exercises.

II. Experiment Equipment

Equipment Quantity
Computer 1
USB with Vivado program 1
USB cable 1
EGO1 1

III. FPGA Introduction

A. Design Flow

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 Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
B. Vivado Tools

(General Purpose Input/Output)

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National Taiwan University

IV. Lab Work

Step0: Hardware Mode Setting
1. Use USB cable to connect FPGA with your computer.
2. Turn on the power

Mode Setting: Do not touch the Jumper.

Remember to turn on the power.

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Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step1: Start Vivado & Create Project
1. Insert the USB we provide into your computer
2. Find the program F:/Vivado/2017.4/bin/vivado.bat
3. Click twice “vivado.bat” to open Vivado (If your filename extension isn’t shown on
your filename, please find vivado whose 類型 is Windows 批次檔案)

4. Create Project
5. Click Next

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Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step2: Enter project name and location
1. The Project location is set at will
2. Click Next

Step 3: Search xc7a35tlcsg324-2L

1. Click “Next” three times
2. Search “xc7a35tlcsg324-2L”
3. Click” Next” and “Finish”

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Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 4: Copy Constraint and Source files to your project location.
Copy files to project location is a good habit:
When modifying files, you won’t modify them which are utilized by other projects

Step 5: PROJECT MANAGER, Add Source

1. In this step, you will add your source file(.v) to Vivado
2. Click “Add Sources” under Project Manager

3. Select “Add or create design sources” → “Next” → “ADD Files” → “Source”

→ ”dont touch” → CTRL+A (select all) → “OK” → “Finish”

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Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University

Step 6: PROJECT MANAGER, Add Constraint File

1. In this step, you will add your constraint file(.xdc) to Vivado. Constraint files can
bridge your design to the I/O interface of FPGA
2. Click “Add Sources” under Project Manager
3. Select “Add or create constraints” → “Next” → “ADD Files” → “Constraint” →
..Select “EGO1.xdc” → “OK” → “Finish”.

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Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 7: Generate Bitstream.
1. Click “Generate Bitstream” under PROGRAM AND DEBUG. This includes synthesis
and implementation. (What is Bitstream? See Appendix)
2. Click “Yes” and “OK”, then wait Vivado running Design Flow (This may take some
time. If synthesis failed, please check your previous steps are all corrected.).

3. If design flow is completed, the status of Synthesis and Implementation will show
“Complete” ,and then it will pops out “Bitstream Generation Completed” window
(You can ignore all warnings in this step)
4. Select “Open Hardware Manager”, then press OK.

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Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 8: Program into FPGA
1. Press “Open Target”, select “open new target”

2. Click “Next” twice

3. Find your FPGA device, Select “xc7a35t”, Click “Next” and “Finish” (This step will
take 1-5 minutes to download some software in your computer to recognize the FPGA.
If beyond 5 minutes, try to use another FPGA or change another computer.)

4. Click “Program device”

5. Find your bit file. If no files, please find [Project_name].runs/impl_1/EGO1_Top.bit
6. Press “Program”.

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Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 9: Test your design!
Now you can use SW15~SW8 as input A, SW7~SW0 as input B, both are expressed in
binary and unsigned. Buttons are used for different modes. This is a calculator done by
Boolean Logic!
Input A and B are expressed in binary, the result will Scroll.

Seven-segment as display

BtnU, BtnD, BtnR,

BtnL, BtnC

SW15~SW8 as input A SW7~SW0 as input B

Inputs from the Push Buttons (btnU, btnD, btnR, btnL, btnC) will allow the user to select
different arithmetic operations that will be computed on the inputs A and B.

BtnU: Substraction / Difference (A-B)

When A>B, difference is positive.
When A<B, difference is negative. If the button is not held down but just pressed once, the
result will scroll. To find out if the result is negative, press and hold onto the push button
btnU. This will show the negative sign.

BtnD: Multiplication / Product (A*B)

BtnR: Quotient (Division Operation) (A/B)

BtnL: Remainder ( Division Operation) (A/B)

BtnC: Adder (A+B)

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 Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University

V. Appendix
FPGA Bitstream

An FPGA bitstream is a file that contains the programming information for an FPGA. A
Xilinx FPGA device must be programmed using a specific bitstream in order for it to behave
as an embedded hardware platform. This bitstream is typically provided by the hardware
designer who creates the embedded platform.

Programming an FPGA is the process of loading a bitstream into the FPGA. During the
development phase, the FPGA device is programmed using utilities such as Vivado® or
using menu options in SDK. These tools transfer the bitstream to the FPGA on board. In
production hardware, the bitstream is usually placed in non-volatile memory, and the
hardware is configured to program the FPGA when powered on.

Reference:
https://www.xilinx.com/html_docs/xilinx2018_1/SDK_Doc/SDK_concepts/concept_fpgabi
tstream.html

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