SERVICE

MANUAL

STEREO/DUAL 31-BAND GRAPHIC

EQUALIZER
GEQ-1231D/2231D

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MADE IN KOREA
2003.2 9017100300
 MICOM DATA

MM74HC4051 8-CHANNEL ANALOG MULTIPLEXER

GENERAL DESCRIPTION
The MM74HC4051, MM74HC4052 and MM74HC4053 Multiplexers are digitally controlled analog switches
implemented in advanced silicon-gate CMOS technology. These switches have low “on” resistance and
low “off” leakages. They are bidirectional switches, thus any analog input may be used as an output and
vice-versa. Also These switches contain linearization circuity which lowers the on resistance and increases
switch linearity. These devices allow control of up to ± 6V(peak) analog signals with digital control signals
of 0 to 6V. Three supply pins are provided for VCC, ground, and VEE. This enables the connection of 0-5V
logic signals when VCC = 5V and an analog input range of ± 5V when VEE = 5V. All three devices also have
an inhibit control which when HIGH will disable all switches to their off state. All analog inputs and outputs
and digital inputs are protected from electrostatic damage by diodes to VCC and ground.

This device connects together the outputs of 8 switches, thus achieving an 8 channel multiplexer. The
binary code placed on the A, B, and C select lines determines which one of the eight switches is “on”, and
connects one of the eight inputs to the common output.

FEATURES
• Wide analog input voltage range: ±6V
• Low on resistance: 50 typ.(VCC-VEE = 4.5V), 30 typ.(VCC-VEE = 9V)
• Logic level translation to enable 5V logic with ± 5V analog signals
• Low quiescent current: 80µA maximum (74HC)
• Matched Switch characteristic

ORDERING CODE:
Order Number Package Number Package Description
MM74HC4051M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012,0.150˝ Narrow
MM74HC4051WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013,0.300˝ Wide
MM74HC4051SJ M16D 16-Lead Small Outline Package (SOP), ELAJ TYPE ll, 5.3mm Wide
MM74HC4051MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide
MM74HC4051N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-0010.300˝ Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

CONTENTS
Micom Data 1 ~ 21
Specifications 22
Electrical Parts List 23 ~ 24
Top and Bottom View of P.C. Board 25 ~ 29
Wiring Diagram 30
Block Diagram 31~ 32
Schematic Diagram 33 ~ 50
Exploded View of Cabinet & Chassis / Mechanical Parts List 51 ~ 54
Ass’y Drawing 55 ~ 58

1
CONNECTION DIAGRAMS (Pin Assignments for DIP, SOIC, SOP and TSSO) PHYSICAL DIMENSIONS inches (millimeters) unless otherwise noted

Top View

TRUTH TABLES

Input “ON”
Inh C B A Channel
H X X X None
L L L L Y0
L L L H Y1
L L H L Y2
L L H H Y3
L H L L Y4
L H L H Y5
L H H L Y6
L H H H Y7

LOGIC DIAGRAMS

2 3
74LV164 8-bit SERIAL-IN / PARALLEL-OUT SHIFT REGISTER PIN CONFIGURATION

FEATURES

– Wide operating voltage: 1.0 to 5.5V

– Optimized for Low Voltage applications: 1.0 to 3.6V
– Accepts TTL input levels between VCC=2.7V and VCC=3.6V
– Typical VOLP (output ground bounce) < 0.8V@VCC=3.3V, Tamb=25°C
– Typical VOHV (output VOH undershoot) > 2V@VCC=3.3V, Tamb=25°C
– Gated serial data inputs – Asynchronous master reset
SV00381
– Output capability: standard – ICC category: MSl

DESCRIPTION PIN DESCRIPTION

The 74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT164. Pin Number Symbol Function
1, 2 Dsa, Dsb Date inputs
The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the 3, 4, 5, 6 Q0 to Q7 Outputs
eight stages. Data is entered serially through one of two inputs(Dsa or Dsb); either input can be used as an 10, 11, 12, 13
active HIGH enable for data entry through the other input. Both inputs must be connected together or an 7 GND Ground(ov)
unused input must be tied HIGH. 8 CP Clock input (LOW-to-HIGH, edge-trig-gered)
9 MR Master reset input (active LOW)
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, 14 VCC Positive supply voltage
which is the logical AND of the two data inputs (Dsa, Dsb) that existed one set-up time prior to the rising clock edge.

LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC)

A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously,
forcing all outputs LOW.

QUICK REFERENCE DATA

GND = OV; Tamb = 25°C; tr=tf ≤ 2.5ns
Symbol Parameter Conditions Typical Unit
tPHL, tPLH Propagation delay C L=15pF 12 ns
CP to Qn VCC=3.3V 12
MR to Qn
fmax Maximum clock frequency 78 MH Z
SV00382 SV00383
Cl Input capacitance 3.5 pF
CPD Power dissipation capacitance per gate VCC=3.3V 40 pF
Notes 1 and 2
NOTES 1: CPD is used to determine the dynamic power dissipation (PD in µW) FUNCTIONAL DIAGRAM
PD = CPD x VCC2 x fi + ∑(CL x VCC2 x fO) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fO = output frequency in MHz; VCC = supply voltage in V;
∑(CL x VCC2 x fO) = sum of the outputs.
2: The condition is Vl = GND to VCC

ORDERING INFORMATION
Packages Temperature Range Outside North Amerlca North Amerlca Pkg. Dwg.#
14-Pin Plastic DIL -40°C to + 125°C 74LV164N 74LV164N SOT27-1
14-Pin Plastic SO -40°C to + 125°C 74LV164D 74LV164D SOT108-1
14-Pin Plastic SSOP Type II -40°C to + 125°C 74LV164DB 74LV164DB SOT337-1 SV00384
14-Pin Plastic TSSOP Type I -40°C to + 125°C 74LV164PW 74LV164PW DH SOT402-1

4 5
SO14 : plastic small outline package; 14 leads; body width 3.9 mm AD7819 2.7V to 5.5V, 200 kSPS 8-bit SAMPLING ADC

FEATURES

– 8-Bit ADC with 4.5 µs Conversion Time

– On-Chip Track and Hold
– Operating Supply Range : 2.7V to 5.5V
– Specifications at 2.7V-3.6V and 5V ± 10%
– 8-Bit Parallel Interface : 8-Bit Read
– Power Performance
Normal Operation : 10.5mW,VDD=3V
– Automatic Power-Down : 57.75µW@1kSPS,VDD=3V
– Analog Input Range : 0V to VREF
– Reference Input Range : 1.2V to VDD

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION
DIMENSIONS (inch dimensions are derived from the original mm dimensions) The AD7819 is a high speed, microprocessor-compatible, 8-bit analog-to-digital converter with a maximum
A throughput of 200kSPS. The converter operates off a single 2.7V to 5.5V supply and contains a 4.5µs
Unit max. A1 A2 A3 bp c D(1) E(1) e HE L LP Q v w y z(1) successive approximation A/D converter, track/hold circuitry, on-chip clock oscillator and 8-bit wide parallel
interface. The parallel interface is designed to allow easy interfacing to microprocessors and DSPs. Using
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.10 1.25
0.25
0.36 0.19 8.55 3.8
1.27
5.8
1.05
0.4 0.6
0.25 0.25 0.1
0.3 8°
only address decoding logic the AD7819 is easily mapped into the microprocessor address space.
0.0098 0.057 0.019 0.0098 0.35 0.16 0.24 0.039 0.028 0.028 0°
inches 0.069 0.0039 0.050 0.041 0.01 0.01 0.004 When used in its power-down mode, the AD7819 automatically powers down at the end of a conversion
0.049 0.01 0.014 0.0075 0.34 0.15 0.23 0.016 0.024 0.012
and powers up at the start of a new conversion. This feature significantly reduces the power consumption
NOTE : Plastic or metal protrusions of 0.15 mm maximum per side are not included.
of the part at lower throughput rates. The AD7819 can also operate in a high speed mode where the part is
not powered down between conversions. In this mode of operation the part is capable of providing 200
References kSPS throughput.
Outline European
Version Iec Jedec Eiaj Projection Issue Date
The part is available in a small, 16-lead 0.3" wide, plastic dual-in-line package (DIP); in a 6-lead, 0.15"
91-08-13 wide, narrow body small outline IC (SOIC) and in a 16-lead, narrow body, thin shrink small outline package
SOT108-1 076E06S MS-012AB 95-01-23 (TSSOP).

6 7
ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTION

VDD to DGND ..............................................................................................................................-0.3V to + 7V Pin No. Mnemonic Description

Digital Input Voltage to DGND 1 VREF Reference Input, 1.2V to VDD.
(CONVST, RD, CS) ...............................................................................................................-0.3V, VDD + 0.3V 2 VIN Analog Input, 0V to VREF.
Digital Output Voltage to DGND 3 GND Analog and Digital Ground.
(BUSY, DB0-DB7) .................................................................................................................-0.3V, VDD + 0.3V 4 CONVST Convert Start. A low-to-high transition on this pin initiates a 1.5 µs pulse on an
REFIN to AGND ......................................................................................................................-0.3V, VDD + 0.3V internally generated CONVST signal. A high-to-low transition on this line initiates the
Analog Input ..........................................................................................................................-0.3V, VDD + 0.3V conversion process if the internal CONVST signal is low. Depending on the signal on
this pin at the end of a conversion, the AD7819 automatically powers down.
Storage Temperature Range.................................................................................................-65 to + 150°C
Junction Temperature ........................................................................................................................... 150°C 5 CS Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs.
Plastic DIP Package, Power Dissipation .............................................................................................450mW 6 RD Read Pin. This is a logic input. When CS is low and RD goes low, the DB7-DB0 leave
JA Thermal Impedance...................................................................................................................105°C/W their high impedance state and data is driven onto the data bus.
Lead Temperature, (Soldering 10 sec)................................................................................................260°C 7 BUSY ADC Busy Signal. This is a logic output. This signal goes logic high during the
SOIC Package, Power Dissipation ......................................................................................................450mW conversion process.
JA Thermal Impedance .....................................................................................................................75°C/W 8-15 DB0-DB7 Data Bit 0 to 7. These outputs are three-state TTL-compatible.
Lead Temperature, Soldering 16 VDD Positive power supply voltage, 2.7V to 5.5V.
Vapor Phase (60 sec) ....................................................................................................................215°C
Infrared (15 sec)............................................................................................................................220°C
SSOP Package, Power Dissipation.....................................................................................................450mW PIN CONFIGURATION DIP/SOIC
JA Thermal Impedance ...................................................................................................................115°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) ....................................................................................................................215°C
Infrared (15 sec).............................................................................................................................220°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charge as high as 4000V

readily accumulate on the human body and test equipment and can discharge
Figure 1. Load Circuit for Digital Output Timing Specifications without detection. Although the AD7819 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges, Therefore, proper ESD precaution are recommended to avoid performance degradation or loss of
functionality.
ORDERING GUIDE

Model Linearity Error(LSB) Package Description Package Option

AD7819YN ± 1 LSB Plastic DIP N-16
AD7819YR ± 1 LSB Small Outline IC R-16A
AD7819YRU ± 1 LSB Thin Shark Small RU-16
Outline (TSSOP)
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

8 9
AK4524 24 bit 96kHz AUDIO CODEC BLOCK DIAGRAM

GENERAL DESCRIPTION

The AK4524 is a high performance 24bit CODEC for the 96kHz recording system. The ADC has an
Enhanced Dual Bit architecture with wide dynamic range. The DAC uses the new developed Advanced
Multi Bit architecture and achieves low outband noise and high jitter tolerance by use of SCF(switched
capacitor filter) techniques.The AK4524 has an input PGA and is well suited MD, DVTR system and
musical instruments.

FEATURES

• 24bit 2ch ADC

– 64x Oversampling
– Single-End inputs
– S/(N+D):90dB
– Dynamic Range, S/N:100dB
– Digital HPF for offset cancellation
– Input PGA with +8dB gain & 0.5dB step
– Input DATT with -72dB att
– I/F format:MSB justified or I2S

• 24bit 2ch DAC

– 128 x Oversampling
– 24bit 8 times Digital Filter
Ripple:±0.005dB, Attenuation:75dB
– SCF
– Differential Outputs
– S/(N+D):94dB
– Dynamic Range, S/N:110dB
– De-emphasis for 32kHz, 44.1kHz, 48kHz sampling ORDERING GUIDE
– Output DATT with -72dB att
– Soft Mute
AK4524VF -10~+70°C 28pin VSOP (0.65mm pitch)
– I/F format:MSB justified, LSB justified or l2S
AKD4524 Evaluation Board
• High Jitter Tolerance

• 3-wire Serial Interface for Volume Control PIN LAYOUT

• Master Clock
– X’tal Oscillating Circuit
– 256fs/384fs/768fs/1024fs

• Master Mode/Slave Mode

• 5V operation

• 3V Power Supply Pin for 3V I/F

• Small 28pin VSOP package

10 11
PACKAGZ ADSP-21065L DSP MICROCOMPUTER

SUMMARY

– High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and
Industrial Applications
– Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle
– 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-Point Arithmetic
– 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral
– I2S Support, for Eight Simultaneous Receive and Transmit Channels

KEY FEATURES

– 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance

– User-Configurable 544 Kbits On-Chip SRAM Memory
– Two External Port, DMA Channels and Eight Serial Port, DMA Channels
– SDRAM Controller for Glueless Interface to Low Cost External Memory (@66 MHz)
– 64M Words External Address Range
– 12 Programmable I/O Pins and Two Timers with Event Capture Options
– Code-Compatible with ADSP-2106x Family
– 208-Lead MQFP or 196-Ball Mini-BGA Package
– 3.3 Volt Operation

Flexible Data Formats and 40-Bit Extended Precision

– 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats
– 32-Bit Fixed-Point Data Format, Integer and Fractional, with Dual 80-Bit Accumulators
Note : Dimension “*” does not include moid flash.
Parallel Computations
– Single-Cycle Multiply and ALU Operations in Parallel with Dual Memory Read/Writes and Instruction
PACKAGE & LEAD FRAME MATERIAl Fetch
Package molding compound: Epoxy – Multiply with Add and Subtract for Accelerated FFT Butterfly Computation
Lead frame material: Cu – 1024-Point Complex FFT Benchmark: 0.274 ms (18,221 Cycles)
Lead frame surface treatment: Solder plate
544 Kbits Configurable On-Chip SRAM
– Dual-Ported for Independent Access by Core Processor and DMA
– Configurable in Combinations of 16-, 32-, 48-Bit Data and Program Words in Block 0 and Block 1

DMA Controller
– Ten DMA Channels–Two Dedicated to the External Port and Eight Dedicated to the Serial Ports
– Background DMA Transfers at up to 66 MHz, in Parallel with Full Speed Processor Execution
– Performs Transfers Between:
Internal RAM and Host
Internal RAM and Serial Ports
Internal RAM and Master or Slave SHARC
Internal RAM and External Memory or I/O Devices
External Memory and External Devices

Host Processor Interface

– Efficient Interface to 8-, 16-, and 32-Bit Microprocessors
– Host Can Directly Read/Write ADSP-21065L IOP Registers

12 13
Multiprocessing PIN DESCRIPTIONS
– Distributed On-Chip Bus Arbitration for Glueless, Parallel Bus Connect Between Two ADSP-21065Ls ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing
Plus Host requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as
– 132 Mbytes/s Transfer Rate Over Parallel Bus asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except for ADDR23-0, DATA31-0, FLAG11-0, SW, and
Serial Ports inputs that have internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and
– Independent Transmit and Receive Functions TDI)–these pins can be left floating. These pins have a logic-level hold circuit that prevents the input from
– Programmable 3-Bit to 32-Bit Serial Word Width floating internally.
– I2S Support Allowing Eight Transmit and Eight Receive Channels I=Input S=Synchronous P=Power Supply (O/D)=Open Drain
– Glueless Interface to Industry Standard Codecs O=Output A=Asynchronous G=Ground (A/D)=Active Drive
– TDM Multichannel Mode with µ-Law/A-Law Hardware Companding
T=Three-state (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
– Multichannel Signaling Protocol
Pin Type Function
BLOCK DIAGRAM ADDR23-0 I/O/T External Bus Address. The ADSP-21065L outputs addresses for external
memory and peripherals on these pins. In a multiprocessor system the bus
master outputs addresses for read/writes of the IOP registers of the other
ADSP-21065L. The ADSP-21065L inputs addresses when a host processor
or multiprocessing bus master is reading or writing its IOP registers.
DATA31-0 I/O/T External Bus Data. The ADSP-21065L inputs and outputs data and
instructions on these pins. The external data bus transfers 32-bit single-
precision floating-point data and 32-bit fixed-point data over bits 31-0. 16-bit
short word data is transferred over bits 15-0 of the bus. Pull-up resistors on
unused DATA pins are not necessary.
MS3-0 I/O/T Memory Select Lines. These lines are asserted as chip selects for the
corresponding banks of external memory. Internal ADDR25-24 are decoded
into MS3-0. The MS3-0 lines are decoded memory address lines that change
at the same time as the other address lines. When no external memory
access is occurring the MS3-0 lines are inactive; they are active, however,
when a conditional memory access instruction is executed, whether or not
the condition is true. Additionally, an MS3-0 line which is mapped to SDRAM
may be asserted even when no SDRAM access is active. In a
multiprocessor system, the MS3-0 lines are output by the bus master.
RD I/O/T Memory Read Strobe. This pin is asserted when the ADSP-21065L reads
from external memory devices or from the IOP register of another ADSP-
21065L. External devices (including another ADSP-21065L) must assert RD
to read from the ADSP-21065L’s IOP registers. In a multiprocessor system,
RD is output by the bus master and is input by another ADSP-21065L.
WR I/O/T Memory Write Strobe. This pin is asserted when the ADSP-21065L writes
to external memory devices or to the IOP register of another ADSP-21065L.
External devices must assert WR to write to the ADSP-21065L’s IOP
registers. In a multiprocessor system, WR is output by the bus master and is
input by the other ADSP-21065L.
SW I/O/T Synchronous Write Select. This signal interfaces the ADSP-21065L to
synchronous memory devices (including another ADSP-21065L). The
ADSP-21065L asserts SW to provide an early indication of an impending
write cycle, which can be aborted if WR is not later asserted (e.g., in a
conditional write instruction). In a multiprocessor system, SW is output by the
bus master and is input by the other ADSP-21065L to determine if the
multiprocessor access is a read or write. SW is asserted at the same time as
the address output.
ACK I/O/S Memory Acknowledge. External devices can deassert ACK to add wait
states to an external memory access. ACK is used by I/O devices, memory
controllers, or other peripherals to hold off completion of an external memory

14 15
Pin Type Function Pin Type Function
access. The ADSP-21065L deasserts ACK as an output to add wait states to access. The ADSP-21065L deasserts ACK as an output to add wait states to
a synchronous access of its IOP registers. In a multiprocessor system, a a synchronous access of its IOP registers. In a multiprocessor system, a
slave ADSP-21065L deasserts the bus master’s ACK input to add wait slave ADSP-21065L deasserts the bus master’s ACK input to add wait
state(s) to an access of its IOP registers. The bus master has a keeper latch state(s) to an access of its IOP registers. The bus master has a keeper latch
on its ACK pin that maintains the input at the level to which it was last driven. on its ACK pin that maintains the input at the level to which it was last driven.
SBTS I/S Suspend Bus Three-State. External devices can assert SBTS to place the SBTS I/S Suspend Bus Three-State. External devices can assert SBTS to place the
external bus address, data, selects, and strobes–but not SDRAM control external bus address, data, selects, and strobes–but not SDRAM control
pins–in a high impedance state for the following cycle. If the ADSP-21065L pins–in a high impedance state for the following cycle. If the ADSP-21065L
attempts to access external memory while SBTS is asserted, the processor attempts to access external memory while SBTS is asserted, the processor
will halt and the memory access will not finish until SBTS is deasserted. will halt and the memory access will not finish until SBTS is deasserted.
SBTS should only be used to recover from host processor/ADSP-21065L SBTS should only be used to recover from host processor/ADSP-21065L
deadlock. deadlock.
IRQ2-0 I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive. IRQ2-0 I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG11-0 I/O/A Flag Pins. Each is configured via control bits as either an input or an output. FLAG11-0 I/O/A Flag Pins. Each is configured via control bits as either an input or an output.
As an input, it can be tested as a condition. As an output, it can be used to As an input, it can be tested as a condition. As an output, it can be used to
signal external peripherals. signal external peripherals.
HBR I/A Host Bus Request. Must be asserted by a host processor to request control HBR I/A Host Bus Request. Must be asserted by a host processor to request control
of the ADSP-21065L’s external bus. When HBR is asserted in a of the ADSP-21065L’s external bus. When HBR is asserted in a
multiprocessing system, the ADSP-21065L that is bus master will relinquish multiprocessing system, the ADSP-21065L that is bus master will relinquish
the bus and assert HBG. To relinquish the bus, the ADSP-21065L places the the bus and assert HBG. To relinquish the bus, the ADSP-21065L places the
address, data, select, and strobe lines in a high impedance state. It does, address, data, select, and strobe lines in a high impedance state. It does,
however, continue to drive the SDRAM control pins. HBR has priority over all however, continue to drive the SDRAM control pins. HBR has priority over all
ADSP-21065L bus requests (BR2-1) in a multiprocessor system. ADSP-21065L bus requests (BR2-1) in a multiprocessor system.
HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the
host processor may take control of the external bus. HBG is asserted by the host processor may take control of the external bus. HBG is asserted by the
ADSP-21065L until HBR is released. In a multiprocessor system, HBG is ADSP-21065L until HBR is released. In a multiprocessor system, HBG is
output by the ADSP-21065L bus master. output by the ADSP-21065L bus master.
CS I/A Chip Select. Asserted by host processor to select the ADSP-21065L. CS I/A Chip Select. Asserted by host processor to select the ADSP-21065L.
REDY(O/D) O Host Bus Acknowledge. The ADSP-21065L deasserts REDY to add wait REDY(O/D) O Host Bus Acknowledge. The ADSP-21065L deasserts REDY to add wait
states to an asynchronous access of its internal memory or IOP registers by states to an asynchronous access of its internal memory or IOP registers by
a host. Open drain output (O/D) by default; can be programmed in ADREDY a host. Open drain output (O/D) by default; can be programmed in ADREDY
bit of SYSCON register to be active drive (A/D). REDY will only be output if bit of SYSCON register to be active drive (A/D). REDY will only be output if
the CS and HBR inputs are asserted. the CS and HBR inputs are asserted.
DMAR1 I/A DMA Request 1 (DMA Channel 9). DMAR1 I/A DMA Request 1 (DMA Channel 9).
DMAR2 I/A DMA Request 2 (DMA Channel 8). DMAR2 I/A DMA Request 2 (DMA Channel 8).
DMAG1 O/T DMA Grant 1 (DMA Channel 9). DMAG1 O/T DMA Grant 1 (DMA Channel 9).
DMAG2 O/T DMA Grant 2 (DMA Channel 8). DMAG2 O/T DMA Grant 2 (DMA Channel 8).
BR2-1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065L’s BR2-1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065L’s
to arbitrate for bus mastership. An ADSP-21065L drives its own BRx line to arbitrate for bus mastership. An ADSP-21065L drives its own BRx line
(corresponding to the value of its ID2-0 inputs) only and monitors all others. In (corresponding to the value of its ID2-0 inputs) only and monitors all others. In
a uniprocessor system, tie both BRx pins to VDD. a uniprocessor system, tie both BRx pins to VDD.
ID1-0 I Multiprocessing ID. Determines which multiprocessor bus request ID1-0 I Multiprocessing ID. Determines which multiprocessor bus request
(BR1–BR2) is used by ADSP-21065L. ID=01 corresponds to BR1, ID=10 (BR1–BR2) is used by ADSP-21065L. ID=01 corresponds to BR1, ID=10
corresponds to BR2. ID=00 in single-processor systems. These lines are a corresponds to BR2. ID=00 in single-processor systems. These lines are a
system configuration selection which should be hard-wired or changed only system configuration selection which should be hard-wired or changed only
at reset. at reset.
CPA (O/D) I/O Core Priority Access. Asserting its CPA pin allows the core processor of an CPA (O/D) I/O Core Priority Access. Asserting its CPA pin allows the core processor of an
ADSP-21065L bus slave to interrupt background DMA transfers and gain ADSP-21065L bus slave to interrupt background DMA transfers and gain

16 17
 Pin Type Function CLOCK SIGNALS
TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has
a 20kΩ internal pull-up resistor. The ADSP-21065L can use an external clock or a crystal. See CLKIN pin description. You can configure the
ADSP-21065L to use its internal clock generator by connecting the necessary components to CLKIN and
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDI has a 20kΩ internal pull-up resistor. XTAL. You can use either a crystal operating in the fundamental mode or a crystal operating at an overtone.
Figure shows the component connections used for a crystal operating in fundamental mode, and Figure 2
TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path. shows the component connections used for a crystal operating at an overtone.
TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-
21065L. TRST has a 20kΩ internal pull-up resistor.
EMU (O/D) O Emulation Status. Must be connected to the ADSP-21065L EZ-ICE target
board connector only.
BMSTR O Bus Master Output. In a multiprocessor system, indicates whether the
ADSP-21065L is current bus master of the shared external bus. The ADSP- SUGGESTED COMPONENTS FOR 30 MHz OPERATION:
SUGGESTED COMPONENTS FOR 30 MHz OPERATION:
21065L drives BMSTR high only while it is the bus master. In a single- ECLIPTEK EC2SM-33-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK EC2SM-T-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK ECT-30.000M (THRU-HOLE PACKAGE)
processor system (ID=00), the processor drives this pin high. ECLIPTEK EC-33-30.000M (THRU-HOLE PACKAGE) C1=18pF
C1=33pF C2=27pF
CAS I/O/T SDRAM Column Access Strobe. Provides the column address. In C2=27pF C3=75pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR L1=3300nH
conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10, X1. Rs=SEE NOTE.
defines the operation for the SDRAM to perform. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. NOTE: C1, C2, C3, Rs AND L1 ARE SPECIFIC TO CRYSTAL SPECIFIED
FOR X1.
RAS I/O/T SDRAM Row Access Strobe. Provides the row address. In conjunction with CONTACT MANUFACTURER FOR DETAILS.
CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation Figure 1. 30 MHz Operation (Fundamental Mode Crystal) Figure 2. 30 MHz Operation (3rd Overtone Crystal)
for the SDRAM to perform.
SDWE I/O/T SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx and TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
sometimes SDA10, defines the operation for the SDRAM to perform.
DQM O/T SDRAM Data Mask. In write mode, DQM has a latency of zero and is used The ADSP-2106x EZ-ICE emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x to
to block write operations. monitor and control the target board processor during emulation. The EZ-ICE probe requires the ADSP-
SDCLK1-0 I/O/S/T SDRAM 2x Clock Output. In systems with multiple SDRAM devices 2106x’s CLKIN, TMS, TCK, TRST, TDI, TDO, EMU and GND signals be made accessible on the target
connected in parallel, supports the corresponding increased clock load system via a 14-pin connector (a 2 row x 7 pin strip header) such as that shown in Figure 3. The EZ-ICE
requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or probe plugs directly onto this connector for chip-on-board emulation. You must add this connector to your
both SDCLKx pins can be three-stated. target board design if you, intend to use the ADSP-2106x EZ-ICE.

SDCKE I/O/T SDRAM Clock Enable. Enables and disables the CLK signal. For details, The total trace length between the EZ-ICE
see the data sheet supplied with your SDRAM device. connector and the furthest device sharing the EZ-
SDA10 O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with ICE JTAG pins should be limited to 15 inches
a host access. maximum for guaranteed operation. This restriction
on length must include EZ-ICE JTAG signals, which
XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the
ADSP-21065L’s internal clock generator or to disable it to use an external are routed to one or more 2106x devices or to a
clock source. See CLKIN. combination of 2106xs and other JTAG devices on
the chain.
PWM_EVENT1-0 I/O/A PWM Output/Event Capture. In PWMOUT mode, is an output pin and
functions as a timer counter. In WIDTH_CNT mode, is an input pin and The 14-pin, 2-row pin strip header is keyed at the
functions as a pulse counter/event capture. Pin 3 location–you must remove Pin 3 from the
VDD P Power Supply; nominally +3.3V dc. (33 pins) header. The pins must be 0.025 inch square and at
least 0.20 inch in length. Pin spacing should be
GND G Power Supply Return. (37 pins)
0.1x0.1 inches. Pin strip headers are available from
NC Do Not Connect. Reserved pins that must be left open and unconnected. (7) vendors such as 3M, McKenzie and Samtec.

Figure 3. Target Board Connector for ADSP-2106x

EZ-ICE (JTAG Header)

18 19
208-LEAD MQFP PIN CONFIGURATION 208-LEAD MQFP PIN

Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
No. Name No. Name No. Name No. Name No. Name
1 VDD 43 CAS 85 VDD 127 DATA28 169 ADDR17
2 RFS0 44 SDWE 86 DATA3 128 DATA29 170 ADDR16
3 GND 45 VDD 87 DATA4 129 GND 171 ADDR15
4 RCLK0 46 DQM 88 DATA5 130 VDD 172 VDD
5 DR0A 47 SDCKE 89 GND 131 VDD 173 ADDR14
6 DR0B 48 SDA10 90 DATA6 132 DATA30 174 ADDR13
7 TFS0 49 GND 91 DATA7 133 DATA31 175 ADDR12
8 TCLK0 50 DMAG1 92 DATA8 134 FLAG7 176 VDD
9 VDD 51 DMAG2 93 VDD 135 GND 177 GND
10 GND 52 HBG 94 GND 136 FLAG6 178 ADDR11
11 DT0A 53 BMSTR 95 VDD 137 FLAG5 179 ADDR10
12 DT0B 54 VDD 96 DATA9 138 FLAG4 180 ADDR9
13 RFS1 55 CS 97 DATA10 139 GND 181 GND
14 GND 56 SBTS 98 DATA11 140 VDD 182 VDD
15 RCLK1 57 GND 99 GND 141 VDD 183 ADDR8
16 DR1A 58 WR 100 DATA12 142 NC 184 ADDR7
17 DR1B 59 RD 101 DATA13 143 ID1 185 ADDR6
18 TFS1 60 GND 102 NC 144 ID0 186 GND
19 TCLK1 61 VDD 103 NC 145 EMU 187 GND
20 VDD 62 GND 104 DATA14 146 TDO 188 ADDR5
21 VDD 63 REDY 105 VDD 147 TRST 189 ADDR4
22 DT1A 64 SW 106 GND 148 TDI 190 ADDR3
23 DT1B 65 CPA 107 DATA15 149 TMS 191 VDD
24 PWM_EVENT1 66 VDD 108 DATA16 150 GND 192 VDD
25 GND 67 VDD 109 DATA17 151 TCK 193 ADDR2
26 PWM_EVENT0 68 GND 110 VDD 152 BSEL 194 ADDR1
27 BR1 69 ACK 111 DATA18 153 BMS 195 ADDR0
28 BR2 70 MS0 112 DATA19 154 GND 196 GND
29 VDD 71 MS1 113 DATA20 155 GND 197 FLAG0
30 CLKIN 72 GND 114 GND 156 VDD 198 FLAG1
31 XTAL 73 GND 115 NC 157 RESET 199 FLAG2
32 VDD 74 MS2 116 DATA21 158 VDD 200 VDD
33 GND 75 MS3 117 DATA22 159 GND 201 FLAG3
34 SDCLK1 76 FLAG11 118 DATA23 160 ADDR23 202 NC
35 GND 77 VDD 119 GND 161 ADDR22 203 NC
36 VDD 78 FLAG10 120 VDD 162 ADDR21 204 GND
37 SDCLK0 79 FLAG9 121 DATA24 163 VDD 205 IRQ0
38 DMAR1 80 FLAG8 122 DATA25 164 ADDR20 206 IRQ1
39 DMAR2 81 GND 123 DATA26 165 ADDR19 207 IRQ2
40 HBR 82 DATA0 124 VDD 166 ADDR18 208 NC
41 GND 83 DATA1 125 GND 167 GND
42 RAS 84 DATA2 126 DATA27 168 GND

20 21
SPECIFICATIONS ELECTRICAL PARTS LIST

Ref No. Part No. Description Value Ref No. Part No. Description Value
ELECTRICAL AC INPUT B'D (4003482620) C427 3509101130-T CAP CE SL 100PF 50V J 100p
C433-436 3689103219 CAP X7R 10N 10% 50V (LS5.08) 10n
C402-403 3549222091 CAP DE7100F 222MVAI-KC 2.2n/250 C428 C432 3689102219 CAP X7R 1N 10% 50V (LS5.08) 1n
• ANALOG INPUT C404-405 3549472092 CAP DE7100F472MVAI-KC 4.7n/250 C310-317 3509331130-T CAP CE SL 330PF 50V J 330P
TR301 2658399940 COMON MODE CHOKE COIL MEQ-2000 CHOKE COIL CN401-402 4428595005 LW5267/LWB0640/2.5MM-05P WAFER 5P
XLR & 1/4˝ TRS, Electronically Balanced, RF Filtered, and fully unbalanced compatible P1 P3 P14 P27 4465998210 TERMINAL(250)PCB TAB TERMINAL CN305 CN403 CN405 4428595002 LW5267/LWB0640/2.5MM-02P WAFER 2P
Impedance .......................................................................................................................................>10kΩ 4458999110 FUSE CLIP 5*20 FUSE CLIP CN301-304 CN406 4428595003 LW5267/LWB0640/2.5MM-07P WAFER 3P
CN404 4428595007 CON WAFER A2505WV2-07P WAFER 7P
Maximal Input Level .........................................................................................................................20dBu FRONT B'D:GEQ-2231D (4003482400) F402 3908609980 EMI FILTER 2200PF 22nF
IC115-116 S21225165401 IC 74LCX 138(SOP16)PHI 74LCX138 D301-302 D401-402 2058100996 DIODE RECTIFIER LT1N4006(4007) 1N 4006
• ANALOG OUTPUT C110-140 C142-197
S35101045039 CAP X7R 100N 10% 63V 2012 100n
D405 D406
C202-207 C209-211 D407 2058304100 DIODE IN4148M 1N 4148
XLR & 1/4˝ TRS, Electronically Balanced, RF Filtered and fully unbalanced compatible C101-102 S35102204321 CAP CL 22PF 50V J 1608 22p D403-404 2058100890 DIODE RECTIFIER IN5401 1N5401
Impedance ......................................................................................................................................< 100Ω F101 S39006999944 EMI NFM60(SMD) NFM60R C426 3409210033-T CAP E SE 10UF 16V 4*5 10/16
C201 C208 S34121000422 CAP RC 10UF 16V 10u C430-431 3409210059-T CAP RG 10UF 50V 105C 10/50
Maximum Output Level @ > 600Ω ...................................................................................................20dBu IC106-114 S21225160201 IC 74HC4051 SOIC 74HC4051 C414-415 C424 3408210233 CAP RSD 1000UF 16V SNAP 10P 1000/16
DIP Switch Selectable Output Attenuator in 3dB Steps ...................20dBu to 2dBu and Unity-Gain Mode IC101-105 IC120 S21224147701 IC 74LV164 SOT108-1 74LVC164 C410-411 3419533265 CAP HC 3300UF 35V 3300/35
D101-103 D142 S22400502001 DIODE BAW56 SOT23 BAW56 C422 3419568238 CAP AF HM 6800UF 16V 25P LUG 6800/16
D6 D8-13 D104-111 FB301-308 2648609900 FERITE BEAD H5B FERRITE
• GRAPHIC EQUALIZER D120-122 D128 D140
2309770100 LED BL-S4548-TBS22A 1.8MM LED1.8MM
FS401 0.125A/250V
31-Band 1/3-Octave Interpolating Constant-Q Filter Bank D116-117 D132-133 2300031100 LED LTL-1CHY LITEON LED3MM-YELLOW FS402-403 5508212233 FUSE NB 20MM 1A/250V U/C 1AT
D14 D113 D123-124 FS404 4458999110 FUSE CLIP 5*20 FUSE CLIP
Selectable Boost/Cut Range ..........................±12dB/ ±6dB and 0 to -12dB/ 0 to -6dB (in Cut Only mode) D114 D129-131 2300032100 LED LTL-1CHG LITEON LED3MM-GREEN JX302 JX304 4408194510 XLR JACK (F) (E303A0070N) XLR JACK (F)
Input Gain Control .....................................................................................................................0 to +18dB D115 D141 JX301 JX303 4408194610 XLR JACK (M) (E403A0090N) XLR JACK (M)
D126-127 D118-119 2300030000 LED LTL-1CHEE LITEON LED3MM-RED JK301-304 4408194210 XLR JACK(M) E503A0130N JACK PHONE
6-LED Input Level Meter ..................................-40dBu, -24dBu, -15dBu, -8dBu,- 3dBu, Peak (> +18dBu) D112 D125 IC405 2168640979 IC LM311N (DIL8) FSC LM311N
R102 R133 30101017121 RES TF 100 1/16W 1608 100 IC402 2168640987 IC 7915 SAMSUNG 7915
• CUT FILTERS R104-119 R211-221
30101517121 RES TF 150 1/16W 1608 150
IC404 2118089926 IC LM 350T LM350T
R223-225 R240-242 48
Low-Cut Frequency Range .................................................................................................12.5Hz~200Hz R101 R103 CN407 4235007210 GND TERMINAL (POWER B'D) GND TERMINAL
Low-Cut Slope .....................................................................................................18dB/octave Butterworth R135-158 R165-210 30101027121 RES TF 1K 1/16W 1608 1K P32 P36 P38-39
R230 R243 P41-42
High-Cut Frequency Range ..............................................................................................3.3kHz~29.5kHz T101-108 4628980110 PUSH SWITCH PUSH S/W P401-404 4465998210 TERMINAL(250)PCB TAB TERMINAL TAB
High-Cut Slope ....................................................................................................18dB/octave Butterworth Q101-103 S20510482001 TR MMBT4124 SOT-23 mmBT4124 JP1-2
SVR101-116 JP301-304 4428590423 PIN HEADER 2X3POL (LS2.54) pinheader 3p
SVR119-132 3238010324 VR RS20111D6 10KB ALP SVR 10KB PT1 PT
• PEAK-LIMITER SVR134-167 R408 3004100953 RES CF 100 1/5W FN SMA-4000 100 1%
Type ......................................................................................................................Maximizer with Soft Clip SVR168-173 3208010324 VR RK09K11330CC9 10KB ALP VR 10KB R403 R418 3001100953 RES CF 100K 1/5W F N 100K 1%
J101 S44410510626 CON FFC/FPC 26P ZIP ANGLE CON 26P R417 R425 3005100953 RES CF 10 1/5W F N 10 1%
Threshold ..................................................................................................................................0 to 19dBu 4355735800 FLAT CABLE 1.0 140MM 26P ASS'Y R420 3002150953 RES CF 15K 1/5W F N 15K 1%
3-LED Gain Reduction Meter .......................................................................................................1, 3, 6dB FRONT B'D:GEQ-1231D (400382500)
R423 3003220953 RES CF 2.2K 1/5W F N 2.2K
R409 3003274953 RES CF 2.7K 1/5W F N 2.7K 1%
Output Clip Indicator ...................................................................................................................> +19dBu IC110 S21225165401 IC 74LCX 138M (SOP16) FSC 74LCX138 R410-411 R416 R419 3002220953 RES CF 22K 1/5W F N 22K 1%
Limiter Link (GEQ-2231D only) .....................................................................................................ON/OFF C108-112 C117-156 R421
S35101045039 CAP X7R 100N 10% 63V 2012 100n
C158-161 C163 R404 3003330953 RES CF 3.3K 1/5W F N 3.3K 1%
Channel Link (GEQ-2231D only) ..................................................................................................ON/OFF C100-101 S35102204321 CAP CL 22PF 50V J 1608 22p R406 3003348953 RES CF 3.48K 1/5W FN SMA-4000 3.48K 1%
F101 S39006999944 EMI NFM60(SMD) NFM60R R401 3004390953 RES CF 390 1/5W FN 390 1%
• SYSTEM PERFORMANCE J101 S44410510626 CON FFC/FPC 26P ZIP ANGLE WAFER 26P R402 3004240953 RES CF 240 1/5W FN 240 1%
C157 C162 S34121000632 CAP RC 10UF 25V 10u R413 3003470953 RES CF 4.7K 1/5W F N 4.7K 1%
Frequency Response (-0.5dB) ............................................................................................10Hz~31.5kHz IC105-109 S21225160201 IC 74HC4051 SOIC 74HC4051 R407 3002470953 RES CF 47K 1/5W F N 47K 1%
IC101-103 S21224147701 IC 74LV164 SOT108-1 74LV164 R415 3004470953 RES 470 1/5W FN 470 1%
Dynamic Range .......................................................................................................................... > 95dB-A D117-118 S22400502001 DIODE BAW56 SOT-23 BAW56 R405 3009564973 RES CF 560K 1/5W J N 560K
THD+N ........................................................................................................................................< 0.003% D1-3 D100-102 S20510482001 LED BL-S4548-TBS22A 1.8MM LED1.8MM RLY301-302 5528007800 RELAY AZ850-12 DC12V RELAY DC12V
D103-104 D110-112 2300032100 LED LTL-1CHG LITEON LED3MM-GREEN SW301-302 4625995510 SW SLIDE SSAF122NB011(9MM) SW SLIDE(9MM)
D109 D105-107 S401 4648099310 POWER SWITCH (H8500VB) POWER SW
GENERAL D115-116
2300030000 LED LTL-1CHEE LITEON LED3MM-RED
IC406 2128612400 IC TL431CLP (TO92) TIA TL431
D113-114 2300031100 LED LTL-1CHY LITEON LED3MM-YELLOW Q401-402 2008405980-T KRA103M-AT KRC103M
R118 R155 S30101017121 RES TF 100 1/16W 1608 100
• Power Source .....................................................................................AC 100V/120V/230V/240V, 50/60Hz R101-116 S30101517121 RES TF 150 1/16W 1608 150 SHT B'D (4003482700)
R100 R123-154 IC605 S21281169601 IC AD7819 8BIT SAMPLING ADC AD7819
• Power Consumption ..............................................................................................................................10W R157-160
S30101027121 RES TF 1K 1/16W 1608
2IC620-621 S22300502001 DIODE BAT54S SOT-23 BAT54S
• Weight ............................................................................................................................GEQ-1231D: 3.5kg T101-103 4628980110 PUSH SWITCH PUSH S/W C529-530 C535-536
Q101 S20510482001 TR MMBT4124 SOT-23 mmBT4124 C538-542 C545-549
........................................................................................................................................GEQ-2231D: 5.0kg SVR101-132 3238010324 VR RS20111D6 10KB SVR 10KB C606-630 C650-651 S35101045039 CAP X7R 100N 10% 63V 2012 100n
• Dimensions ...........................................................GEQ-1231D (1HU Rack): 482(W) 44(H) 280(D) mm SVR133-135 3208010324 VR RK09K11330CC9 10KB VR 10KB C655-659 C670-677
J101 S44410510626 CON FFC/FPC 26P ZIP ANGLE CON 26P C683-684
.............................................................................. GEQ-2231D (2HU Rack): 482(W) 88(H) 280(D) mm 4355735900 FLAT CABLE 1.0 80MM 26P ASS'Y C654 S35101025039 CAP NPO 1N 10% 63V 2012 1N
C505 C507 C510 C512 S35101014331 CAP CE C 100PF 50V J 0805(2012) 100P NPO
DIP S/W B'D (4003481200) C531-532 S35201005020 CAP NPO 10p 10% 63V SMD 10p NPO
* Due to continuous improvements specifications and design are subject to change without prior notice. DS701 4698099610 SW DIP 4 WAY JEC DIP SW C601-603 S35102204339 CAP CL 22PF 50V J 2012 22P
4355738616 CON ASS'Y 5P 360MM ASS'Y C604 S35102704321 CAP CE C 27PF 50V J 0603(1608) 27P
C525-526 C551-552 S35203314030 CAP NPO 330P 5% 50V 2012 330P
POWER/IN-OUT B'D (4003482600) C503-504 C513-514
IC401 2168640988 IC 7815 SAMSUNG 7815 C524 C527 C550 S35203324030 CAP NPO 3.3N 5% 50V 2012 3.3N
AC101 4308991810 AC CORD DOM 12A INLET AC INPUT C553 C506 C511
BD401 2058100976 DIODE BRIDGE KBP202G/KBP203G KBP02 C518-521 C556-559 S35103304321 CAP CL 33PF 50V J 1608 33P
C301-303 C307-309 3609104120-T CAP MA 0.1UF 100V J 0.1u C605
C412-413 C416-417 3689104219 CAP X7R 100N 10% 63V (LS5.08) 100n CN501 CN503-506 4428595003 LW5267/LWB0640/2.5MM-03P WAFER 3P
C423 C425 C429 CN502 4428595007 LW5267/LWB0640/2.5MM-07P CON / 7P

22 23
 TOP AND BOTTOM VIEW OF P.C BOARD

Ref No. Part No. Description Value

F601-604 S39006999944 EMI NFM60(SMD) NFM60R
J603 4428592510 WAFER BOX TPHB03-1419-10A WAFER 10P
J602 4428592520 WAFER BOX TPHB03-1419-20A WAFER 20P
J101 S4410510626 CON FFC/FPC 26P ZIP ANGLE WAFER 26P
S601 4428590807 PIN HEADER 2X7PIN 2*7 pin header
X602 3938000860 CRYSTAL 24.576MHz (ATS-49U) 24.576MHz
X601 3938000830 CRYSTAL 33MHz (ATS-49U) 33MHz
C528 C534
C543-544 C561
S34121000422 CAP RC 10UF 16V
C652-653 C685-687 10 / 16
C689
C517 C522 C555
3409210149-T CAP RG 100UF 25V 105C 100 / 25
C560
C537 S34114700232 CAP SC 47UF 6.3V SAMWHA 47 / 6.3
C680-682 S34104700642 CAP SC 47UF 25V SAMWHA 47 / 25
C501-502 C508-509
C515-516 C523 3409247041-T CAP AF RSG 47UF 25V 5 P 47 / 25
C554
IC607 S21229069401 IC DS2401P(TSOC)DALLAS DS2401
IC602 S21235328101 SST28VF040A-200-4C-NH FALSH ROM
IC604 S21210009801 IC ALG265QL 4009 ROUTER TQFP100 QL4009
IC608 S21102030402 IC NJM78L05UA-TE1 JRC 78I05
IC603 S21243862501 IC K4S64323C-TC/L70 SRAM
IC606 S21265055402 IC TPS3801(SOT-323) TIA TPS3801
IC601 S21213009601 IC ADSP21065LKS-264 66MH ADI adsp 21065
IC614 S21286282701 IC AKM4524 24BIT 96kHz CODEC AKM4524
IC609 IC611-613 S21101083204 IC NJM 5532 DMP-8 JRC 5532DD
J3 J5 S30100007231 RES TF 0 1/10W 2012 0
R614 R628-630 S30100007121 RES TF 0 1/16W 1608 0
R503-504 R523-524 S30331505121 RES MF 1.5K F 1/16W 1608 1.5K 1%
R658 R680-681 S30101017231 RES TF 100 1/10W 2012 100
R501-502 R525-528
S30311005121 RES MF 100K 1/16W 1608 100K 1%
R573-574
R548-550 R615
R617-619 R625-627
S30101037121 RES TF 10K 1/16W 1608 10K
R652 R671-673
R607-609
R536 R565 S303320110120 RES MF 18.7K F 1608 18.7K 1%
R670 S30101007121 RES TF 10 1/16W 1608 10
R507-512 R515-520
R532-533 R539-540 S30333305121 RES MF 3.3K F 1/16 1608 3.3K 1%
R561-562 R568-569
R543-544 R557-558 S30336345120 RES MF 6.34K F 1608 6.34K 1%
R551-554 R650-651
R654-657
S30103907121 RES TF 39 1/16W 1608 39
R610-613 R616
R620-623 R601-606
R513-514 R529
S30104707121 RES MF 47 1/16W 1608 47
R538 R563 R572
R547 S30104797121 RES TF 4.7 1/16W 1608 4.7
R530-531 R534-535
S30318255120 RES MF 8.25K F 1608 8.25K 1%
R566-567 R570
R537 R564 S30321025120 RES MF 10.2K F 1608 10.2K1%
R541 R545 R556 S30318255120 RES MF 768 F 1608 768 1%
R560 4.7
R542 R546 R555
R559 S30332110120 RES MF 11K F1608 11K 1%
R505-506 R521-522
D601 2308660126 LED TLM-2100 RED SOT-23 (SMD) TLM2100
T601-602 4628988710 SW TACT THHV501BAA SW TACT
S44410013632 SOCKET IC PLCC 32 (SMD) SOCKET
4408194800 CON JUMP CON JMP
CN508 4428595005 LW5267/LWB0640/2.5MM-05P WAFER 5P

24 25
26 27
28 29
WIRING DIAGRAM BLOCK DIAGRAM

30 31
32
SCHEMATIC DIAGRAM

GEQ - 1231D
FRONT B D

33 34
GEQ - 2231D
FRONT B D 1/2

35 36
GEQ - 2231D
FRONT B D 2/2

37 38
IN/OUT B D

39 40
POWER B D

41 42
SHT B D 1/4

43 44
SHT B D 2/4

45 46
SHT B D 3/4

47 48
SHT B D 4/4

49 50
EXPLODED CIEW OF CABINET & CHASSIS / MACHANICAL PARTS LIST

51 52
53 54
ASS’Y DRAWING

55 56
57 58
NOTE