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pahujahimankArithmetic Operations Algorithm and Hardware
Addition and Subtraction :
Addition and Subtraction with Signed –Magnitude Data
We designate the magnitude of the two numbers by A and B.
Where the signed numbers are added or subtracted, we find that there are eight different
conditions to consider, depending on the sign of the numbers and the operation
performed.
These conditions are listed in the first column of given Table.
The other columns in the table show the actual operation to be performed with the
magnitude of the numbers. The last column is needed to present a negative zero.
In other words, when two equal numbers are subtracted, the result should be +0 not -0.
The algorithms for addition and subtraction are derived from the table and can be stated
as follows (the words parentheses should be used for the subtraction algorithm)
Algorithm: -
The flowchart is shown in Figure. The two signs A, and B, are compared by an exclusive-OR
gate.
If the output of the gate is 0 the signs are identical; If it is 1, the signs are different.
For an add operation, identical signs dictate that the magnitudes be added. For a subtract
operation, different signs dictate that the magnitudes be added.
The magnitudes are added with a microoperation EA A + B, where EA is a register that combines
E and A. The carry in E after the addition constitutes an overflow if it is equal to 1. The value of
E is transferred into the add-overflow flip-flop AVF.
The two magnitudes are subtracted if the signs are different for an add operation or identical for a
subtract operation. The magnitudes are subtracted by adding A to the 2's complemented B. No
overflow can occur if the numbers are subtracted so AVF is cleared to 0.
1 in E indicates that A >= B and the number in A is the correct result. If this numbs is zero, the
sign A must be made positive to avoid a negative zero.
0 in E indicates that A < B. For this case it is necessary to take the 2's complement of the value in
A. The operation can be done with one microoperation A A' +1.
However, we assume that the A register has circuits for microoperations complement and
increment, so the 2's complement is obtained from these two microoperations.
In other paths of the flowchart, the sign of the result is the same as the sign of A. so no change in
A is required. However, when A < B, the sign of the result is the complement of the original sign
of A. It is then necessary to complement A, to obtain the correct sign.
The final result is found in register A and its sign in As. The value in AVF provides an overflow
indication. The final value of E is immaterial.
Figure below shows a block diagram of the hardware for implementing the addition and
subtraction operations.
It consists of registers A and B and sign flip-flops As and Bs.
Subtraction is done by adding A to the 2's complement of B.
The output carry is transferred to flip-flop E , where it can be checked to determine the relative
magnitudes of two numbers.
The add-overflow flip-flop AVF holds the overflow bit when A and B are added.
The A register provides other microoperations that may be needed when we specify the sequence
of steps in the algorithm.
Flowchart for add and subtract operations
Addition and Subtraction with -2's Complement Data
Multiplication Algorithm:-
In the beginning, the multiplicand is in B and the multiplier in Q.
Their corresponding signs are in Bs and Qs respectively.
We compare the signs of both A and Q and set to corresponding sign of the product since
a double-length product will be stored in registers A and Q.
Registers A and E are cleared and the sequence counter SC is set to the number of bits of
the multiplier.
Since an operand must be stored with its sign, one bit of the word will be occupied by the
sign and the magnitude will consist of n-1 bits.
Now, the low order bit of the multiplier in Qn is tested. If it is 1, the multiplicand (B) is
added to present partial product (A), 0 otherwise.
Register EAQ is then shifted once to the right to form the new partial product.
The sequence counter is decremented by 1 and its new value checked.
If it is not equal to zero, the process is repeated and a new partial product is formed.
When SC = 0 we stops the process.
Hardware Implementation
Hardware Multiplication Algorithm:-
Hardware Booth Algorithm and Hardware Implementation For Booth Algorithm
Division Algorithms
Division of two fixed-point binary numbers in signed magnitude representation is performed
with paper and pencil by a process of successive compare, shift and subtract operations.
Binary division is much simpler than decimal division because here the quotient digits are
either 0 or 1 and there is no need to estimate how many times the dividend or partial
remainder fits into the divisor.
The division process is described in Figure
The devisor is compared with the five most significant bits of the dividend.
Since the 5-bit number is smaller than B, we again repeat the same process.
Now the 6-bit number is greater than B, so we place a 1 for the quotient bit in the sixth
position above the dividend.
Now we shift the divisor once to the right and subtract it from the dividend.
The difference is known as a partial remainder because the division could have stopped here
to obtain a quotient of 1 and a remainder equal to the partial remainder.
Comparing a partial remainder with the divisor continues the process.
If the partial remainder is greater than or equal to the divisor, the quotient bit is equal to 1.
The divisor is then shifted right and subtracted from the partial remainder.
If the partial remainder is smaller than the divisor, the quotient bit is 0 and no subtraction is
needed.
The divisor is shifted once to the right in any case.
Obviously the result gives both a quotient and a remainder.
Hardware Implementation for Signed-Magnitude Data
In hardware implementation for signed-magnitude data in a digital computer, it is convenient
to change the process slightly.
Instead of shifting the divisor to the right, two dividends, or partial remainders, are shifted to
the left, thus leaving the two numbers in the required relative position.
Subtraction is achieved by adding A to the 2's complement of B.
End carry gives the information about the relative magnitudes.
The hardware required is identical to that of multiplication.
Register EAQ is now shifted to the left with 0 inserted into Qn and the previous value of E is
lost.
The example is given in Figure to clear the proposed division process.
The divisor is stored in the B register and the double-length dividend is stored in registers A
and Q.
The dividend is shifted to the left and the divisor is subtracted by adding its 2's complement
value.
