Computer Instructions

Computer instructions are a set of machine language instructions that a particular

processor understands and executes. A computer performs tasks on the basis of the
instruction provided.

An instruction comprises of groups called fields. These fields include:

o The Operation code (Opcode) field which specifies the operation to be

performed.
o The Address field which contains the location of the operand, i.e., register or
memory location.
o The Mode field which specifies how the operand will be located.

A basic computer has three instruction code formats which are:

1. Memory - reference instruction

2. Register - reference instruction
3. Input-Output instruction

Memory - reference instruction

In Memory-reference instruction, 12 bits of memory is used to specify an address and

one bit to specify the addressing mode 'I'.

Register - reference instruction

The Register-reference instructions are represented by the Opcode 111 with a 0 in the
leftmost bit (bit 15) of the instruction.

Note: The Operation code (Opcode) of an instruction refers to a group of bits that define
arithmetic and logic operations such as add, subtract, multiply, shift, and compliment.

A Register-reference instruction specifies an operation on or a test of the AC

(Accumulator) register.

Input-Output instruction

Just like the Register-reference instruction, an Input-Output instruction does not need a
reference to memory and is recognized by the operation code 111 with a 1 in the
leftmost bit of the instruction. The remaining 12 bits are used to specify the type of the
input-output operation or test performed.

Note

o The three operation code bits in positions 12 through 14 should be equal to 111.
Otherwise, the instruction is a memory-reference type, and the bit in position 15
is taken as the addressing mode I.
o When the three operation code bits are equal to 111, control unit inspects the bit
in position 15. If the bit is 0, the instruction is a register-reference type.
Otherwise, the instruction is an input-output type having bit 1 at position 15.

Instruction Set Completeness

A set of instructions is said to be complete if the computer includes a sufficient number
of instructions in each of the following categories:

o Arithmetic, logical and shift instructions

o A set of instructions for moving information to and from memory and processor
registers.
o Instructions which controls the program together with instructions that check
status conditions.
o Input and Output instructions

Arithmetic, logic and shift instructions provide computational capabilities for processing
the type of data the user may wish to employ.

A huge amount of binary information is stored in the memory unit, but all computations
are done in processor registers. Therefore, one must possess the capability of moving
information between these two units.

Program control instructions such as branch instructions are used change the sequence
in which the program is executed.

Input and Output instructions act as an interface between the computer and the user.
Programs and data must be transferred into memory, and the results of computations
must be transferred back to the user.
Instruction Formats (Zero, One, Two and
Three Address Instruction)
A computer performs a task based on the instruction provided. Instruction in
computers comprises groups called fields. These fields contain different
information as for computers everything is in 0 and 1 so each field has different
significance based on which a CPU decides what to perform. The most
common fields are:
 Operation field specifies the operation to be performed like addition.
 Address field which contains the location of the operand, i.e., register or
memory location.
 Mode field which specifies how operand is to be founded.
Instruction is of variable length depending upon the number of addresses it
contains. Generally, CPU organization is of three types based on the number of
address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization
In the first organization, the operation is done involving a special register called
the accumulator. In second on multiple registers are used for the computation
purpose. In the third organization the work on stack basis operation due to
which it does not contain any address field. Only a single organization doesn’t
need to be applied, a blend of various organizations is mostly what we see
generally.
Based on the number of address, instructions are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.

1. Zero Address Instructions –

A stack-based computer does not use the address field in the instruction. To
evaluate an expression first it is converted to reverse Polish Notation i.e. Postfix
Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

2 .One Address Instructions –

This uses an implied ACCUMULATOR register for data manipulation. One
operand is in the accumulator and the other is in the register or memory
location. Implied means that the CPU already knows that one operand is in the
accumulator so there is no need to specify it.

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

3.Two Address Instructions –

This is common in commercial computers. Here two addresses can be specified
in the instruction. Unlike earlier in one address instruction, the result was stored
in the accumulator, here the result can be stored at different locations rather
than just accumulators, but require more number of bit to represent address.

Here destination address can also contain operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

4.Three Address Instructions –

This has three address field to specify a register or a memory location. Program
created are much short in size but number of bits per instruction increase.
These instructions make creation of program much easier but it does not mean
that program will run much faster because now instruction only contain more
information but each micro operation (changing content of register, loading
address in address bus etc.) will be performed in one cycle only.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

 Instruction Cycle Definition
The processing involved in the execution of a single instruction is termed as
Instruction Cycle. This processing is done in two steps i.e. fetch and execute.
To execute an instruction the processor first reads an instruction from the
memory which is called fetching and then the fetched instruction is executed.

If we discuss the basic structure it includes the following two cycles:

 Fetch cycle: In this cycle, the processor reads the instruction that is to be
executed from the memory.
 Execute cycle: In this cycle, the processor interprets the opcode of the fetched
instruction and performs the operations accordingly.

The figure below shows you the processing of the basic instruction cycle. In
the beginning, to start the execution of a program, the processor runs the
fetch cycle and fetches the first instruction from the memory. The execution
cycle interprets the operation and performs the operations specified in the
instruction accordingly.

This cycle repeats until all the instructions are executed from the program and
after the execution of the last instruction the instruction cycle get halt. So, this
was the scenario where there were no interrupts.
Interrupt Cycle
To accommodate the occurrence of interrupts the interrupt cycle must be
added to amend the structure of the instruction cycle. As in the figure below
you can see the interrupt cycle has been added to the basic instruction cycle.

Consider the condition that the interrupts are enabled. In this case, if an
interrupt occurs then the processor halt the execution of the current program.
Thereby it saves the address of the instruction that has to be executed next
and service the occurred interrupt.

To process the interrupts the processor set the program counter with starting
address of the interrupt service routine. This would let the processor fetch the
first instruction of interrupt service routine and service the occurred interrupt.
Once the interrupt is serviced the processor resumes back to the execution of
the program it has halted to service the interrupt. It set the program counter
with the address of the next instruction to be executed.

If the interrupts are disabled then the processor will simply ignore the
occurrence of interrupts. The processor will smoothly execute the currently
running program and will check the pending interrupts once the interrupts are
enabled.

Indirect Cycle
An instruction may have one or more than one operands. To operate these
operands its value is accessed from the memory. So, to execute the
instructions with operands we require memory access. Now, what if indirect
addressing is used?

Additional memory access is required if indirect addressing is used in the

instructions. This adds one more stage or cycle to the basic instruction cycle.
Basically, the instruction fetch and instruction execute cycle occurs
alternatively.

The fetched instruction is checked for indirect addressing. If indirect

addressing is present the operands are fetched by performing an indirect
cycle. And if there occurs an interrupt it is processed before the execution of
the next instruction.
Execution of a complete instruction
As instructions are a part of the program which are stored inside the memory,
so every time the processor requires to execute an instruction, for that the
processor first fetches the instruction from the memory, then decodes the
instruction and then executes the instruction. The whole process is known as an
instruction cycle.

Instruction cycle state transition diagram

Instruction execution :
Instruction execution needs the following steps, which are
 PC (program counter) register of the processor gives the address of the
instruction which needs to be fetched from the memory.
 If the instruction is fetched then, the instruction opcode is decoded. On
decoding, the processor identifies the number of operands. If there is any
operand to be fetched from the memory, then that operand address is
calculated.
 Operands are fetched from the memory. If there is more than one operand,
then the operand fetching process may be repeated (i.e. address calculation
and fetching operands).
 After this, the data operation is performed on the operands, and a result is
generated.
 If the result has to be stored in a register, the instructions end here.
 If the destination is memory, then first the destination address has to be
calculated. Then the result is then stored in the memory. If there are multiple
results which need to be stored inside the memory, then this process may
repeat (i.e. destination address calculation and store result).
 Now the current instructions have been executed. Side by side, the PC is
incremented to calculate the address of the next instruction.
 The above instruction cycle then repeats for further instructions.
Program Control
Program Control has different types of Instructions. Program Control
Instructions are the machine code that are used by machine or in assembly
language by user to command the processor act accordingly. These
instructions are of various types. These are used in assembly language by user
also. But in level language, user code is translated into machine code and thus
instructions are passed to instruct the processor do the task.
Types of Program Control Instructions:
There are different types of Program Control Instructions:
1. Compare Instruction:
Compare instruction is specifically provided, which is similar to a subtract
instruction except the result is not stored anywhere, but flags are set according
to the result.

Example:
CMP R1, R2 ;
2. Unconditional Branch Instruction:
It causes an unconditional change of execution sequence to a new location.

Example:
JUMP L2
Mov R3, R1 goto L2
3. Conditional Branch Instruction:
A conditional branch instruction is used to examine the values stored in the
condition code register to determine whether the specific condition exists and to
branch if it does.

Example:
Assembly Code : BE R1, R2, L1
Compiler allocates R1 for x and R2 for y
High Level Code: if (x==y) goto L1;
4. Subroutines:
A subroutine is a program fragment that lives in user space, performs a well-
defined task. It is invoked by another user program and returns control to the
calling program when finished.

Example:
CALL and RET
5. Halting Instructions:

 NOP Instruction – NOP is no operation. It cause no change in the

processor state other than an advancement of the program counter. It can
 be used to synchronize timing.

 HALT – It brings the processor to an orderly halt, remaining in an idle state

until restarted by interrupt, trace, reset or external action.

6. Interrupt Instructions:
Interrupt is a mechanism by which an I/O or an instruction can suspend the
normal execution of processor and get itself serviced.

 RESET – It reset the processor. This may include any or all setting registers
to an initial value or setting program counter to standard starting location.
 TRAP – It is non-maskable edge and level triggered interrupt. TRAP has the
highest priority and vectored interrupt.
 INTR – It is level triggered and maskable interrupt. It has the lowest priority.
It can be disabled by resetting the processor.

Computer Organization | RISC and CISC

Reduced Instruction Set Architecture (RISC) –
The main idea behind this is to make hardware simpler by using an instruction
set composed of a few basic steps for loading, evaluating, and storing
operations just like a load command will load data, a store command will store
the data.
Complex Instruction Set Architecture (CISC) –
The main idea is that a single instruction will do all loading, evaluating, and
storing operations just like a multiplication command will do stuff like loading
data, evaluating, and storing it, hence it’s complex.
Both approaches try to increase the CPU performance
 RISC: Reduce the cycles per instruction at the cost of the number of
instructions per program.

 CISC: The CISC approach attempts to minimize the number of instructions

per program but at the cost of an increase in the number of cycles per
instruction.

Earlier when programming was done using assembly language, a need was felt
to make instruction do more tasks because programming in assembly was
tedious and error-prone due to which CISC architecture evolved but with the
uprise of high-level language dependency on assembly reduced RISC
architecture prevailed.
Characteristic of RISC –
1. Simpler instruction, hence simple instruction decoding.
2. Instruction comes undersize of one word.
3. Instruction takes a single clock cycle to get executed.
4. More general-purpose registers.
5. Simple Addressing Modes.
6. Fewer Data types.
7. A pipeline can be achieved.
Characteristic of CISC –
1. Complex instruction, hence complex instruction decoding.
2. Instructions are larger than one-word size.
3. Instruction may take more than a single clock cycle to get executed.
4. Less number of general-purpose registers as operations get performed in
memory itself.
5. Complex Addressing Modes.
6. More Data types.
Example – Suppose we have to add two 8-bit numbers:
 CISC approach: There will be a single command or instruction for this like
ADD which will perform the task.
 RISC approach: Here programmer will write the first load command to load
data in registers then it will use a suitable operator and then it will store the
result in the desired location.
So, add operation is divided into parts i.e. load, operate, store due to which
RISC programs are longer and require more memory to get stored but require
fewer transistors due to less complex command.
Difference –
RISC CISC

Focus on software Focus on hardware

Uses both hardwired and microprogrammed

Uses only Hardwired control unit control unit

Transistors are used for storing complex

Transistors are used for more registers Instructions

Fixed sized instructions Variable sized instructions

RISC CISC

Can perform only Register to Register Can perform REG to REG or REG to MEM or
Arithmetic operations MEM to MEM

Requires more number of registers Requires less number of registers

Code size is large Code size is small

An instruction executed in a single clock

cycle Instruction takes more than one clock cycle

Instructions are larger than the size of one

An instruction fit in one word word
 Pipelining
(Execution, Stages and Throughput)
Pipelining organizes the execution of the multiple instructions
simultaneously. Pipelining improves the throughput of the system. In
pipelining the instruction is divided into the subtasks. Each subtask performs
the dedicated task.

The instruction is divided into 5 subtasks: instruction fetch, instruction

decode, operand fetch, instruction execution and operand store. The
instruction fetch subtask will only perform the instruction fetching operation,
instruction decode subtask will only be decoding the fetched instruction and
so on the other subtasks will do.

In this section, we will discuss the types of pipelining, pipelining hazards, its
advantage. So let us start.

Content: Pipelining in Computer Architecture

1. Introduction
2. Types of Pipelining
3. Pipelining Hazards
4. Advantages
5. Key Takeaways

Introduction
Have you ever visited an industrial plant and see the assembly lines over
there? How a product passes through the assembly line and while passing it
is worked on, at different phases simultaneously. For example, take a car
manufacturing plant. At the first stage, the automobile chassis is prepared, in
the next stage workers add body to the chassis, further, the engine is
installed, then painting work is done and so on.

The group of workers after working on the chassis of the first car don’t sit idle.
They start working on the chassis of the next car. And the next group take the
chassis of the car and add body to it. The same thing is repeated at every
 stage, after finishing the work on the current car body they take on next car
body which is the output of the previous stage.

Here, though the first car is completed in several hours or days, due to the
assembly line arrangement it becomes possible to have a new car at the end
of an assembly line in every clock cycle.

Similarly, the concept of pipelining works. The output of the first pipeline
becomes the input for the next pipeline. It is like a set of data processing unit
connected in series to utilize processor up to its maximum.

An instruction in a process is divided into 5 subtasks likely,

1. In the first subtask, the instruction is fetched.

2. The fetched instruction is decoded in the second stage.
3. In the third stage, the operands of the instruction are fetched.
4. In the fourth, arithmetic and logical operation are performed on the operands
to execute the instruction.
5. In the fifth stage, the result is stored in memory.

Now, understanding the division of the instruction into subtasks. Let us

understand, how the n number of instructions in a process, are pipelined.

Look at the figure below the 5 instructions are pipelined. The first instruction
gets completed in 5 clock cycle. After the completion of first instruction, in
every new clock cycle, a new instruction completes its execution.
Observe that when the Instruction fetch operation of the first instruction is
completed in the next clock cycle the instruction fetch of second instruction
gets started. This way the hardware never sits idle it is always busy in
performing some or other operation. But, no two instructions
can execute their same stage at the same clock cycle.

Types of Pipelining
In 1977 Handler and Ramamoorthy classified pipeline processors depending
on their functionality.

1. Arithmetic Pipelining

It is designed to perform high-speed floating-point addition, multiplication and

division. Here, the multiple arithmetic logic units are built in the system to
perform the parallel arithmetic computation in various data format. Examples
of the arithmetic pipelined processor are Star-100, TI-ASC, Cray-1, Cyber-
205.

2. Instruction Pipelining
Here, the number of instruction are pipelined and the execution of current
instruction is overlapped by the execution of the subsequent instruction. It is
also called instruction lookahead.

3. Processor Pipelining

Here, the processors are pipelined to process the same data stream. The
data stream is processed by the first processor and the result is stored in the
memory block. The result in the memory block is accessed by the second
processor. The second processor reprocesses the result obtained by the first
processor and the passes the refined result to the third processor and so on.

4. Unifunction Vs. Multifunction Pipelining

The pipeline performing the precise function every time is unifunctional

pipeline. On the other hand, the pipeline performing multiple functions at a
different time or multiple functions at the same time is multifunction pipeline.

5. Static vs Dynamic Pipelining

The static pipeline performs a fixed-function each time. The static pipeline is
unifunctional. The static pipeline executes the same type of instructions
continuously. Frequent change in the type of instruction may vary the
performance of the pipelining.

Dynamic pipeline performs several functions simultaneously. It is a

multifunction pipelining.

6. Scalar vs Vector Pipelining

Scalar pipelining processes the instructions with scalar operands. The vector
pipeline processes the instruction with vector operands.

Hardwired Vs. Micro-programmed Control Unit

In a system or computer, most of the tasks are controlled with the help of a processor or
CPU (Central processing unit), which is the main component of a computer. The CPU
usually has two main systems: control unit (CU) and arithmetic and logic unit (ALU).
The control unit (CU) is used to synchronize the tasks with the help of sending timings
and control signals. On the other hand, mathematical and logical operations can be
handled with the help of ALU. Micro programmed control units and hardwired control
units can be called two types of control units. We can execute an instruction with the
help of these two control units.

In the hardwired control unit, the execution of operations is much faster, but the
implementation, modification, and decoding are difficult. In contrast, implementing,
modifying, decoding micro-programmed control units is very easy. The micro-
programmed control unit is also able to handle complex instructions. With the help of
control signals generated by micro-programmed and hardwired control units, we are
able to fetch and execute the instructions.

Control Signals
In order to generate the control signals, both the control signals were basically
designed. The functionality of a processor's hardware is operated with the help of these
control signals. The control signals are used to know about various types of things,
which are described as follows:

o Control signals are used to know what operation is going to be performed.

o It is used to know about the sequence of operations that are performed by the
processor.
o It is used to know about the timing at which an operation must be executed and many
other types of things.

Hardwired Control Unit

With the help of generating control signals, the hardwired control unit is able to execute
the instructions at a correct time and proper sequence. As compared to the micro-
programmed, the hardwired CU is generally faster. In this CU, the control signals are
generated with the help of PLA circuit and state counter. Here the Central processing
unit requires all these control signals. With the help of hardware, the hardwired control
signals are generated, and it basically uses the circuitry approach.

The image of a hardwired control unit is described as follows, which contains various
components in the form of circuitry. We will discuss them one by one so that we can
properly understand the "generation of control signals".
o The instruction register is a type of processor register used to contain an instruction
that is currently in execution. As we can see, the instruction register is used to generate
the OP-code bits respective of the operation as well as the addressing mode of
operands.
o The above generated Op-code bits are received in the field of an instruction decoder.
The instruction decoder interprets the operation and instruction's addressing mode. Now
on the basis of the addressing mode of instruction and operation which exists in the
instruction register, the instruction decoder sets the corresponding Instruction signal
INSi to 1. Some steps are used to execute each instruction, i.e., instruction
fetch, decode, operand fetch, Arithmetic and logical unit, and memory store.
Different books might be contained different steps. But in general, we are able to
execute an instruction with the help of these five steps.
o The information about the current step of instruction must be known by the control unit.
Now the Step Counter is implemented, which is used to contain the signals from T1,….,
 T5. Now on the basis of the step which contains the instruction, one of the signals of a
step counter will be set from T1 to T5 to 1.
o Now we have a question that how the step counter knows about the current step of
instruction? So to know the current step, a Clock is implemented. The one-clock cycle of
the clock will be completed for each step. For example, suppose that if the stop counter
sets T3 to 1, then after completing one clock cycle, the step counter will set T4 to 1.
o Now we have a question, i.e., what will happen if the execution of an instruction is
interrupted for some reason? Will the step counter still be triggered by the clock? The
answer to this question is No. As long as the execution is current step is completed,
the Counter Enable will "disable" the Step Counter so that it will stop then increment to
the next step signal.
o Now we have a question, i.e., what if the execution of instruction depends on some
conditions? In this case, the Condition Signals will be used. There are various conditions
in which the signals are generated with the help of control signals that can be less than,
greater than, less than equal, greater than equal, and many more.
o The external input is the last one. It is used to tell the Control Signal Generator about
the interrupts, which will affect the execution of an instruction.

So, on the basis of the input obtained by the conditional signals, step counter, external
inputs, and instruction register, the control signals will be generated with the help of
Control signal Generator.

Micro-programmed Control Unit

A micro-programmed control unit can be described as a simple logic circuit. We can use
it in two ways, i.e., it is able to execute each instruction with the help of generating
control signals, and it is also able to do sequencing through microinstructions. It will
generate the control signals with the help of programs. At the time of evolution of CISC
architecture in the past, this approach was very famous. The program which is used to
create the control signals is known as the "Micro-program". The micro-program is
placed on the processor chip, which is a type of fast memory. This memory is also
known as the control store or control memory.

A micro-program is used to contain a set of microinstructions. Each microinstruction or

control word contains different bit patterns. The n bit words are contained by each
microinstruction. On the basis of the bit pattern of a control word, every control signals
differ from each other.
Like the above, the instruction execution in a micro-programmed control unit is also
performed in steps. So for each step, the micro-program contains a control word/
microinstruction. If we want to execute a particular instruction, we need a sequence of
microinstructions. This process is known as the micro-routine. The image of a micro-
programmed control unit is described as follows. Here, we will learn the organization of
micro-program, micro-routine, and control word/ microinstruction.

Now we will learn about the organization of Micro-program CU. Then we will learn
about the flow of instruction execution with the help of instruction execution steps,
which are described as follows:
o Instruction fetch is the first step. In this step, the instruction is fetched from the IR
(Instruction Register) with the help of a Microinstruction address register.
o Decode is the second step. In this step, the instructions obtained from the instruction
register will be decoded with the help of a microinstruction address generator. Here we
will also get the starting address of a micro-routine. With the help of this address, we can
easily perform the operation, which is mentioned in the instruction. It will also load the
starting address into the micro-program counter.
o Increment is the third step. In this step, the control word, which corresponds to the
starting address of a micro-program, will be read. When the execution proceeds, the
value of the micro-program counter will be increased so that it can read the successive
control words of a micro-routine.
 o End bit is the fourth step. In this step, the microinstruction of a micro-routine contains a
bit, which is known as the end bit. The execution of the microinstruction will be
successfully completed when the end bit is set to 1.
o This is the last step, and in this step, the micro-program address generator will again go
back to Step 1 so that we can fetch a new instruction, and this process or cycle goes on.

So in the micro-programmed control unit, the micro-programs are stored with the help
of Control memory or Control store. The implementation of this CU is very easy and
flexible, but it is slower as compared to the Hardwired control unit.

Micro Instructions Sequencer is a combination of all hardware for selecting

the next micro-instruction address. The micro-instruction in control memory
contains a set of bits to initiate micro operations in computer registers and other
bits to specify the method by which the address is obtained.
Implementation of Micro Instructions Sequencer –
 Control Address Register(CAR) :
Control address register receives the address from four different paths. For
receiving the addresses from four different paths, Multiplexer is used.
 Multiplexer :
Multiplexer is a combinational circuit which contains many data inputs and
single data output depending on control or select inputs.
 Branching :
Branching is achieved by specifying the branch address in one of the fields
of the micro instruction. Conditional branching is obtained by using part of
the micro-instruction to select a specific status bit in order to determine its
condition.
 Mapping Logic :
An external address is transferred into control memory via a mapping logic
circuit.
 Incrementer :
Incrementer increments the content of the control address register by one, to
select the next micro-instruction in sequence.
 Subroutine Register (SBR) :
The return address for a subroutine is stored in a special register called
Subroutine Register whose value is then used when the micro-program
wishes to return from the subroutine.
 Control Memory :
Control memory is a type of memory which contains addressable storage
registers. Data is temporarily stored in control memory. Control memory can
be accessed quicker than main memory.

Types of Micro-programmed Control Unit – Based on the type of Control

Word stored in the Control Memory (CM), it is classified into two types :
1. Horizontal Micro-programmed Control Unit :
The control signals are represented in the decoded binary format that is 1
bit/CS. Example: If 53 Control signals are present in the processor then 53 bits
are required. More than 1 control signal can be enabled at a time.
 It supports longer control words.
 It is used in parallel processing applications.
 It allows a higher degree of parallelism. If degree is n, n CS is enabled at a
time.
 It requires no additional hardware(decoders). It means it is faster than
Vertical Microprogrammed.
 It is more flexible than vertical microprogrammed
2. Vertical Micro-programmed Control Unit :
The control signals are represented in the encoded binary format. For N control
signals- Log2(N) bits are required.
 It supports shorter control words.
 It supports easy implementation of new control signals therefore it is more
flexible.
 It allows a low degree of parallelism i.e., the degree of parallelism is either 0
or 1.
 Requires additional hardware (decoders) to generate control signals, it
implies it is slower than horizontal microprogrammed.
 It is less flexible than horizontal but more flexible than that of a hardwired
control unit.