Part1

Internet-of-things-based embedded systems depend on batteries as an energy

resource, and thus, require energy-efficient
circuits for prolonged operation. To achieve energy-efficient designs, multiple-
valued logic circuits and carbon nanotube
field-effect transistors (CNTFETs) are used instead of binary logic circuits and
complementary metal–oxide–semiconductor,
respectively. This paper presents a novel high-performance and energy-efficient
ternarymultiplier (TMUL) circuit inCNTFET
technology.
two power supplies, VDD and VDD/2, are employed to eliminate the direct path
from high to low voltage levels in each possible combination of inputs. Using
ternary unary operator circuits and applying two power supply components reduce
the number of transistors used, delay, and power/energy.
The delay, power, and power-delay-product (PDP) of the proposed design at 0.9 V
supply voltage are 0.048 ns, 0.172 μW, and 0.008 pJ, respectively. The proposed
TMUL offers an improvement between 8.70 and 71% in transistors count, between
11.11 and 81.54% in delay, between 6.52 and 72.74% in power consumption, and
between 27.27 and 94.07% in PDP compared to the latest TMUL circuits.

،‫دو منبع تغذیه‬VDD ‫ و‬VDD/2 ‫ برای حذف مسیر مستقیم از سطوح ولتاژ باال به پایین در هر ترکیب‬،
‫ استفاده از مدارهای اپراتور سه تایی و اعمال دو جزء منبع تغذیه‬.‫ممکن از ورودیها استفاده میشوند‬
‫ توان و محصول‬،‫ تأخیر‬.‫انرژی می شود‬/‫ تاخیر و توان‬،‫باعث کاهش تعداد ترانزیستورهای استفاده شده‬
‫( تأخیر توان‬PDP) 0.048 ‫ ولت به ترتیب‬0.9 ‫ طرح پیشنهادی در ولتاژ تغذیه‬ns0.172 ، ‫میکرووات و‬
0.008 pJ ‫است‬. TMUL 11.11 ‫ بین‬،‫ درصد در تعداد ترانزیستورها‬71 ‫ تا‬8.70 ‫پیشنهادی بهبودی بین‬
‫ درصد‬94.07 ‫ تا‬27.27 ‫ درصد در مصرف برق و بین‬72.74 ‫ تا‬6.52 ‫ بین‬،‫ درصد در تاخیر‬81.54 ‫تا‬
‫ در‬PDP ‫ نسبت به آخرین مدارهای‬TMUL ‫ارائه می دهد‬.

Part2
Introduction
Problem statement (S2)
The IoTs, in turn, result in rapid growth and advance in all fields such as wearable
electronics, robotics, military applications, wireless sensor nodes, environmental
monitoring, health monitoring, smart cities, implantable medical devices,
handhelds, and smart home security systems
these IoT-based systems require long battery lifetimes, further limiting the power
budgets

solutions (S3)

To achieve this purpose:

1. Use of carbon nanotube field-effect transistors (CNTFETs) rather than

complementary metal–oxide–semiconductor (CMOS) as a transistor-level
technique.

2. Use of multiple-valued logic (MVL) circuits rather than binary logic circuits
as a design-level technique.

(S4)
The use of CMOS technology in designing nanometerscale systems causes some
limitations and problems including the known short-channel effects (SCEs),
increasing leakage current, decreasing gate control, and high lithography costs . To
overcome these problems, researchers try their best to find alternatives to
traditional CMOS technology.
CNTFET is one of the promising alternatives to CMOS technology. CNTFET can
reduce the transistor feature size, delay, and power consumption and have a better
performance

its properties:
1. the high mobility of P-CNTFET and N-CNTFET,
2. high ON to OFF currents ratio,
3. low OFF current
4. low power consumption,
5. energy-efficient
6. less leakage current

interconnections cover nearly 70% of the total area of a modern very large-scale
integrated (VLSI) circuit, which leads to serious limitations As a result, it may be
considered a failure source
MVL can be employed as a technique for enhancing the transfer rate of data
because in MVL each digit can hold more than two states of data. Therefore, the
number of interconnections and their
complexity is considerably reduced. This enhances energy efficiency in
comparison with binary circuits

MVL system lowers interconnections, chip area by up to 70%, and energy

consumption by more than 50%. Among all known base systems, the ternary logic
system, which is represented as [Low: 0 (0 V), Middle: 1 (VDD/2), and High: 2
(VDD)], has a higher performance [4], and therefore, will be used in this paper to
design the proposed circuit.

1.3 Getting Logic ‘1’ in Ternary System (S5)

In the ternary logic systems, accessing logic ‘1’ is very challenging.There are three
possible solutions as follows:
1. Getting the logic ‘1’ by inserting two resistor(‫)مقاومت‬to create a voltage
divider in the output, but increasing the circuit area. This solution is not
recommended in modern VLSI circuits. Moreover, when the ternary input is
equal to the logic ‘1’, a direct path from VDD to ground is created, increasing
power consumption
2. Getting the logic ‘1’ by inserting two diode-connected transistors to create a
voltage divider in the output. This solution overcomes the problems of
solution (1) in terms of the circuit size. However, this kind of design also
consumes high power
3. Use of two power supplies (dual-VDD), VDD and VDD/2, to remove the direct
path between high and low potential voltages. The drawback of this solution
is an increase in the interconnections in the circuits

1.4 Our Contributions (S6)

The same mobility of P-CNTFET and N-CNTFET transistors is one of the most
important features of CNTFETs that reduces the complexity of the design and
reduces the size of CNTFET-based circuits compared to MOSFET-based circuits.

The effect of the PVT variation on CNTFET is much lower than that of MOSFET
devices
The threshold voltage (Vth) of the CNTFET has an inverse relation to the diameter
of the carbon nanotube (CNT). Therefore, the CNTFET is an optimal candidate
for MVL circuit implementations. Therefore, in this paper, we present a novel
ternary multiplier (TMUL) using CNTFET transistors. The main features of the
proposed design are as follows:

1. The proposed design does not employ ternary logic gates, ternary decoder,
or ternary encoder,which increase the number of transistors used and power-
delay-product (PDP)
2. The proposed design does not utilize cascading transmission-gates (TGs),
which produce more propagation delay.

3. The proposed design is designed based on only the two unary(‫)یکنواخت‬

operators, negative ternary inverter (NTI) and positive ternary inverter (PTI).
4. The proposed design employs the dual-VDD technique to get the logic ‘1’,
thereby removing the direct path between VDD and ground and improving
energy consumption.
5. Only 21 CNTFET transistors are required to design the proposed TMUL,
which is the lowest transistors count till now,

2 Background
2.1 Existing TernaryMultipliers
2.2 Carbon Nanotube Field-Effect Transistor (CNTFET) (S7)

(Si-MOSFETs) suffer highly from the well-known SCEs and related problems
such as increased gate leakage current, higher power dissipation(‫)اتالف‬, and
unreliability in the scale of nanometer. These limitations have forced researchers to
look for other promising nanometerscale materials that can be replaced with Si as
channel materials.

CNT, one of the best carbon allotropes, has emerged as a potential replacement for
Si in future electronics.

CNTFETs have four terminals Drain, Source, Gate, and Bulk just likeMOSFETs.
InCNTFETs also, the gate terminal controls the ON and OFF states of the
transistor
both n and m are integers, a CNT would have either metallic or semiconducting
properties. If n is equal to m (n = m) or the difference of n and m is a multiple of 3
(n − m = 3 k,k is an integer), a CNT would be metallic, and otherwise, it is
semiconducting [17]. The diameter of a CNT, denoted by DCNT, is calculated by
Eq. (1), where a is the carbon–carbon atom distance and equals 0.249 nm. It is
assumed that m is always zero (i.e.,m=0), and therefore, Eq. (1) is simplified to Eq.
(2)[17]. ‫توضیحات مربوط به فرمول‬

(S8)

Figure 1 shows the schematic diagram, illustration of modeled CNTFET, and

relevant parameters of CNTFET [19]. Where Lch, Ldd, and Lss are the lengths of
the undoped CNT channel, doped CNT drain-side extension, and doped CNT
source-side extension regions, respectively. TOX is the oxide thickness of the gate
dielectric material, which is hafnium dioxide or hafnia (HfO2), and Csub is the
coupling capacitancebetween the channel region and the substrate.

(S9)
Thewidth of the channel in a CNTFET (WCNT) is calculated by Eq. (3), where N is
the number of CNTs, and Pitch is the distance between the centers of two
neighboring CNTs [20].

The Vth of a CNTFET is determined by Eq. (4), where Eπ is the carbon–carbon

bond energy in the tight bonding model and equals nearly 3.033 eV (electron volt)
and e is the unit electron charge.

As can be seen from Eq. (3), the Vth of a CNTFET has an inverse relation to DCNT.
This is one of themost useful properties of a CNTFET because its Vth can be easily
controlled by the value of DCNT [17].

(S10)

The operations of P-CNTFT and N-CNTFET devices are described in Table 1. As

can be seen, a CNT with a chirality(‫ )کایرالیته‬vector (10, 0) provides a high |Vth|
(0.56 V) and a CNT with a chirality vector (19, 0) provides a low |Vth| (0.29 V)
(S11)
Unary Operators of Ternary System

Unary operators of an i-valued system are special types of logic gates, having only
one-input and one-output. In an ivalued system, there are ii unary functions. For
instance, in the binary system, where i=2, there are four unary functions including
“00”, “01”, “10”, and “11”. In the ternary system, on the other hand, where i = 3,
there are twenty-seven unary functions including “000”, “001”, “002”, …, and
“222”. In this paper, the ternary logic system is represented in its standard way (0,
1 or VDD/2, 2 or VDD)

(s12)

Table 2 shows some of the unary operators of the ternary system. As observed
from Table 2, the first three unary operators are the three types of ternary inverters.
Negative ternary inverter (NTI), denoted byBN, positive ternary inverter (PTI),
denoted by BP, and standard ternary inverter (STI), denoted by B, which is the
complement of B. These unary operators can be derived from Eq. (5),

(s13)
In this paper, only NTI and PTI will be used to design the proposed TMUL, as
shown in Fig. 2.

(s14)
Proposed Ternary Multiplier
The TMUL gets the two ternary inputs A and B, multiplies them, and then
generates the two ternary outputs Product and Carry. Table 3 gives the truth table
of the TMUL.

(s15)
Carry Generation Circuit

As observed in Table 4, the ternary output Carry gets the logic ‘1’ only when both
the ternary inputs, A and B, are equal to the logic ‘2’, and it becomes the logic ‘0’
for the other combinations of the inputs
this is the efficient of design of Carry generation circuit because it needs only the
two unary operators, Ap and Bp, and is implemented using four transistors. The
proposed TMUL utilizes this circuit for the ternary output Carry generation, as
shown in Fig. 3 along with its transient response. (S16)

(s17)
Product Generation Circuit

In Table 3, the part related to the ternary output Product is modified to the form of
Table 5 to design the Product generation circuit. To design the ternary output
Product generation circuit, we follow three steps, as shown in Table 5.

(S18)
Step 1 As observed in Table 5, the ternary output Product is equal to the logic ‘0’
when one of the ternary inputs is the logic ‘0’ and when both the ternary inputs are
the logic ‘0’. This can be implemented using the two unary operators An and Bn
and needs only two n-type transistors, as shown in Fig. 4 along with its transient
response.

(S19)

Step 2 As observed in Table 5, when the ternary input A is the logic ‘1’, the ternary
output Product becomes equal to the ternary input B. This can be implemented
using two series-connected p-type transistors, gated by A and AN,which transmit
the ternary input B to the output, as shown in Fig. 5. It is worth mentioning that
this path is established only for A = ‘1’.

(S20)
Step 3 As observed in Table 5, when both the unary operators AP and BP are the
logic ‘0’, the ternary output Product becomes equal to the logic ‘1’. On the other
hand, the ternary output Product becomes equal to the logic ‘2’ when the unary
operators AP and BN are the logic ‘0’ and the ternary input B is the logic ‘1’. This
can be implemented using five p-type transistors, as shown in Fig. 6.

(S21)
Overall Schematic of Proposed TMUL
The overall schematic of the proposed TMUL along with its transient response is
illustrated in Fig. 7. It is observed from this figure that the proposed TMUL
operates well.

The previous TMUL [2] utilizes three unary operators including NTI (AN and BN),
PTI (AP and BP), and B2 (see Table 2). Furthermore, it employs two cascading TGs
to pass the ternary input B when the ternary input A is equal to the logic ‘1’ and
one TG to pass the B2 when the ternary input A is equal to the logic ‘2’.

These cascading TGs increase the propagation delay. Moreover, it utilizes dual-
VDD technique to get the logic ‘1’.

(S22)
Table 6 gives some of the important parameters of the CNTFET model used in all
the circuits with brief descriptions

(S23)
Transistors Count Comparison

Table 7 compares the proposed TMUL with the other existing TMULs in the
literature in terms of transistors count. As can be seen from this table, the proposed
TMUL has the lowest transistors count. These improvements are due to the fact
that the proposed TMUL is designed using only two unary operators, NTI and PTI,
which reduce the number of transistors used.

(S24)
Performance Comparison

Table 8 provides a comparison between the proposed TMUL and some of the
existing TMULs in the literature [2, 4, 5, 7, 14]. As can be seen from this table, the
proposed TMUL reduces the number of transistors used by 30%, 8.70%, 44.74%,
19.23%, and 8.70% compared to the TMULs proposed in [2, 4, 5, 7, 14],
respectively.

static power is the dominant factor because it consumes nearly 98% of the average
power. To reduce the static power, the use of dual-VDD, is preferred.
Major Process Variation (S25)

Process variations are mainly occurred due to the changes in the transistor’s
attributes such as channel length (Lch), oxide thickness (TOX), CNT diameter
(DCNT), Pitch, and CNT’s count (N. These variations will become a main concern
in the nanometer-scale region

(S26)

Which One is Better: Chirality Vector (19, 0) or (28, 0)?

The transistors with chirality vectors (19, 0) and (28, 0) have similar ON or OFF
states for 0, 1, and 2 inputs [24]. Table 9 compares the delay, power, and PDP of
the proposed design and the studied TMULs [2, 4, 5, 7] for the above-mentioned
chirality vectors. Selecting the chirality vector (28, 0) instead of (19, 0) reduces
delay and increases the power consumption of the TMULs. However, PDP reduces

Conclusion
IoT applications demand low-energy circuits because they operate with restricted
energy from batteries. MVL circuits provide notable improvements over binary
circuits in terms of interconnect complexity, chip area, delay, and power/energy
consumption. Moreover, CNTFET overcomes CMOS scaling issues in the
nanometer regime and offers better performance. Therefore, in this paper, a novel
highperformanceand energy-efficientTMULcircuit is presented, which can be used
in IoT devices to save battery consumption