DATASHEET

HCS165MS FN2481
Radiation Hardened Inverting 8-Bit Parallel-Input/Serial Output Shift Register Rev 2.00
September 1995

Features Pinouts
• 3 Micron Radiation Hardened SOS CMOS 16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
• Total Dose 200K RAD (Si) MIL-STD-1835 CDIP2-T16, LEAD FINISH C
• SEP Effective LET No Upsets: >100 MEV-cm2/mg TOP VIEW

• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ PL 1 16 VCC

Bit-Day (Typ) CP 2 15 CE
12 D4 3 14 D3
• Dose Rate Survivability: >1 x 10 RAD (Si)/s
D5 4 13 D2
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
D6 5 12 D1
• Latch-Up Free Under Any Conditions
D7 6 11 D0
• Fanout (Over Temperature Range) Q7 7 10 DS
- Standard Outputs - 10 LSTTL Loads GND 8 9 Q7
oC
• Military Temperature Range: -55 to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V 16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
• Input Logic Levels MIL-STD-1835 CDFP4-F16, LEAD FINISH C
- VIL = 0.3 VCC Max TOP VIEW
- VIH = 0.7 VCC Min
PL 1 16 VCC
• Input Current Levels Ii  5A at VOL, VOH CP 2 15 CE
D4 3 14 D3
Description D5 4 13 D2
The Intersil HCS165MS is a Radiation Hardened 8-Bit Paral- D6 5 12 D1
lel-In/Serial-Out Shift Register with complementary serial D7 6 11 D0
outputs and an asynchronous parallel load input. Q7 7 10 DS
The HCS165MS utilizes advanced CMOS/SOS technology GND 8 9 Q7
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS165MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).

Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE

HCS165DMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead SBDIP

HCS165KMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead Ceramic Flatpack

HCS165D/Sample +25oC Sample 16 Lead SBDIP

HCS165K/Sample +25oC Sample 16 Lead Ceramic Flatpack

HCS165HMSR +25oC Die Die

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September 1995
HCS165MS

Functional Diagram

D0 D1 D2 D3 D4 D5 D6 D7

CP
CE

CL CL CL CL CL CL CL CL
DP PL DP PL DP PL DP PL DP PL DP PL DP PL DP PL
FF FF FF FF FF FF FF FF
DS DS Q DS Q DS Q DS Q DS Q DS Q DS Q DS Q

PL

D7

D7

TRUTH TABLE

INPUTS Qn REGISTER OUTPUTS

OPERATING
MODES PL CE CP DS D0 - D7 Q0 Q1 - Q6 Q7 Q7

Parallel Load L X X X L L L-L L H

L X X X H H H-H H L

Serial Shift H L l X L Q0 - Q5 Q6 Q6

H L h X H Q0 - Q5 Q6 Q6

Hold “Do Nothing” H H X X X Q0 Q1 - Q6 Q7 Q7

H = HIGH voltage level

h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the LOW-to-High clock transition
Qn = Lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition.
X = Don’t Care
= LOW-to-HIGH clock transition.

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Absolute Maximum Ratings Reliability Information

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Thermal Resistance JA JC
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W
DC Input Current, Any One Input  10mA Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W
DC Drain Current, Any One Output 25mA Maximum Package Power Dissipation at +125oC Ambient
(All Voltage Reference to the VSS Terminal) SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC If device power exceeds package dissipation capability, provide heat
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC sinking or derate linearly at the following rate:
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..

Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . . 500ns Max Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP LIMITS
(NOTE 1) A SUB-
PARAMETER SYMBOL CONDITIONS GROUPS TEMPERATURE MIN MAX UNITS

Quiescent Current ICC VCC = 5.5V, 1 +25oC - 40 A

VIN = VCC or GND
2, 3 +125oC, -55oC - 750 A

Output Current IOL VCC = 4.5V, VIH = 4.5V, 1 +25oC 4.8 - mA

(Sink) VOUT = 0.4V, VIL = 0V
2, 3 +125oC, -55oC 4.0 - mA

Output Current IOH VCC = 4.5V, VIH = 4.5V, 1 +25oC -4.8 - mA

(Source) VOUT = VCC -0.4V,
VIL = 0V 2, 3 +125oC, -55oC -4.0 - mA

Output Voltage Low VOL VCC = 4.5V, VIH = 3.15V, 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V
IOL = 50A, VIL = 1.35V

VCC = 5.5V, VIH = 3.85V, 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

IOL = 50A, VIL = 1.65V

Output Voltage High VOH VCC = 4.5V, VIH = 3.15V, 1, 2, 3 +25oC, +125oC, -55oC VCC - V
IOH = -50A, VIL = 1.35V -0.1

VCC = 5.5V, VIH = 3.85V, 1, 2, 3 +25oC, +125oC, -55oC VCC - V

IOH = -50A, VIL = 1.65V -0.1

Input Leakage IIN VCC = 5.5V, VIN = VCC or 1 +25oC - 0.5 A

Current GND
2, 3 +125oC, -55oC - 5.0 A

Noise Immunity FN VCC = 4.5V, 7, 8A, 8B +25oC, +125oC, -55oC - - -

Functional Test VIH = 0.70(VCC),
VIL = 0.30(VCC) (Note 2)

NOTES:
1. All voltages reference to device GND.
2. For functional tests VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.

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TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP LIMITS
(NOTES 1, 2) A SUB-
PARAMETER SYMBOL CONDITIONS GROUPS TEMPERATURE MIN MAX UNITS

CP or CE to Q7 or TPLH VCC = 4.5V 9 +25oC 2 35 ns

Q7 TPHL
10, 11 +125oC, -55oC 2 41 ns

PEN to Q7 or Q7 TPLH VCC = 4.5V 9 +25oC 2 40 ns

TPHL
10, 11 +125oC, -55oC 2 46 ns

D7 to Q7 TPLH VCC = 4.5V 9 +25oC 2 27 ns

TPHL
10, 11 +125oC, -55oC 2 31 ns

D7 to Q7 TPLH VCC = 4.5V 9 +25oC 2 29 ns

TPHL
10, 11 +125oC, -55oC 2 35 ns

NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
(NOTE 1)
PARAMETER SYMBOL CONDITIONS TEMPERATURE MIN MAX UNITS
oC
Capacitance Power CPD VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, +25 - 41 pF
Dissipation f = 1MHz o o
+125 C, -55 C - 56 pF
Input Capacitance CIN VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, +25oC - 10 pF
f = 1MHz
+125oC, -55oC - 10 pF
o
Output Capacitance COUT VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, +25 C - 20 pF
f = 1MHz
+125oC, -55oC - 20 pF

Pulse Width Time CP, TW VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25oC 16 - ns
PL o o
+125 C, -55 C 24 - ns
Setup Time TSU VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25oC 16 - ns
DS to CP, CE to CP,
+125o o
C, -55 C 24 - ns
Dn to PL

Hold Time TH VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25oC 7 - ns

DS to CP, CE
+125o o
C, -55 C 11 - ns
o
Hold Time TH VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25 C 0 - ns
CE to CP oC,
+125 -55oC 0 - ns

Recovery Time o
TREC VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25 C 20 - ns
PL to CP o o
+125 C, -55 C 30 - ns
oC
Maximum FMAX VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25 30 - MHz
Frequency
+125o o
C, -55 C 20 - MHz
o
Output Transition Time TTHL VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25 C 1 15 ns
TTLH
+125o o
C, -55 C 1 22 ns

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TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
(NOTE 1)
PARAMETER SYMBOL CONDITIONS TEMPERATURE MIN MAX UNITS

NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

200K RAD
LIMITS
(NOTES 1, 2)
PARAMETER SYMBOL CONDITIONS TEMPERATURE MIN MAX UNITS

Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND +25oC - 0.75 mA

Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, +25oC 4.0 - mA
VOUT = 0.4V

Output Current IOH VCC = 4.5V, VIN = VCC or GND, +25oC -4.0 - mA
(Source) VOUT = VCC -0.4V

Output Voltage Low VOL VCC = 4.5V or 5.5V, VIH = 0.70(VCC), +25oC - 0.1 V
VIL = 0.30(VCC), IOL = 50A

Output Voltage High VOH VCC = 4.5V or 5.5V, VIH = 0.70(VCC), +25oC VCC - V
VIL = 0.30(VCC), IOH = -50A -0.1

Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC - 5 A

Noise Immunity FN VCC = 4.5V, VIH = 0.70(VCC), +25oC - - -

Functional Test VIL = 0.30(VCC), (Note 3)

CP or CEN to Q7 or TPLH VCC = 4.5V +25oC 2 41 ns

Q7N TPHL

PEN to Q7 or Q7N TPLH VCC = 4.5V +25oC 2 46 ns

TPHL

D7 to Q7 TPLH VCC = 4.5V +25oC 2 31 ns

TPHL

D7 to Q7N TPLH VCC = 4.5V +25oC 2 35 ns

TPHL

NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)

GROUP B
PARAMETER SUBGROUP DELTA LIMIT

ICC 5 12A

IOL/IOH 5 -15% of 0 Hour

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TABLE 6. APPLICABLE SUBGROUPS

CONFORMANCE GROUPS METHOD GROUP A SUBGROUPS READ AND RECORD

Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H

Interim Test I (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H

Interim Test II (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H

PDA 100%/5004 1, 7, 9, Deltas

Interim Test III (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H

PDA 100%/5004 1, 7, 9, Deltas

Final Test 100%/5004 2, 3, 8A, 8B, 10, 11

Group A (Note 1) Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11

Group B Subgroup B-5 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11,
(Note 2)

Subgroup B-6 Sample/5005 1, 7, 9

Group D Sample/5005 1, 7, 9

NOTES:
1. Alternate Group A testing in accordance with method 5005 of MIL-STD-883 may be exercised.
2. Table 5 parameters only.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

CONFORMANCE
GROUPS METHOD PRE RAD POST RAD PRE RAD POST RAD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1,9 Table 4 (Note 1)

NOTE:
1. Except FN test which will be performed 100% Go/No-Go.

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS

OSCILLATOR

OPEN GROUND 1/2 VCC = 3V  0.5V VCC = 6V  0.5V 50kHz 25kHz

STATIC BURN-IN I TEST CONNECTIONS (Note 1)

7, 9 1 - 6, 8, 10 - 15 - 16 - -

STATIC BURN-IN II TEST CONNECTIONS (Note 1)

7, 9 8 - 1 - 6, 10 - 16 - -

DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)

- 3 - 6, 8, 11 - 15 7, 9 1, 16 2 10

NOTES:
1. Each pin except VCC and GND will have a resistor of 10k  5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1k  5% for dynamic burn-in

TABLE 9. IRRADIATION TEST CONNECTIONS

OPEN GROUND VCC = 5V  0.5V

7, 9 8 1 - 6, 10 - 16

NOTE: Each pin except VCC and GND will have a resistor of 47K  5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.

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Intersil Space Level Product Flow - ‘MS’

Wafer Lot Acceptance (All Lots) Method 5007 100% Interim Electrical Test 1 (T1)
(Includes SEM) 100% Delta Calculation (T0-T1)
GAMMA Radiation Verification (Each Wafer) Method 1019, 100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
4 Samples/Wafer, 0 Rejects +125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023 100% Interim Electrical Test 2 (T2)
Sample - Wire Bond Pull Monitor, Method 2011 100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027 100% PDA 1, Method 5004 (Notes 1and 2)
100% Internal Visual Inspection, Method 2010, Condition A 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
100% Temperature Cycle, Method 1010, Condition C, Equivalent, Method 1015
10 Cycles 100% Interim Electrical Test 3 (T3)
100% Constant Acceleration, Method 2001, Condition per 100% Delta Calculation (T0-T3)
Method 5004
100% PDA 2, Method 5004 (Note 2)
100% PIND, Method 2020, Condition A
100% Final Electrical Test
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Serialization
100% Radiographic, Method 2012 (Note 3)
100% Initial Electrical Test (T0)
100% External Visual, Method 2009
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
Sample - Group A, Method 5005 (Note 4)
+125oC min., Method 1015
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.

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HCS165MS

AC Timing Diagram AC Load Circuit

DUT TEST
VIH POINT

VS INPUT
CL RL
VIL

TPLH
TPHL
VOH
CL = 50pF
VS OUTPUT RL = 500
VOL

TTLH TTHL
VOH
80% 80%

20% OUTPUT 20%

VOL

AC VOLTAGE LEVELS

PARAMETER HCS UNITS

VCC 4.50 V

VIH 4.50 V

VS 2.25 V

VIL 0 V

GND 0 V

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Die Characteristics GLASSIVATION:

Type: SiO2
DIE DIMENSIONS: Thickness: 13kÅ  2.6kÅ
95 x 94 mils
WORST CASE CURRENT DENSITY:
METALLIZATION: < 2.0 x 105A/cm2
Type: AlSi
Metal Thickness: 11kÅ 1kÅ BOND PAD SIZE:
100m x 100m
4 x 4 mils

Metallization Mask Layout

HCS165MS

CP PL VCC CE D3
(2) (1) (16) (15) (14)

D4 (3)

(13) D2

D5 (4)

(12) D1

D6 (5)

(11) D0

(6) (7) (8) (9) (10)

D7 Q7 GND Q7 DS

NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask
series for the HCS165 is TA14385A.

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