Computer Organization Architecture Unit-III Ms.

Suman Singh
Assistant Professor (IT)

UNIT – III:-No. of Hours: 11 Chapter/Book Reference: TB1 [Chapter-5, 9], RB3 [Chapter-11]

Data Transfer Operations: Register Transfer, Bus and Memory Transfer, Registers and micro-
operations. Basic Computer Organizations and Design: Instruction Codes, Computer Registers,
Instruction Cycle, General Register Organization, Stack Organization, Instruction Formats,
Addressing Modes,

Data Transfer Operations: Register Transfer, Bus and Memory Transfer, Registers and micro-
operations.

Register Transfer Language

 Digital System uses a modular approach.

 The modules are constructed from such digital components as registers, decoders,
arithmetic elements and control logics.
 Various modules are interconnected with common data and control data and control path.
 Digital Module is best defined fine Registers.
 Register contains the operations that are performed on the data stored in them.

Micro operation: The operations executed on the data stored in registers are called micro
operations.

 The functions built into registers are examples of micro operations

 Shift
 Load
 Clear
 Increment
Register transfer language

 A symbolic language
 A convenient tool for describing the internal organization of digital
computers
 Can also be used to facilitate the design process of digital systems.
Register transfer implies the availability of hardware logic circuits that can perform a stated
micro operation and transfer the result of operation to the same register or another register.
Language implies the programming language or Symbolic language for register transfer.

Register

 Registers are designated by capital letters, sometimes followed by numbers (e.g., A,

R13, IR)
 Often the names indicate function:
– MAR - memory address register

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

– PC - program counter
– IR - instruction register

 Registers and their contents can be viewed and represented in various ways
 A register can be viewed as a single entity:
 Registers may also be represented showing the bits of data they contain
Common ways of drawing the block diagram of a register

Fig 2 Block Diagram of Register

Register Transfer

 Copying the contents of one register to another is a register transfer

 Information transfer from one register to another is designated in symbolic form by
means of a replacement operator.
 A register transfer is indicated as

R2 R1
 In this case the contents of register R2 are copied (loaded) into registerR1
 A simultaneous transfer of all bits from the source R1 to the destination
register R2, during one clock pulse

 Note that this is a non-destructive; i.e. the contents of R1 are not altered by copying
(loading) them to R2
Example: A register transfer such as
R3 R5
Implies that the digital system has
 the data lines from the source register (R5) to the destination register (R3)
 Parallel load in the destination register (R3)
 Control lines to perform the action
 Transfer to occur only under a predetermined control condition This is shown by an if-
else statement
If (P=1) then (R2  R1) Where P is a control signal.
 In digital systems, if –else statement done via a control signal, called a control function
 Control Function is a Boolean variable that is equal to 1 or 0.

– If the signal is 1, the action takes place

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

This is represented as: P: R2  R1

Control Condition is terminated with a colon.
Which means “if P = 1, then load the contents of register R1 into register R2”, i.e., if (P =
1) then (R2  R1)

Fig. 3 Block Diagram of a Register Transfer

Fig 4 .Timing Diagram

 The same clock controls the circuits that generate the control function and the destination register
 If two or more operations are to occur simultaneously, they are separated with commas

P: R3 R5, MARIR

Here, if the control function P = 1, load the contents of R5 into R3, and at the same time (clock), load the
contents of register IR into register MAR

Basic Symbols for Register Transfers

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

Common Bus System

The number of wires will be excessive if separate lines are used between each register and all
other register in the system.

• In a digital system with many registers, it is impractical to have data and control
lines to directly allow each register to be loaded with the contents of every possible
other registers

Bus: Bus is a path (of a group of wires) over which information is transferred, from any of
several sources to any of several destinations.

Common Bus: The more efficient scheme of transferring information between registers in a
multiple register organization configuration is called a Common bus system

Bus Structure Consists of a set of common lines, one for each bit of a register, through which
binary information is transferred one at a time. Control Signal determines which register is
selected by bus during register transfer.

Bus System For four register

Bus system is constructed with multiplexers; Multiplexers select the source register whose binary
information’s placed on the bus. The Bus consisted of four Multiplexers each having four input 0
to 4, and two selection inputs S1 and S0.there are four register 0 to 3.
Example: Output 1 of register A is connected to inputs 0 of MUX 1 because the input is labeled
as A1.

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

Bus Selection: The two selection lines S1 and S0 are connected to the selection inputs of all four
multiplexers. The selection line selects the four bits of one register and transfers them into 4 line
common bus.

S1 S0 Register Selected
0 0 A
0 1 B
1 0 C
1 1 D

Table.1 Function Table for Bus

The transfer of information from a bus into one of many destination register can be accomplished
by connecting the bus lines to the inputs of all destination registers and activating the load
control for particular register selected.

BUS C, R1BUS

Three- State Bus Buffers
 A bus can also be constructed with three state gates instead of multiplexers.
Inverter gate: An inverter is called a NOT gate

Fig.1 Inverter gate

 The inverter is a triangle, followed by a circle/bubble. That circle sometimes appears by itself,
and meansnegation.
 If we remove the circle… We'd have a buffer.
 In buffer the output is exactly the same as the input.

Fig. 2 Buffer gate

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

 Three state gate: A three state gate is a digital circuit that exhibits three states. Two
states are signals equivalent to logic 0 and logic 1.third state is a high- impedance state.
 High- impedance state Behaves like an open circuit, which means that the output is
disconnected and does not have logic significance.
 Tri –State Buffer

A tri-state buffer is a useful device that allows us to control when current passes through the
device, and when it doesn't

Fig .3 Tri-state buffers

Tri-state buffer has two inputs: a data input x and a control input c. The control input acts like a
valve. When the control input is active, the output is the input. That is, it behaves just like a
normal buffer. The "valve" is open.

When the control input is not active, the output is "Z". The "valve" is open, and no electrical
current flows through. Thus, even if x is 0 or 1, that value does not flow through

c x z

0 0 Z

0 1 Z

1 0 0

1 1 1

Table 1: Truth table describing the behavior of a active-high tri-state buffer

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

Construction of Bus System with Three State Buffer

The output of the four buffers are connected together to form a single bus line. The control inputs
to the buffers determine which of the four normal inputs will communicate with the bus line.

Note: No more than one buffer may be in the active state at any given time
No more than one control input is active at any given time (when we use a decoder)

Fig .4 Bus line with three state-buffers.

 When the enable input of the decoder is 0, all of its four outputs are 0 and the bus line is
in a high-impedance state because all four buffers are disabled.
 When the enable input is active one of the three state buffers will be active, depending on
the binary value in the select inputs of the decoder.

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

Micro operations
Microoperation is an elementary operation performed with the data stored in registers. Computer
system micro operations are of four types these are:
 Register transfer micro operations
 Arithmetic micro operations
 Logic micro operations
 Shift micro operations
The basic arithmetic micro operations are:

 Addition
 Subtraction
 Increment
 Decrement
 Shift.
The arithmetic microoperation defined by the statement:
R3 R1 +R2 Specifies the add operation
R3R1+R2’ +1 Specifies the subtract microoperation

The additional arithmetic micro- operations are:

 Add with carry

 Subtract with borrow
 Transfer/Load
Summary of Typical Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3

R3  R1 - R2 Contents of R1 minus R2 transferred to R3

R2  R2’ complements the contents of R2 (1’s

compliments)

R2  R2’+ 1 2's complement the contents of R2 (negate)

R3  R1 + R2’+ 1 subtraction

R1  R1 + 1 Increment

R1  R1 – 1 Decrement

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

 Binary Adder:

To implement the add microoperation with hardware ,a digital circuit that forms the arithmetic
sum of two bits and the previous carry is called a full adder.

The binary adder is constructed with full adder circuits connected in cascade with output carry
from one full adder connected to the input carry of the next full-adder.

Fig. 1 4-bit binary adder

The augends bit of A and the addend bits of B are designated by subscript numbers from right to
left with subscript 0 denoting the low order bit. The carry are connected in a chain through the
full adders. The input carry to the binary adder is C0 and the output carry is C4. The S output of
the full adders generates the required sum bits.

 Binary adder/subtractor:

The Subtraction (A-B) can be done by taking 2’s complements of B and adding it to A.

Fig 2 4-bit binary adder/subtractor

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

The addition and subtraction operation can be combined into one common circuit by including an
exclusive OR gate with each full adder. In 4-bit adder/subtractor there is a mode input M controls
the operation. When M=0 the circuit is an adder and when M=1 the circuits become subtractor.
Each exclusive-OR gate receives input M and one of the inputs of B. When M=0, we have B 
0=B. The full adder receives the value of B the input carry C0=0 and circuit performs A plus B.
When M=1 we have B  1 =B’ and C0=1.the B inputs are all complemented and a 1 is added
through the input carry, the circuits performs the A-B’+1.
 Binary Incrementer:

In 4-bit binary incrementer one of the inputs to half adder is connected to logic-1 and the other
inputs is connected to least significant bit of the number to be incremented. The output carry
from one half adder is connected to one of the inputs of the next higher order half adder.

The circuit receives the four bits from A0 to A3 adds one to it and generates the incremented
output in S0 to S3.The output carry C4 will be 1 only after incrementing binary 111.

Arithmetic Circuit:

The basic components of an arithmetic circuit are parallel adder. In 4 bit arithmetic circuit it has
four full adder circuits that constitute the 4 bit adder and four multiplexers for choosing different
operations.
 There are two 4 bit inputs A and B and a 4-bit output D.

 The four inputs from A go directly to the X inputs of the binary adder.

 Each of the four inputs from B are connected to data inputs of the multiplexers, The
multiplexers data inputs also receive the complement of B.
 The other two data inputs are connected to logic 0 and logic 1

 The four multiplexers are controlled by two selection inputs S1 and S0.

 The input carry Cin goes to the carry input of FA in the least significant position.

 The output of the binary adder is calculated from the following arithmetic sum:

D=A+Y+Cin

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

Arithmetic circuit function table:

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

Binary Decrementer:

In 4-bit binary decrementer one of the inputs to full adder is connected to logic-1 and the other
inputs is connected to least significant bit of the number to be decremented.

Logic microoperations specify binary operations for strings of bits stored in registers.

 Logic microoperations are bit-wise operations, i.e., they work on the individual bits of
data
 useful for bit manipulations on binary data

 useful for making logical decisions based on the bit value

There are, in principle, 16 different logic functions that can be defined over two binary
input variables

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

Hardware implementation of Logic Micro- operations:

The hardware implementation of logic microoperations requires that logic gates be inserted
for each bit or pair of bits in the registers to perform the required logic functions.

Logic circuit:

1. It consists of four gates and a multiplexer.

2. Each of four logic operations is generated through a gate that perform the logic .

3. The outputs of the gates are applied to the data inputs of the multiplexer.

4. The two selection input selects one of the data inputs of the multiplexers and directs
its value to output.

Fig 1: Logic Diagram

Table 2: Function Table

APPLICATIONS OF LOGIC MICROOPERATIONS

• Logic microoperations can be used to manipulate individual bits or a portions of a word

in a register
• Consider the data in a register A. In another register, B, is bit data that will be used to
modify the contents of A

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

1. SELECTIVE SET

• In a selective set operation, the bit pattern in B is used to set certain bits in A

1 1 0 0 A (t)
1010B
1 1 1 0 A (t+1) (A A + B) [t= clock time]

• If a bit in B is set to 1, that same position in A gets set to 1, otherwise that bit in A keeps
its previous value

2. SELECTIVE COMPLEMENT

• In a selective complement operation, the bit pattern in B is used to complement certain

bits in A

1 1 0 0 A (t)
1 0 1 0 ()
0 1 1 0 A (t+1) (A  A  B)

• If a bit in B is set to 1, that same position in A gets complemented from its original
value,otherwise it is unchanged

3. SELECTIVE CLEAR

• In a selective clear operation, the bit pattern in B is used to clear certain bits in A

1 1 0 0 A (t)
1010B
0 1 0 0 A (t+1) (A  A  B’)

• If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is unchanged

4. MASK OPERATION

• In a mask operation, the bit pattern in B is used to clear certain bits in A

1 1 0 0 A (t)
1010B
1 0 0 0 A (t+1) (A  A  B)
• If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is unchanged

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

5. CLEAR OPERATION

• In a clear operation, if the bits in the same position in A and B are the same, they
arecleared in A, otherwise they are set in A
1 1 0 0 A (t)

1010B

0 1 1 0 A (t+1) (A  A  B)

6. INSERT OPERATION

• An insert operation is used to introduce a specific bit pattern into A register, leaving the
other bit positions unchanged
• This is done as
– A mask operation to clear the desired bit positions, followed by
– An OR operation to introduce the new bits into the desired positions
– Example

» Suppose you wanted to introduce 1010 into the low order four bits of A:
1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)
» 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask

1101 1000 1011 0000 A (Intermediate)

0000 0000 0000 1010 Added bits

1101 1000 1011 1010 A (Desired)

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

SHIFT MICROOPERATIONS

 Are used for serial transfer of data. They can also be used with arithmetic, logic and
other data processing operations.

 In shift microoperations the content of a register can be shifted to left or the right.

 A right shift operation:

 A left shift operation:

 There are three types of shifts

 Logical shift

 Circular shift

 Arithmetic shift

Logical Shift
 In a logical shift the serial input to the shift is a 0.

 A right logical shift operation:

 A left logical shift operation:

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

 In a Register Transfer Language, the following notation is used

 shl : for a logical shift left

 shr : for a logical shift right

Examples: R2  shr R2

R3  shl R3

Circular Shift
 In a circular shift the serial input is the bit that is shifted out of the other end of the
register.

 A right circular shift operation:

 A left circular shift operation:

 In a RTL, the following notation is used

 Cil : for a circular shift left

 Cir: for a circular shift right

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

Examples: R2  cir R2, R3  cil R3

ARITHMETIC SHIFT

 An arithmetic shift is meant for signed binary numbers (integer)

 An arithmetic left shift multiplies a signed number by two

 An arithmetic right shift divides a signed number by two

 The main distinction of an arithmetic shift is that it must keep the sign of the
number the same as it performs the multiplication or division

 A left arithmetic shift operation:

 A right arithmetic shift operation:

• An left arithmetic shift operation must be checked for the overflow

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)

 In a RTL, the following notation is used

o ashl :for an arithmetic shift left

o ashr :for an arithmetic shift right

Examples:

 R2  ashr R2

 R3  ashl R3

HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS

 Information can be transferred to the register in parallel and then shifted to left and right.

 A clock pulse is needed for loading the data into register and another pulse is needed to
initiate the shift.

 The content of a register that has to be shifted is first placed onto a common bus whose
output is connected to the combinational shifter and shifted number is then loaded back
into the register.

 This requires only one clock pulse for loading the shifted value into the register.

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Computer Organization Architecture Unit-III Ms. Suman Singh
Assistant Professor (IT)
4 –bit combinational circuit shifter

A combinational circuit shifter can be constructed with multiplexers .The 4 –bit shifter has four
data inputs, A0 through A3 and four data outputs,H0 through H3.There are two serial inputs one
for shift left(IL) and other is for shift right(IR).When the selection inputs S=0 the input data are
shifted right .When S=1 the input data are shifted left.

Functional Table for 4-bit combinational circuit shifter

Select output
Input

S H0 H1 H2 H3

0 IR A0 A1 A2

1 A1 A2 A3 IL

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COA BCA-III M1 Prepared By: Ms. Suman Singh
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IITM

Basic Computer Organizations and Design: Instruction Codes, Computer Registers,

Instruction Cycle, General Register Organization, Stack Organization, Instruction
Formats, Addressing Modes

Basic Computer Organizations and Design

INTRODUCTION

• Every different processor type has its own design (different registers, buses,
microoperations, machine instructions, etc)

• Modern processor is a very complex device

• It contains

– Many registers

– Multiple arithmetic units, for both integer and floating point calculations

– The ability to pipeline several consecutive instructions to speed execution

– Etc.

• However, to understand how processors work, we will start with a simplified processor
model

THE BASIC COMPUTER

• The Basic Computer has two components, a processor and memory

• The memory has 4096 words in it

– 4096 = 212, so it takes 12 bits to select a word in memory

• Each word is 16 bits long

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
INSTRUCTIONS

• Program

– A sequence of (machine) instructions

• Instruction

– A group of bits that tell the computer to perform a specific operation (a sequence
of micro-operation)

• The instructions of a program, along with any needed data are stored in memory

• The CPU reads the next instruction from memory

• It is placed in an Instruction Register (IR)

• Control circuitry in control unit then translates the instruction into the sequence of
microoperations necessary to implement it

INSTRUCTION FORMAT

• A computer instruction is often divided into two parts

– An opcode (Operation Code) that specifies the operation for that instruction

– An address that specifies the registers and/or locations in memory to use for that
operation

• In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit
to specify which memory address this instruction will use

• In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0:
direct addressing, 1: indirect addressing)

• Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits
for the instruction’s opcode

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
• The address field of an instruction can represent either

– Direct address: the address in memory of the data to use (the address of the
operand), or

– Indirect address: the address in memory of the address in memory of the data to
use

• Immediate instruction

- A computer program instruction, part of which contains the actual data to be

operated upon, rather than the address of that data.

• Effective Address (EA)

– The address, that can be directly used without modification to access an operand
for a computation-type instruction, or as the target address for a branch-type
instruction

Computer instructions are stored in memory locations and are executed sequentially one at a
time. The control read an instruction from a specific address in memory and executes it.

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
Computer Registers:

 A processor has many registers to hold instructions, addresses, data, etc

 The processor has a register, the Program Counter (PC) that holds the memory address of
the next instruction to get
– Since the memory in the Basic Computer only has 4096 locations, the PC only
needs 12 bits
 In a direct or indirect addressing, the processor needs to keep track of what locations
in memory it is addressing: The Address Register (AR) is used for this
– The AR is a 12 bit register in the Basic Computer
 When an operand is found, using either direct or indirect addressing, it is placed in
the Data Register (DR). The processor then uses this value as data for its operation
 The Basic Computer has a single general purpose register – the Accumulator (AC)
 The significance of a general purpose register is that it can be referred to in
instructions
– e.g. load AC with the contents of a specific memory location; store the contents of
AC into a specified memory location
 Often a processor will need a scratch register to store intermediate results or other
temporary data; in the Basic Computer this is the Temporary Register (TR)
 The Basic Computer uses a very simple model of input/output (I/O) operations
– Input devices are considered to send 8 bits of character data to the processor
– The processor can send 8 bits of character data to output devices
 The Input Register (INPR) holds an 8 bit character gotten from an input device
 The Output Register (OUTR) holds an 8 bit character to be send to an output device

Registers in the Basic Computer

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COA BCA-III M1 Prepared By: Ms. Suman Singh
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IITM
List of basic computer registers

Computer Instructions
 The basic computer has three instruction formats .each format is of 16 bits. The operation
part contain the three bits, 12 bit for address of operand n 1 bit for addressing mode or
address bit. These are:

1. Memory reference instruction: A memory reference instruction uses 12 bits to specify

an address and one bit to specifies the addressing mode I.I is equal to 0 for direct
addressing and to 1 for indirect address. Opcode value is from 000 to 110.

2. Register -reference instruction: The register reference instructions are recognized by

the operation code 111 with a 0 in the left most bit of the instruction. Register reference
instruction specifies an operation on AC register.

3. Input –output instruction: An input –output instruction does not need a reference to
memory and recognized by the operation code 111 with a 1 in the 15th bit of the
instruction.

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
 The type of instruction is recognized by the computer control from the four bits in
Position 12 through 15 of the instruction.

 The total number of instructions chosen for the basic computer is equal to 25.

BASIC COMPUTER INSTRUCTIONS:

INSTRUCTION SET COMPLETENESS:

A computer should have a set of instructions so that the user can construct machine language
programs to evaluate any function that is known to be computable.

• Instruction Types

 Functional Instructions

- Arithmetic, logic, and shift instructions

Eg: - ADD, CMA, INC, CIR, CIL, AND, CLA

 Transfer Instructions

- Data transfers between the main memory and the processor registers

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Assistant Professor (IT)
IITM
Eg: - LDA, STA

 Control Instructions

- Program sequencing and control

Eg - BUN, BSA, ISZ

 Input/Output Instructions

- Input and output

Eg: INP, OUT

INSTRUCTION CYCLE

• In Basic Computer, a machine instruction is executed in the following cycle:

1. Fetch an instruction from memory

2. Decode the instruction

3. Read the effective address from memory if the instruction has an indirect address

4. Execute the instruction

• After an instruction is executed, the cycle starts again at step 1, for the next instruction

• Note: Every different processor has its own (different) instruction cycle

 Fetch and Decode:

Initially the program counter PC is loaded with the address of the first instruction in the program.
After each clock pulse SC is incremented by one so that the timing signals go through T0, T1, T2
and so on the microoperations for the fetch and decode phase can be specified by the following
register transfer statements.

T0: AR PC (S0S1S2=010, T0=1)

T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)

T2: D0, . . . , D7  Decode IR (12-14), AR  IR (0-11), I  IR (15)

 DETERMINE THE TYPE OF INSTRUCTION

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COA BCA-III M1 Prepared By: Ms. Suman Singh
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IITM
The timing signal that is active after the decoding is T3 .During T3 the control unit determine
the type of instruction that was just read from memory.

Decoder output D7 is equal to 1 if the operation code is equal to binary 111, if D7=1 the
instruction must be a register reference or input-output type, If D7=0 the operation code must
one of the other seven values 000 through 110 specifying a memory reference instruction.

Instruction Cycle Flow Chart

The three instruction types are subdivided into four separate paths The selected operation is
activated with the clock transition associated with timing signal T3.This can be symbolized as
follows:

D'7IT3: AR M [AR]

D'7I'T3: Nothing
D7I'T3: Execute a register-reference instruction.
D7IT3: Execute an input-output instruction.
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CENTRAL PROCESSING UNIT

The computer that performs the bulk of data processing operations is called the central
processing unit and referred as CPU.
The CPU is made up of three major parts. These are:
1. Register set: stores intermediate data used during the execution of the instructions.
2. ALU: performs the required micro operations for executing the instructions.
3. Control unit: supervises the transfer of information among the registers and instructs the
ALU to which operation to perform

General register organization

 The output of each register is connected to two multiplexers (MUX) to form the two
buses A and B.
 The selection lines in each multiplexer select one register or the input data for the
particular bus.
 The A and B buses form the inputs to common arithmetic logic unit (ALU).
 The operation selected in the ALU determines the arithmetic or logic microoperation that
is to be performed.
 The result of the microoperation is available for output data and also goes into the inputs
of all registers.
 The register that receives the information from the output bus is selected by a decoder.
 The control unit that operates the CPU bus system directs the information flow through
the registers and ALU by selecting the various components in the system.
 For example: R1<-R2+ R3

The control must provide binary selection variables the following selector inputs:
1. MUX A selector (SEL A): To place the content of R2 into bus A.
2. MUX B selector (SEL B): To place the content of R3 into bus B.
3. ALU operation selector (OPR): To provide the arithmetic addition A+B.
4. Decoder destination selector (SEL D): To transfer the content of the output bus into R1.

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM

Control Variable: Control word is a 14-binary selection inputs in the unit and their combined
value specifies a control word.
Three fields contain three bits each and one field has five bits.
Three bits of SELA select a source register for the A input of the ALU
* The three bits of SELB select a register for the b input of the ALU.
* The three bit of SELD selects a destination register using the decoder.
* The five bits of OPR selects one of the operations in the ALU.

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
Stack Organization
 A stack is a storage device that stores information, the item stored last is the first
retrieved (LIFO).
 The stack in digital computers is essentially a memory unit with an address register.
 The register that holds the address for the stack is called a stack pointer (SP).
 The two operation of stack are the insertion and deletion of items.
 The operation of insertion is called push and the deletion operation is pop
 Push and pop operations are simulated by incrementing or decrementing the stack pointer
register.

Register Stack

 A stack can be placed in a portion of a large memory organized as a collection of a

finite number of memory words or registers.
 In a 64 word stack, the stack pointer contains 6 bits because 26=64.
 SP has only six bits it cannot exceed a number greater than 63.
 When 63 is incremented by 1 the result is 0 and when 000000 is decremented by 1 the
result is 111111.

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
• The one bit register FULL is set to 1 when stack is full
• The one bit register EMPTY is set to 1when the stack is empty of items.
• DR is the data register holds the binary data to be written or read of the stack
Push operations: initially SP is cleared to 0, EMPTY is set to 1 and FULL is cleared to 0

POP Operation:

A new item is deleted from the stack if the stack is not empty if EMPTY =0.the pop operation
consists of the following microoperations

Memory Stack

 A stack can exist as a standalone unit.

 The implementation of stack in the CPU is done by assigning a portion of memory to
stack operation and using a processor register as a stack pointer
 Computer memory partitioned into three segments:
 Program
 Data
 Stack

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
Three register are connected to a common address bus.PC is used for fetch phase, AR is used
during execution and SP is used to push or pop items into or from the stack.

• The initial value of SP is 4001 and the stack grows with decreasing addresses.
• First item stored in stack at 4000.

Push operation in memory stack:

Pop operation in memory stack : A new item is deleted with a pop operation as follows

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
Note: most computers do not provide hardware to check for stack overflow or underflow.
Stack Limit:
 The stack limit can be checked by using two processor registers one holds the upper limit
(3000)and other to holds the lower limit (4001).
 After push operation SP is compared with the upper limit register and after a pop
operation SP is compared with lower limit register.

Instruction Formats
 A Computer will usually have a variety of instruction code formats.
 It is the function of the control unit within the CPU to interpret each instruction code and
provide the necessary control functions needed to process the instruction.
 The Bit of the instruction is divided into groups called fields. The most common fields in
instruction format are:
 Operation code field that specifies the operation to be performed.
 Address field that designates a memory address or a processor register.
 Mode field that specifies the way the operand or the effective address is determined.
 Operations specified by computer instructions are executed on some data stored in
memory or processor register.
 Operands residing in memory are specified by their memory address
 Operands residing in processor registers are specified with a register address.
 Computers may have instructions of several different lengths containing varying number
of address.
 The number of address fields in the instruction format of a computer depends on the
internal organization of its register.
 Most of the computers are one of the following types of CPU organizations:
1. Single Accumulator Organization
2. General Register Organization
3. Stack organization

Three Address Instructions

Computer with three address instruction formats can use each address fields to specify either a
processor register or memory operands.
Evaluate X= (A+B)*(C+D)

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 COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
Two Address Instructions
Two Address Instructions are the most common in commercial computers. The program to
evaluate X= (A+B)*(C+D) as follows

One Address Instructions

One address instructions use an implied accumulator register for all data manipulation.. The
program to evaluate X= (A+B)*(C+D) as follows
result will store in accumulator register rather than main
memory

Zero Address Instructions

A stack organized computer does not use an address field for the instructions ADD and MUL.

The PUSH and POP instructions needed an address field to specify the operand that
communicates with the stack

no address field
stack organized
computer use
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zero address instruction
instruction specify data itself
COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
Addressing Modes
The addressing mode specifies a rule for interpreting or modifying the address field of the
instruction before the operand is actually referenced. Addressing mode techniques is use for the
purpose of:
1. To give programming versatility
2. To reduce the number of bits in the addressing field of the instruction.

Mode Field: The mode field is used to locate the operands needed for the operation. There may
or may not be an address field in the instruction. The instruction may have more than one address
field.

In a basic computer there are following types of addressing mode these are:

1. Implied Mode:

In this mode the operands are specified implicitly in the definition of the
instruction.For example (complement accumulator) is an implied mode instruction
because the operand in the accumulator register is implied in the definition of
instruction. All register reference instructions that use an accumulator are implied
mode instructions. Zero address instructions in a stack organized computer are
implied mode instructions since the operands are implied to be on the top of the stack.

2. Immediate Mode:

In this mode the operand is specified in the instruction itself. An immediate

instruction has an operand field rather than an address field. The operand field
contains the actual operand.

3. Register Mode :

The address field of an instruction may specify either a memory word or processor
register. When the address field specifies a processor register, the instruction is said
to be in the register mode. In the mode the operands are in registers that reside within
the CPU

4. Register Indirect Mode:

In this mode the instruction specifies a register in the CPU whose contents give the
address of the operand in memory.The selected register contains the address of the
operand rather than the operand itself. The advantage of a register indirect mode
instruction is that the address field of the instruction uses fewer bits to select a
register than would have been required to specify a memory address directly.

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM
5. Auto increment or Decrement Mode:

This is similar to the register indirect mode except that the register is incremented or
decremented (after or before) its value is used to access memory. When the address
stored in the register refers to a table of data in memory, it is necessary to increment
or decrement the register after every access to the table, can be achieved by using the
increment or decrement instruction.

6. Direct Address Mode:

In this mode the effective address is equal to the address part of instruction. The
operand resides in memory and its address is given directly by the address field of the
instruction.

7. Indirect Address Mode:

In this mode the address field of the instruction gives the address where the effective
address is stored in memory.

8. Relative Address Mode:

In this mode the content of the program counter is added to the address part of the
instruction in order to obtain the effective address. When this number is added to the
content of the program counter, the result produces an effective address whose
position in memory is relative to the address of the next instruct on. Relative
addressing is often used with branch type instructions.

9. Indexed Addressing Mode:

The index register is a special CPU register that contains an index value. The address
field of the instruction defines the beginning address of data array in memory. The
index register can be incremented to consecutive operands. In this mode the content
of an index register is added to the address part of the instruction to obtain the
effective address.

10. Base Register Addressing Mode:

A base register is assumed to hold a base address and the address field of the
instruction gives a displacement relative to this base address. In this mode the content
of a base register is added to the address part of the instruction to obtain the effective
address.

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COA BCA-III M1 Prepared By: Ms. Suman Singh
Assistant Professor (IT)
IITM

Numerical Example for Addressing Modes:

To show the difference between the various modes we will take the given figure as an example.
The two word instruction at address 200 and 201. The PC has the value 200 for fetching this
instruction. The content of processor register R1 is 400. Index register XR has content 100. AC
receives the operand after the instruction is executed.

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