International Journal of Speech Technology

https://doi.org/10.1007/s10772-021-09800-8

Design and comparative analysis of on‑chip sigma delta ADC for signal
processing applications
P. A. Harsha Vardhini1 · Madhavi Latha Makkena2

Received: 8 June 2020 / Accepted: 2 January 2021

© The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature 2021

Abstract
Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter
plays a vital role in modern digital signal processing applications. Various signal processing applications incorporated sigma
delta ADC among different analog to digital converters because of its digital dominant architecture. This paper presents the
design of a low pass continuous time sigma delta analog to digital converter on-chip architecture with a very few passive
components connected externally to FPGA suitable for signal processing applications, wireless application, sonar and radar
beamforming. Schematic level architecture of high speed comparator working at a differential swing which is not allowed by
FPGA standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance
and power is analyzed. High performance comparator schematic is designed as on-chip continuous-time sigma-delta analog
to digital converter architecture. SPICE simulations are carried out to verify the maximum input frequency for given RC
values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL
logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with
mixed signal simulations at different stages are performed. Power and performance analysis are carried out using h-Spice
and questasim simulations. schematic level architecture of a high speed comparator at a differential swing of 1.65 ± 1.5 V
which is not allowed by standard differential pads is designed. Analysis illustrates that proposed on-chip continuous-time
sigma-delta analog to digital converter exhibits a sampling rate of 400 MHz designed with high speed comparator with
varied differential swing. Power analysis resulted with 1.86 mW for an input signal of 1 MHz. Optimal filtering is achieved
with total decimation of 400, out of which the decimation of 100 is achieved by CIC filter and PFIR filter achieves remaining
decimation factor of 4. Output data rate of 1 MHz with a dynamic range of 72 dB is achieved with less bill of material that
suites for signal processing applications.

Keywords Sigma delta ADC · Differential I/O · LVPECL · Comparator · Optimum filtering

1 Introduction technology, digital signal processing took over analog pro-

cessing. The processing of signal in digital system is done
Signal processing represents, transforms, and manipulates a using digital computation. In contrast to analog systems,
signal and the signal information. Signal processing technol- the digital systems provide better reliability and resolution
ogy used before 1960s was Continuous Time (CT) analog at a low cost. Digital systems became area efficient circuits
technology. But noise comes into existence in processing with growth of silicon technology. Digital systems are less
a signal using analog technology. Signal processing on susceptible to noise and they add an additional feature of
analog circuits are even complex. But the advancement in IC programmability (Brandt 1991).
Evolution of Very Large Scale Integration (VLSI)
circuits led to the implementation of high performance
* P. A. Harsha Vardhini and high resolution architectures. Digital signal process-
[email protected] ing system found its application in every field of daily
1
life viz., consumer electronics, industrial applications,
Department of ECE, Vignan Institute of Technology
and Science, Deshmukhi, Telangana, India speech synthesis. Digital signal processing systems need
2
the real-time occurring signals to be converted into digital
Department of ECE, JNTUH, Hyderabad, Telangana, India

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 International Journal of Speech Technology

form for processing and vice versa to get the analog out- • Utilization of the silicon by the ADCs.
put from digital processing system. Hence data convert- • As the converters are placed outside the processing sys-
ers, Analog to Digital Converters (ADCs) and Digital to tem they require an interface, like SPI, I2C, etc., to get
Analog Converters (DACs) are required to interface the connected with processing system
real-time analog world and the digital processing systems • Protocol is to be followed for interfacing
as in Fig. 1. Interfacing the digital domain with the analog • Synchronization in multi channel ADC applications
world became the bottleneck for the designers for the pro-
cessing system as lot of filtering circuits, complex conver- Artigas et al. (2009) research proposed with active
sion procedures, noise rejection and elimination circuits component digital only SD-ADC for the digitization of
are involved. the parameters related to the power supply describing the
dynamic comparator analysis that is carried out by imple-
menting the negative feedback around the inverter. How-
1.1 Need for sigma delta ADC digital architecture ever, in practical FPGA circuits, possible threshold level
variations of inverter gate with temperature, ageing etc. are
ADCs perform the conversion of analog to digital by dif- not considered. Such unpredictable variations degrade the
ferent methods. By 1960s, new architectures aroused with overall output of modulators. In low V ­ dd and high velocity
the replacement of vacuum tubes by transistor and later by switches these differences become more important. In addi-
IC technology. Among various Nyquist ADCs, parallel or tion, an FPGA input pad is used as a comparator, the hys-
flash ADC is known for its high speed, Successive approxi- teresis of which may produce unwanted device poles which
mation ADC gives better accuracy but at moderate speeds. may cause errors in the operation of signal and noise transfer
Oversampling ADCs trade digital signal processing com- (Sousa et al. 2004). The research in Palagiri et al. (2012)
plexity for relaxed requirements on the analog components emphasizes the use of an LVDS input buffer as compara-
compared to Nyquist rate ADCs. Oversampling ADCs or tor on another all digital implementation. In the context of
sigma delta architecture based on oversampling and noise passive analog and FPGA/ASIC based SD-ADC, Jacomet
shaping principles monopolized most of the applications et al., Fabio Sousa et al., and Artigas works are surveyed and
in the last two decades (Norsworthy et al. 1996; Jacomet the work proposed here describes the simulation of passive
et al. 2004). The approach earlier by the VLSI researchers analog only SD-ADC with two high speed differential pins in
is towards Application Specific Integrated Circuit (ASIC) Xilinx Spartan and Virtex family FPGAs. FPGA differential
implementation and the analog VLSI synthesis is not auto- I/Os perform as 1 bit comparator and the digital analysis of
mated. Research in the direction of digital implementation the same can be done with spice simulations (Artigas et al.
of the ADC is being carried out (Harsha Vardhini et al. 2009; Sousa et al. 2004). FPGA configurable logic blocks
2012). Field Programmable Gate Array (FPGA) imple- can be programmed to achieve the digital block modules that
mentations of sigma delta ADC competed with the ASIC perform the operation of filtering and decimation (Palagiri
implementations evolving new architectures. et al. 2012). 7 series FPGAs like ZYNQ, PYNQ with AMS
ASIC and FPGA implementations of sigma delta archi- technology is the motivation for the present research in the
tectures allows the designers in realizing an ADC deliv- upcoming mixed signal IP technologies that provide flex-
ering reasonably good performance. But both implemen- ibility for general purpose analog interface (Harsha Vardhini
tations presented various limitations. Some of them are et al. 2013; Palagiri et al. 2013b).
listed below. Xilinx FPGAs are chosen due to the availability of soft-
ware and tools for the simulation. However, the method-
ologies presented here are technology-independent, and can
be applied to any FPGAs and ASIC category. The perfor-
mance benchmarks are given with FPGAs made from 90 nm
Analog Signal
Analog sensor
input Signal
Conditioning & technology, widely used in today’s systems. The approach
Analog to
Digital presented in this paper presents the design of area and cost
Digital
Signal
efficient sigma delta ADC with optimum performance. The
Processing second section illustrates the design of low-pass on-chip
Digital to Analog continuous-time sigma-delta ADC. Power analysis of dif-
Analog Signal
Conversion &
Output signal
ferential I/O is carried out and tabulated in third section
conditioning and fourth section illustrate the design of high speed com-
parator suitable for proposed architecture. The fifth section
Fig. 1  Interfacing physical world with digital signal processing sys- concludes the proposed work suitable for SONAR and many
tem wireless communication applications.

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International Journal of Speech Technology

Fig. 2  Proposed on-chip ADC FPGA

on Xilinx FPGA

Analog Signal Differential

I/O PIN Configurable
Logic Blocks
(CLB)
R Differential
Digital Section

12- bit output

I/O PIN
C
Analog Down
Low Section conversion &
Pass Decimation
filter Differential
I/O PIN

2 Design of low‑pass on‑chip Table 1  Maximum input frequency with R = 100 Ω; C = 1 pf

continuous‑time sigma‑delta ADC Differential Simulation time Clock speed Max. input
on FPGA swing (µV) (nano secs) (MHz) frequency
(MHz)
Proposed sigma delta ADC architecture suitable for signal 300 200 200 10
processing applications is depicted in Fig. 2. It is a 12-bit 200 400 100 5
high performance first order sigma delta ADC implemented 150 200 50 5
on FPGA to overcome the limitations described in the above
section.
This work makes use of Xilinx FPGA to design sigma
delta ADC. Conventional ASIC sigma delta modulator block Table 2  Maximum input frequency with R = 100Ω; C = 10 pf
is implemented here in this work with LVPECL I/O of FPGA Differential Simulation time Clock speed Max. input fre-
and a resistor R and capacitor C are placed outside which are swing (µV) (nano secs) (MHz) quency (MHz)
connected to the I/O, represents first order CT sigma delta
300 200 200 5
modulator. Digital section following the modulator for down
200 200 100 5
conversion and decimation process is implemented by the
200 400 100 4
Configurable Logic Blocks (CLBs) of FPGA.
200 600 100 1
150 400 5 5

2.1 Selection of R&C

The external RC product decides the maximum input fre- Table 3  Maximum input frequency with R = 100Ω; C = 100pf
quency. Simulations are carried out to verify the maximum Differential Simulation time Clock speed Max. input
input frequency for given RC value. Resistor value R is swing (µV) (nano secs) (MHz) frequency
fixed, as the impedance matching needs 100 Ω termination (MHz)
and C is varied. 300 200 200 10
The maximum input signal frequency for LVPECL differ- 200 200 200 5
ential I/Os with various capacitor values for different voltage 150 400 400 4
swings are listed in following tables. Table 1 illustrates the
maximum input frequency at a various differential swing
with 1 pf capacitor. Tables 2 and 3 illustrates the maximum
input frequency at various input swings for LVPECL I/O 3 Power analysis of LVPECL comparator
with a capacitor of 10 pf and 100 pf respectively. Table 4
tabulates the same for a capacitance of 1000 pf or 1 nf. From Conventional sigma delta ADC requires comparator with
Fig. 3, it can be interpreted that LVPECL with higher clock faster dynamic response and stable operating conditions.
speed is suitable for high speed applications.

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 International Journal of Speech Technology

Table 4  Maximum input frequency with R = 100Ω; C = 1000 pF or 1 Table 5  LVPECL I/O power analysis at various differential swings
nf
Differential swing (µV) Speed (MHz) Power (mW)
Differential Simulation time Clock speed Max. input
swing (µV) (nano secs) (MHz) frequency 300 200 1.86
(MHz) 300 170 1.65
200 100 1.80
300 200 200 10
200 88 1.55
200 200 200 5
150 50 1.77
150 400 400 4
150 38 1.43

200
Max operaing speed (MHz)

Table 6  Power analysis of I/O standards at various differential swings

150
Differential Speed (MHz) Power (mW)
swing (µV)
100 LVPECL LVPECL LVDS HSTL-II
LVDS 300 200 1.867 Not working Not working
50
HSTL-II 180 1.701 1.84 not working
0 170 1.6568 1.823 2.13
150
200 100 1.8 Not working Not working
175 200
250 90 1.683 1.79 Not working
300
88 1.5595 1.7817 2.133
Voltage Swing(µV) 150 50 1.77 Not working Not working
40 1.491 1.73 Not working
Fig. 3  Speed versus swing- various differential I/Os 38 1.4378 1.7215 2.15

FPGA differential pins can be used as comparator. Xilinx

FPGA families supports various differential I/O standards
2.5
Speed vs Power
2
viz., Low Voltage Differential Signaling (LVDS), mini
Power (mW)

LVDS, Bus LVDS, High Speed Transceiver Logic (HSTL), 1.5

Reduced Swing Differential Signaling (RSDS), Low Volt- LVPECL
1
age Positive Emitter coupled Logic (LVPECL), Transition LVDS
Minimized Differential Signaling (TMDS), Point-to-Point 0.5
HSTL-II
Differential signaling (PPDS), so on (Harsha Vardhini and 0
Madhavi Latha 2015; Palagiri et al. 2013a). The selected 38 40
FPGA is Spartan-6 family which supports several differ- 50 88
90 100
170 180
ential signal types. Among the differential I/Os LVPECL 200
is selected due to their fast switching speeds. The analog 150 μV 200 μV 300 μV

part and the LVPECL differential I/O simulations are car- Speed(MHz)
ried out with H-SPICE simulator. Xilinx provided Spartan
6 I/O pad and package SPICE models are used for this Fig. 4  Speed versus power
simulation (Vardhini 2016). By applying various differen-
tial swings at the input to LVPECL, the performance and
power is analyzed. Differential I/Os h-spice simulations power and performance analysis of LVPECL, LVDS and
are carried out and the results are illustrated in Table 5. HSTL-II differential I/Os.
Power analysis is carried out with LVPECL logic family
based differential buffers along with external RC circuit
for realizing 1-bit sigma delta ADC. The results are tabu- 4 Design of high speed comparator
lated below as in Table 6 and it reports less than 1.9 mW
power, which is comparable with typical low power ADC Using a normal FPGA I/O, limits the swing of the applied
requirements. Table 6 depicts that LVPECL works at a input. nm-CMOS comparator with varied differential swing
maximum clock speed of 200 MHz and it fails to operate is designed. This section proposes a schematic level architec-
at a higher frequency above 200 MHz. Figure 4 depicts the ture of a high speed comparator which works at a differential

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International Journal of Speech Technology

swing of 1.65 ± 1.5 V which is not allowed by standard dif- 4.1 CIC based decimator with 1‑bit input at these
ferential pads. For the future FPGAs this architecture can high rates in digital fabrics
be implemented for high performance on-chip architecture.
Comparator schematic as shown in Fig. 5 comprised of pre- CIC architecture is as shown in Fig. 6 where by the down
amplifier, decision and output buffer stages. A D-flipflop and sampling by a factor of D is carried out by integrators before
a digital buffer follow the comparator stage. Digital buffer comb sections. A total decimation of 400 is achieved out of
ensure to produce the logic levels compatible to digital cir- which the decimation of 100 is achieved by CIC filter and
cuits. According to level 49 simulations, schematic extracted PFIR filter achieves remaining factor of 4. Proposed sigma
netlist of 130 nm model files are simulated and the results delta ADC top level functionality is verified by Analog
illustrate that this comparator works at 400 MHz clock. Mixed Signal VHDL. The analog and digital sections and

TW = 1.5u
Mp3 W = 1.5u
Vbiasp L = 250n
2.5v
TW = 1.5u
NF = 1 W = 1.5u Mp5 TW = 1.5u TW = 1.5u TW = 1.5u
M = 1 L = 250n Mp4 W = 1.5u Mp6 W = 1.5u Mp7 W = 1.5u
2.5v
L = 250n L = 250n L = 250n
NF = 1 2.5v 2.5v 2.5v
M = 1 NF = 1 NF = 1 NF = 1
M = 1 M = 1 M = 1
TW = 1.5u TW = 1.5u
Mp1 W = 1.5u W = 1.5u Mp2
Vp Vm
2.5v
L = 250n L = 250n
2.5v
Vop Vom
NF = 1 NF = 1
M = 1 M = 1
TW = 1.5u TW = 1.5u TW = 1.5u TW = 1.5u TW = 1.5u TW = 1.5u
Mn5 W = 1.5u W = 1.5u Mn6 W = 1.5u Mn8 W = 1.5u Mn9 Mn10 W = 1.5u W = 1.5u Mn11
Vp L = 250n L = 250n Vm L = 250n L = 250n L = 250n L = 250n
2.5v 2.5v 2.5v 2.5v 2.5v 2.5v
TW = 1.5u TW = 1.5u TW = 1.5u TW = 1.5u NF = 1 NF = 1 NF = 1 NF = 1 NF = 1 NF = 1
W = 1.5u Mn2 Mn1 W = 1.5u W = 1.5u Mn4 Mn3 W = 1.5u M = 1 M = 1 M = 1 M = 1 M = 1 M = 1
L = 250n L = 250n L = 250n L = 250n
2.5v 2.5v 2.5v 2.5v
NF = 1 NF = 1 NF = 1 NF = 1 TW = 1.5u
M = 1 M = 1 M = 1 M = 1 Mn7 W = 1.5u
Vbiasn L = 250n
2.5v
TW = 1.5u
NF = 1 Mn12 W = 1.5u
M = 1 L = 250n
2.5v
NF = 1
M = 1

TW = 1.5u
Mp20 W = 1.5u
Vbiasp L = 250n
2.5v
NF = 1
M = 1

clk_bar
TW = 1.5u TW = 1.5u
Mp18 W = 1.5u W = 1.5u Mp19 TW = 1.5u TW = 1.5u TW = 1.5u TW = 1.5u TW = 1.5u
Mp22

L = 250n L = 250n Mp21 W = 1.5u Mp24 W = 1.5u Mp25 W = 1.5u Mp26 W = 1.5u Mp27 W = 1.5u
2.5v

2.5v 2.5v
L = 250n L = 250n L = 250n L = 250n L = 250n
NF = 1 NF = 1 2.5v 2.5v 2.5v 2.5v 2.5v
M = 1 M = 1 NF = 1 NF = 1 NF = 1 NF = 1 NF = 1
M = 1 M = 1 M = 1 M = 1 M = 1
M TW
NF W= =1 1.5u

L = 250n
W = 1.5u
TW = 1.5u

DFF_out
= 1= 1.5u

L = 250n

DFF_out_buf
NF = 1
M = 1

TW = 1.5u TW = 1.5u TW = 1.5u

clk_bar TW = 1.5u TW = 1.5u TW = 1.5u TW = 1.5u
W = 1.5u Mn22 Mn23 W = 1.5u Mn24 W = 1.5u Mn27 W = 1.5u Mn28 W = 1.5u Mn29 W = 1.5u Mn30 W = 1.5u
L = 250n L = 250n L = 250n L = 250n L = 250n L = 250n L = 250n
Mn25

2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v

2.5v

Mp23

NF = 1 NF = 1 NF = 1 NF = 1 NF = 1 NF = 1 NF = 1
2.5v

M = 1 M = 1 M = 1 M = 1 M = 1 M = 1 M = 1

clk
M TW
NF W= =1 1.5u

L = 250n
W = 1.5u
TW = 1.5u
= 1= 1.5u

L = 250n

NF = 1
M = 1
Mn26

2.5v

clk

Fig. 5  Comparator schematic

Fig. 6  Digital section Integrators Comb Sections

I I I I D C C C C

(a)CIC filter

Z-1 Z-M

+ +
(b) Basic Integrator (c) Basic Comb Section

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 International Journal of Speech Technology

Table 7  Comparison of results of proposed SD-ADC with Sousa et al. (2004)

Parameter Sousa et al. (2004) Proposed SD ADC Proposed ADC with high speed comparator

OSR 1024 400 400

Input Signal 15 kHz 1 MHz Up to 500 kHz (for D = 400)
Up to 2 MHz (for D = 100)
FPGA family Altera Xilinx Xilinx
Spartan Spartan
Signaling Technology LVDS LVPECL Comparator with varied differential swing
Standard Operating Range 1.0 to 1.4 0.9 to 1.5 V (1.2 ± 0.3 V) 1.65 ± 1.5 V
Unconventional swing
Sampling rate 50 MHz 200 MHz 400 MHz
Analog Section Power – 1.86 mW 7.7 mW
Output data rate 48.8 kHz 500 kHz 1 MHz with 72 dB DR

mixed signal simulations at different stages are carried out nodes (Hu et al. 2019; Harsha Vardhini and Murali Mohan
and compared with the work contributed by Sousa et al. Babu 2020). The proposed on-chip ADC is suitable for wire-
(2004) using FPGA I/O pads with LVDS as a comparator less transceivers with required bandwidth access. IoT based
for SD-ADC in Table 7. wireless applications implemented with arduino, raspberry
Power and performance analysis are carried out using pi or any controller boards with ‘n’ number of sensor and
h-Spice and questasim simulations. schematic level archi- ADCs can be replaced with the proposed on-chip ADC
tecture of a high speed comparator at a differential swing of FPGA architecture (Babu and Harsha Vardhini 2020; Harsha
1.65 ± 1.5 V which is not allowed by standard differential Vardhini et al. 2020; Vasishta et al. 2020).
pads is designed. Analysis illustrates that proposed on-chip
continuous-time sigma-delta analog to digital converter
exhibits a sampling rate of 400 MHz designed with high 5 Conclusion
speed comparator with varied differential swing. Power anal-
ysis resulted with 1.86 mW for input signal of 1 MHz with On-chip sigma delta ADC with the Xilinx FPGA differential
output data rate of is 1 MHz with a dynamic range of 72 dB. I/O i.e., LVPECL is analyzed and the on-chip architecture is
simulated with the proposed comparator design. schematic
4.2 Applications level architecture of a high speed comparator at a differen-
tial swing of 1.65 ± 1.5 V which is not allowed by standard
On-chip sigma-delta ADC architecture with FPGA differen- differential pads is designed. Analysis illustrates that pro-
tial I/Os find its applications including low cost instrumenta- posed ADC exhibits a sampling rate of 400 MHz designed
tion, audio, SONAR and sensor networks. Among several with high speed comparator with varied differential swing.
applications the sigma delta ADC architectures are highly Power analysis resulted 1.86 mW for input signal of 1 MHz.
suitable for many wireless applications where ADC is a req- Optimal filtering is achieved with total decimation of 400,
uisite and the count of ADCs needed by the application is out of which the decimation of 100 is achieved by CIC filter
more in number. Wireless applications, RADAR, SONAR and PFIR filter achieves decimation factor of 4. Output data
applications can be easily benefitted with the proposed rate of is 1 MHz with a dynamic range of 72 dB. SONAR/
architecture due to the advantages over existing categories RADAR applications utilizing the maximum silicon area for
(Palagiri et al. 2016; Bindu Tushara and Harsha Vardhini analog to digital conversion of the real time signals can be
2015). Firstly, SONAR beamforming applications require easily achieved by replacing the proposed architecture with
digitization of SONAR signals coming from multiple sen- the existing FPGA architecture differential I/Os. Proposed
sors with high level of time synchronization. Multi channel On-chip sigma delta ADC design enable high end signal
inputs where analog to digital conversion is required can processing application realization with less bill of material.
be replaced with proposed architecture (Bindu et al. 2017;
Szczesny et al. 2020).
Secondly, for low cost wireless sensor networks, wire-
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