Course Info

• Lab 5 will be released, get yourself prepared before going to lab

sessions! (FSM preview, FSM background knowledge not a must,
just use sum of minterm/Karnaugh map)
• Project 1.1! Start early! Do not waste your slip days (CS110P)!
DDL March 13th.
• Project 1.2 will be available this week, and will be marked in lab
sessions. Deadline March 31th.
• HW3 ddl March 18th.
• Next week discussion on synchronized digital system (SDS)

1
 CS 110
Computer Architecture
Combinational & Sequential Circuits
Instructors:
Siting Liu & Chundong W ng
Course website: https://to st-l b.sist.sh ngh itech.edu.cn/courses/CS110@Sh ngh iTech/
Spring-2023/index.html
School of Inform tion Science nd Technology (SIST)
Sh ngh iTech University

2023/3/5
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 Where are we?
temp = v[k];
High Level Language v[k] = v[k+1];
Program (e.g., C) v[k+1] = temp;
Compiler
lw xs0, 0(x2) Anything can be represented
Assembly Language Program
lw xs1, 4(x2) as a number,
(e.g., RISC-V) sw xs1, 0(x2)
sw xs0, 4(x2) i.e., data or instructions
Assembler
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language Program 1010 1111 0101 1000 0000 1001 1100 0110
(RISC-V) 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111
Machine
Interpretation

Hardware Architecture Description

(e.g., block diagrams)

Architecture
Implementation

Logic Circuit Description

(Circuit Schematic Diagrams)

3
 Basic Symbols
• Standard symbols for logic gates

– Buffer, NOT - Universal sets

– NOT, AND, OR
A O Can be combined to implement
any logics
– AND, NAND
– NAND
A
B O

– OR, NOR – NOR

A O
B
Through Boolean algebra! 4
 Build Combinational Circuits with
Basic Logic Gates
• Combinational circuits: the ones that the output of
the digital circuits depends solely on its inputs;
usually built with logic gates without feedback
• Step 1: Write down truth table of the desired logic
For example build an XOR
with AND/OR/NOT
A B O
0 0 0
0 1 1
1 0 1
1 1 0

5
 Build Combinational Circuits with
Basic Logic Gates
• Combinational circuits: the ones that the output of
the digital circuits depends solely on its inputs;
usually built with logic gates without feedback
• Step 2: Pick the lines with 1 as the output; write
them down in Sum of Minterms (Product) form;
For example build an XOR
with AND/OR/NOT Minterms
A B O ĀB̄ m0
0 0 0 ĀB m1
0 1 1
AB̄ m2
1 0 1
AB m3
1 1 0

6
 Build Combinational Circuits with
Basic Logic Gates
• Combinational circuits: the ones that the output of
the digital circuits depends solely on its inputs;
usually built with logic gates without feedback
• Step 3: Simplify using Laws of Boolean algebra;

For example build an XOR

with AND/OR/NOT
A B O
0 0 0
0 1 1
1 0 1
1 1 0

7
 Your turn!
• Build a half adder: • Build a 2-bit adder:
• Sum Carry • Sum Carry • Sum Carry
• 0+0=0 0 • 00 + 00 = 00 0 • 10 + 00 = 10 0
• 0+1=1 0 • 00 + 01 = 01 0 • 10 + 01 = 11 0
• 1+0=1 0 • 00 + 10 = 10 0 • 10 + 10 = 00 1
• 1+1=0 1 • 00 + 11 = 11 0 • 10 + 11 = 01 1
• 01 + 00 = 01 0 • 11 + 00 = 11 0
• 01 + 01 = 10 0 • 11 + 01 = 00 1
• 01 + 10 = 11 0 • 11 + 10 = 01 1
• 01 + 11 = 00 1 • 11 + 11 = 10 1
AB CD

8
 Another Simpli ication Method
—Karnauph Map
AB Gray coded
00 01 11 10

00

01 1
CD
11 1 1 1

Gray
10 1 1
coded

Each cell corresponds to a minterm

Online Karnauph map solver: http://www.32x8.com/index.html 9
f
Representations of Combinational Logic

Truth Table

Enumerate Sum of Products, Enumerate

Inputs Product of Sums Inputs
Methods
or Karnauph map

Use Equivalency
Boolean between boolean Gate Diagram
Expression operators and gates
 Build Larger Blocks—like LEGO®
01010101 • Build a full adder (FA): truth table
+ 01110011
Carry in A B Sum Carry out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
FA FA …… FA FA
Other Useful Combinational Circuits
• Multiplexer (2-to-1) • Multiplexer (2n-to-1)

A 0

0 B 1
A 0
C O
B 1 Sel0 1
C 0
Sel2
Sel D 1

Sel1 Tree structure

Timing Diagram—Signal & Waveform

A Transistors:
O
B non-ideal
switches
Propagation
delay
A L/0 H/1

t
Timing Diagram—Signal Grouping
A
O
B
A
a0
a1
a2
b0
b1
b2
o0
o1
o2
O
t
Build an ALU

15
Instructions are Abstract of Hardware

16
Instructions are Abstract of Hardware

CS110
17
 An Arithmetic & Logic Unit (ALU)
• Arithmetic: Add/Sub/Addi
• Logic: And/Or/Xor(i) (bit-wise)
31st bit of d1 d1[31]
Processor d[31]
31st bit of d2 d2[31]
Control d1[30]
d[30]
d2[30]
Datapath ……
PC d1[0]
d[0]
d2[0]
Registers
Or/Xor similar
Arithmetic & 32
Logic Unit (ALU) d1 32
AND d
d2
32 18
 An Arithmetic & Logic Unit (ALU)
• Arithmetic: Add/Sub/Addi
• Logic: And/Or/Xor(i) (bit-wise)

d1[31] d1[30] d1[1] d1[0]

d2[31] d2[30] d2[1] d2[0] 0

FA FA …… FA FA

c[31] d[31] c[30] d[30] c[1] d[1] c[0] d[0]

32
d1 32
Adder d
d2
32 19
 An Arithmetic & Logic Unit (ALU)
• Arithmetic: Add/Sub/Addi
• Logic: And/Or/Xor(i) (bit-wise)
A - B = A + (-B) = A + B + 1 (mod 2N-1)

d1[31] d1[30] d1[1] d1[0]

d2[31] d2[30] d2[1] d2[0] 0

FA FA …… FA FA

c[31] d[31] c[30] d[30] c[1] d[1] c[0] d[0]

A A
0 1
20
 An Arithmetic & Logic Unit (ALU)
• Arithmetic: Add/Sub/Addi
• Logic: And/Or/Xor(i) (bit-wise)
A - B = A + (-B) = A + B + 1 (mod 2N-1)

d1[31] d1[30] d1[1] d1[0]

d2[31] d2[30] d2[1] d2[0] 0

FA FA …… FA FA

c[31] d[31] c[30] d[30] c[1] d[1] c[0] d[0]

A A
0 1
21
 An Arithmetic & Logic Unit (ALU)
• Arithmetic: Add/Sub/Addi
• Logic: And/Or/Xor(i) (bit-wise)
A - B = A + (-B) = A + B + 1 (mod 2N-1)
d2[31] d2[30] d2[1] d2[0] 0
d1[31] d1[30] d1[1] d1[0]

FA FA …… FA FA

c[31] d[31] c[30] d[30] c[1] d[1] c[0] d[0]

A A
0 1
22
 An Arithmetic & Logic Unit (ALU)
• Arithmetic: Add/Sub/Addi
• Logic: And/Or/Xor(i) (bit-wise)
A - B = A + (-B) = A + B + 1 (mod 2N-1) add/sub
d2[31] d2[30] d2[1] d2[0] 0
d1[31] d1[30] d1[1] d1[0]

FA FA …… FA FA

c[31] d[31] c[30] d[30] c[1] d[1] c[0] d[0]

32
d1 Sub/ 32
d
d2 Adder
32 23
add/sub
 An Arithmetic & Logic Unit (ALU)
• Arithmetic: Add/Sub/Addi
• Logic: And/Or/Xor(i) (bit-wise)
32
From rs1/rs2/imm d1 Sub/ 32
d
d2 Adder
add/sub

d1
AND d
d2
d1
OR d
d2

d1
XOR d
d2
24
 An Arithmetic & Logic Unit (ALU)
• Arithmetic: Add/Sub/Addi
• Logic: And/Or/Xor(i) (bit-wise)
32
From rs1/rs2/imm d1 Sub/ 32
d
d2 Adder 32
add/sub 32
d
AND d

Sel[1:0]
OR d

XOR d
25
Recall: RISC-V Instruction Format
0000000 rs2 rs1 000 rd 0110011 ADD
0100000 rs2 rs1 000 rd 0110011 SUB
0000000 rs2 rs1 100 rd 0110011 XOR
0000000 rs2 rs1 110 rd 0110011 OR
0000000 rs2 rs1 111 rd 0110011 AND

imm rs1 000 rd 0010011 ADDI

imm rs1 100 rd 0010011 XORI
imm rs1 110 rd 0010011 ORI
imm rs1 111 rd 0010011 ANDI

26
Recall: RISC-V Instruction Format
funct3 sel

000 ADD(I) 00
32
d1 Sub/ 32
000 SUB 00 d2 Adder 32
100 XOR(I) 11 00
Instruc[30] add/sub 32
01
110 OR(I) 10 d
10
AND(I) 01
111 AND 11

Sel[1:0]
OR

XOR

27
 Sequential Elements
What about the registers?

28
Combinational Circuits with Feedbacks
• Circuits that can remember or store information
(steady state only)
• Output depends on not only input but also current
state

This structure can

implement SRAM/
latches/FFs.
29
 D Latches & D Flip-Flops
• Latches & Flip-Flops are basic sequential circuits
• D/R-S/J-K/T

C
Q0

Q1
D
One possible implementation of a D latch.

30
 D Latches
C A 0
Q0 Q0

Q1 Q1
D B 1

A B Q0 Q1
1 Q0
0 0
0 1
Q1
1 0 0
1 1
31
 D Latches
A Q0 1 Q0

Q1 Q1
B 1

A B Q0 Q1
0 Q0
0 0
0 1
Q1
1 0 0
1 1
32
 D Latches
A Q0 1 Q0

Q1 Q1
B 1

A B Q0(n+1) Q1(n+1) 0 Q0
0 0
0 1
Q1
1 0 0
1 1
33
 D Latches
C A Q0

Q1
D B

C D A B Q0(n+1) Q1(n+1)
0 0
0 1
1 0
1 1

34
 D Latches—Timing Diagram
C A Q0 (Q) D Q
D latch Q̄
C
Q1 (Q̄) A symbol.
D B

Q
C D A B Q0(n+1) Q1(n+1) C
0 0
0 1 D
1 0 Q
1 1 Q̄
Level-triggered 35
 D Flip-Flops

Q′ Q Q
D D DFF
D latch D latch C
C
A symbol.

Q
C D Q′(n+1) Q (n+1) C
0 0
0 1 D
1 0 Q′
1 1 Q
Edge-triggered 36



 Registers & Synchronized Circuits
D31 Dk D1 D0
Register
x1
DFF …… DFF …… DFF DFF

Q31 Qk Q1 Q0
Clock
D31 Dk D1 D0
Register
x2
DFF …… DFF …… DFF DFF

Q31 Qk Q1 Q0
……

…… 37
 Registers & Synchronized Circuits
D31 Dk D1 D0

DFF …… DFF …… DFF DFF

Q31 Qk Q1 Q0
Clock

Clock: operations coordinated by it;

Help control flow of combinational
blocks; “Heartbeat” of the system

Modern CPUs use fast SRAMs

with multiple (dedicated read
and write) ports as register files.
From Wikipedia. 38
Other Usage of Synchronized Circuits
• PC counter: PC = PC + 4 (w/o considering branch/jump)

temp
32
PC 32
Adder DFF Q=PC
4
clk

clk
PC
Q
temp
39
 Other Components: Shift Register
• Cascaded DFFs Q[3] Q[2] Q[1] Q[0]

D DFF DFF DFF DFF

clk
clk
D
Q[3]
Q[2]
Q[1]
Q[0]
40
 Timing Issues
• Why clk frequency cannot goes to infinity?
D1 Q1 D2
Q2
Combinational Combinational
…… DFF DFF ……
logic logic

clk
Typical digital system: a mix of combinational & sequential circuits
1. Setup/hold time of FF
Setup time Hold time
clk
D2 data1 data2 data3
Q2 data1
Like “undefined 41
behavior” in C
 Timing Issues
• Why clk frequency cannot goes to infinity?
D1 Q1 D2
Q2
Combinational Combinational
…… DFF DFF ……
logic logic

clk
Typical digital system: a mix of combinational & sequential circuits
1. Setup/hold time of FF
Setup time Hold time
clk
D2 data1 data2 data3
tccq
Q2 Contamination delay data1
Clock to Q 42
 Timing Issues
• Why clk frequency cannot goes to infinity?
D1 Q1 D2
Q2
Combinational Combinational
…… DFF DFF ……
logic logic

clk
Typical digital system: a mix of combinational & sequential circuits
1. Setup/hold time of FF
Setup time Hold time
clk
D2 data1 data2 data3
tpcq
Q2 data1
Propagation delay
43
Clock to Q
 Max-Delay Constraints
• Why clk frequency cannot goes to infinity?
D1 tpcq Q1 tpd D2
Q2
Combinational Combinational
…… DFF DFF ……
logic logic

clk Tclk
clk
Q1 tpcq d1
D2 tpd d2
Q2 d2
Tclk ≥ tpcq + tpd + setup me 44
ti
 Max-Delay Constraints
• Why clk frequency cannot goes to infinity?
D1 tpcq Q1 tpd D2
Q2
Combinational Combinational
…… DFF DFF ……
logic logic

clk Tclk
clk
Q1 tpcq d1
D2 tpd d2
Q2 d2
Tclk ≥ tpcq + tpd + setup me Critical path 45
ti
 Min-Delay Constraints
• Avoid hold time violation
D1 tccq Q1 tcd D2
Q2
Combinational Combinational
…… DFF DFF ……
logic logic

clk Tclk
clk
Q1 d1 tccq
D2 d2 tcd
Q2 d2
tcd ≥ hold me − tccq 46
ti
 Question
Clock->Q (P) 1ns
Setup 1ns
Hold 1ns
AND delay 1ns

What is maximum clock frequency?

• A: 5 GHz
• B: 500 MHz
• C: 200 MHz
• D: 250 MHz
• E: 1/6 GHz 47
 Finite-State Machine (FSM)
“Give me the place to stand, and I shall move the earth.”—Archimedes

48
 FSM
• FSMs consists of states, transitions, an entrance (initial
state) and input/output (optional)

Transistion condition
a
S0 S1
b
d c
e

S2 S3
f

49
 C Program as an FSM
• FSMs consists of states, transitions, an entrance (initial
state) and input/output (optional)

#include <stdio.h> main() {?,?,?}

int main() {//compute 1234 + 4321
int x = 1234, y = 4321;
{?,?,?} (start)
int z = x+y;
printf("z=%d/n",z);
return 0; {x,y,z} {x,y,?}
}
{1234,4321,5555} {1234,4321,?}

Print (output)
Exit
z
50
 ISA as an FSM
• FSMs consists of states, transitions, an entrance (initial
state) and input/output (optional)
Processor Memory
• States: all registers & memory
Control • Transition: register/memory value
change
Datapath
• Entrance: power on
Bytes
• Input: instructions, can change
PC
registers/memory value
Registers • Output: states of each registers/
memory
Arithmetic & Logic
Unit (ALU)

51
 Digital Systems as FSMs
• FSMs consists of states, transitions, an entrance (initial
state) and input/output (optional)

D
clk DFF Q

D=1
& clk posedge

S0/0 S1/1

D=0 State transition diagram

& clk posedge

52
 A Classic Problem: Build Digital Circuit for
Sequence Detection
• Build a digital circuit, detecting the occurrence of {101} in
the input 0/1 sequence (non-overlapping)

clk
input 0 1 0 0 1 1 0 1 0 1
output
input: 0 or 1 in a sequence, one bit at a clock cycle
Output: 1 after {101} detected, otherwise 0;
States: ?
Transition: ?

53
 A Classic Problem: Build Digital Circuit for
Sequence Detection
• Build a digital circuit, detecting the occurrence of {101} in
the input 0/1 sequence (non-overlapping)

clk
input 0 1 0 0 1 1 0 1 0 1
output
input: 0 or 1 in a sequence, one bit at a clock cycle
Output: 1 after {101} detected, otherwise 0;
States:
Transition: Nothing /0 {101} /1
detected detected
54
 A Classic Problem: Build Digital Circuit for
Sequence Detection
• Build a digital circuit, detecting the occurrence of {101} in
the input 0/1 sequence (non-overlapping)

clk
input 0 1 0 0 1 1 0 1 0 1
output
0
0 Nothing /0 1 {101} /1
detected detected
1 0 1
1 {1} /0 {10} /0
detected detected
0 55
 A Classic Problem: Build Digital Circuit for
Sequence Detection
• Everything is a number. Use binary numbers to encode
states: {00, 01, 10, 11}

00/0 0 11/1
0 Nothing /0 1 {101} /1
detected detected
1 0 1
01/0 10/0
1 {1} /0 {10} /0
detected detected
0

56
 A Classic Problem: Build Digital Circuit for
Sequence Detection
• A digital circuit model (TaoLu) for FSM (Moore machine)
Cur. State

Next-State State Output

Logic register Logic

• Timing diagram

57
 A Classic Problem: Build Digital Circuit for
Sequence Detection
• A digital circuit model for FSM (Moore machine)
Cur. State
Input
Next-State State Output
Output
Logic register Logic

• Truth table Cur.State Input Next State Output

00 0 00 0
00 1 01 0
01 0 10 0
01 1 01 0
10 0 00 0
10 1 11 0
11 0 00 1
11 1 01 1 58
 A Classic Problem: Build Digital Circuit for
Sequence Detection
• A digital circuit model for FSM (Moore machine)
Cur. State
Input
Next-State State Output
Output
Logic register Logic

• Truth table Cur.State Input Next State Output

00 0 00 0
00 1 01 0
01 0 10 0
01 1 01 0
10 0 00 0
10 1 11 0
11 0 00 1
11 1 01 1 59