EES 20.06.

2023
20/02/2023/V4

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SE
MESTER-I
ASICDESIGN
CourseCode 22LVS12 CIEMarks 50
TeachingHours/Week(L:P:SDA) 3:2:0 SEEMarks 50
TotalHoursofPedagogy 40hoursTheory+10-12Labslots TotalMarks 100
Credits 04 ExamHours 3

Courseobjectives:
 TolearnASICmethodologiesandprogrammablelogiccellstoimplementafunctiononIC.
 ToAnalyseback-endphysicaldesignflow,includingpartitioning,floor-planning,placement,androuting.
 ToGainsufficienttheoreticalknowledgeforcarryingoutFPGAandASICdesigns.

MODULE-1
IntroductiontoASICs:Fullcustom,Semi-customandProgrammableASICs,ASICDesignflow,ASICcelllibraries.
CMOSLogic: DatapathLogicCells:DataPathElements,Adders:Carryskip,Carrybypass,Carrysave,Carryselect,
Conditionalsum,Multiplier(Boothencoding),DatapathOperators,I/Ocells,CellCompilers.

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
MODULE-2
ASICLibraryDesign:Logicaleffort:PredictingDelay,Logicalareaandlogicalefficiency,Logicalpaths,Multistage
cells,Optimumdelayandnumberofstages,librarycelldesign.
ProgrammableASICLogicCells:
MUXasBooleanfunctiongenerators,ActedACT:ACT1,ACT2andACT3LogicModules,XilinxLCA:XC3000CLB,AlteraFLEX
andMAX,ProgrammableASICI/OCells:XilinxandAlteraI/OBlock.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProces
s
MODULE-3
Low-leveldesignentry:Schematicentry:Hierarchicaldesign,Thecelllibrary,Names,SchematicIcons&Symbols,
Nets, Schematic Entry for ASICs, Connections, vectored instances & buses, Edit in place, attributes, Netlistscreener.
ASICConstruction:PhysicalDesign,CADToolsSystempartitioning,EstimatingASICsize.
Partitioning:Goalsandobjectives,ConstructivePartitioning,IterativePartitioningImprovement,KL,FMand
LookAheadalgorithms.

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
MODULE-4
Floorplanningandplacement:Goalsandobjectives,MeasurementofdelayinFloorplanning,Floorplanningtools,Chan
neldefinition, I/OandPowerplanningandClockplanning.
Placement:GoalsandObjectives,Min-
cutPlacementalgorithm,IterativePlacementImprovement,Timedrivenplacementmethods, PhysicalDesignFlow.

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
MODULE5
Routing: Global Routing: Goals and objectives, Global Routing Methods, Global routing between blocks, Back-
annotation. Detailed Routing: Goals and objectives, Measurement of Channel Density, Left-Edge
Algorithm,Area-RoutingAlgorithms,Multilevelrouting,Timing–Drivendetailedrouting,Finalroutingsteps,Special
Routing,CircuitextractionandDRC.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
EES 20.06.2023
20/02/2023/V4

PRACTICALCOMPONENTOFIPCC.
Sl.NO Experiments

Developandverifyaverilogcode,exerciseatestbench,synthesize,anddotheinitialtimingverific
ationwithgatelevelsimulation.ExperimentstobedoneusingsuitableCADtools.
Forthesetofexperimentslistedbelow,studentscanmakethefollowingflowasastudy:

- CoreConstrainedflow
- CreationofI/Opadframe
- UsethecreatedI/OpadframeforPadconstraineddesign.
- CTSflowOnlyfordesignswhichhaveclock
1 Inverter

2
4-bitbinarycomparatorcomposedof2-bitcomparators

3
3:8decoder

4 Flipflop-RS,D,JK,MS,T

5 4-bitcounter[Synchronous&Asynchronouscounter]

6
4·bituniversalshiftregister

7
4-bitadder/subtractor

8
12-bitregisterthatstoresanunsignedintegervalue

 Tolearnthebasicscienceunderlyingindividualprocesssteps.
AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE. A student shall be deemed to have satisfied the academic requirements and earned
thecreditsallottedtoeachsubject/courseifthestudentsecuresnotlessthan50%(50marksoutof100)inthesumtotalof
theCIE(ContinuousInternalEvaluation)andSEE(SemesterEnd Examination)takentogether

CIEforthetheorycomponentofIPCC
1. TwoTestseachof20Marks
2. Twoassignmentseachof10Marks/OneSkillDevelopmentActivityof20marks
3. TotalMarksoftwotestsandtwoassignments/oneSkillDevelopmentActivityaddedwillbeCIEfor60marks,markss
coredwill beproportionallyscaleddownto30marks.
CIEforthepracticalcomponentofIPCC

 On completion of every experiment/program in the laboratory, the students shall be evaluated and
marksshallbeawardedonthesameday.The15marksareforconductingtheexperimentandpreparationofthela
boratory record,theother 05marksshallbefor thetestconductedattheendofthesemester.
 TheCIEmarks awardedinthecaseofthePracticalcomponentshallbebasedonthecontinuousevaluationof the
laboratory report. Each experiment report can be evaluated for 10 marks. Marks of all experiments’write-
upsareaddedandscaleddownto15marks.

 Thelaboratorytestattheend/aftercompletionofalltheexperimentsshallbeconductedfor50marksandscaledd
ownto05 marks.

Scaled-downmarksofwrite-upevaluationsandtestsaddedwillbeCIEmarksforthelaboratorycomponentof
EES 20.06.2023
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IPCCfor20marks.S
EEfor IPCC
TheorySEEwillbeconductedbyUniversityasperthescheduledtimetable,withcommonquestionpapersforthecourse
(duration03 hours)
1. Thequestionpaperwillbesetfor100marksandmarksscoredwillbescaleddownproportionatelyto50marks.
2. Thequestionpaperwillhavetenquestions.Eachquestionissetfor20marks.
3. Therewillbe2questionsfromeachmodule.Eachof thetwoquestionsunder a module(with a maximumof 3sub-
questions),shouldhave amixoftopicsunder that module.
4. Thestudentshavetoanswer5fullquestions,selectingonefullquestionfromeachmodule.

ThetheoryportionoftheIPCCshallbeforbothCIEandSEE,whereasthepracticalportionwillhaveaCIEcomponent
only. Questions mentioned in the SEE paper shall include questions from the practicalcomponent).
 TheminimummarkstobesecuredinCIEtoappearforSEEshallbethe15(50%ofmaximummarks-30)inthe
theory component and 10 (50% of maximum marks -20) in the practical component. The
laboratorycomponentoftheIPCCshallbeforCIEonly.However,inSEE,thequestionsfromthelaboratorycompon
entshallbeincluded.Themaximumof04/05questionstobesetfromthepracticalcomponentofIPCC,thetotalmar
ks ofallquestionsshouldnotbemorethanthe20marks.
 SEEwillbeconductedfor100marksandstudentsshallsecure40%ofthemaximummarkstoqualifyintheSEE.Mar
kssecuredwillbescaleddownto50.(Studenthastosecureanaggregateof50%ofmaximum
marksofthecourse(CIE+SEE)

SuggestedLearningResources:
Books
1. MichaelJohnSebastianSmith,“Application-SpecificIntegratedCircuits”,Addison-WesleyProfessional,2005
2. NeilH.E.Weste,DavidHarris,andAyanBanerjee,“CMOSVLSIDesign:ACircuitsandSystemsPerspective”,Addiso
nWesley/Pearsoneducation3rdedition,2011
3. VikramArkalgudChandrasetty,“VLSIDesign:APracticalGuideforFPGAandASICImplementations”Springer,IS
BN:978-1-4614-1119-2.2011
4. RakeshChadha,BhaskerJ,“AnASICLowPowerPrimer”,Springer,ISBN:978-14614-4270-7.

5. PeterJ.AshendenDigitalDesign(Verilog):AnEmbeddedSystemsApproachUsingVerilog,1stEdition,KindleEditio
n

WeblinksandVideoLectures(e-Resources):
 https://www.youtube.com/watch?v=oZSv68esbgI
 https://www.youtube.com/watch?v=4cPkr1VHu7Q
 https://nptel.ac.in/courses/106105161
ActivityBasedLearning(SuggestedActivitiesinClass)/PracticalBasedlearning
RealworldProblemSolving: ApplyingtheASICfrontendandbackendconcepts.
EES 20.06.2023
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Courseoutcome(CourseSkillSet)

Attheendofthecoursethe studentwillbeableto:
Sl.No. Description BloomsLevel
CO1 DescribetheconceptsofASICdesignmethodology,datapathelements,logicaleffort. L 1,L2

CO2 AnalyzethedesignofASICssuitableforspecifictasks,performdesignentryandexplainthep L2,L3

hysicaldesignflow.
CO3 DesigndatapathelementsforASICcelllibrariesandcomputeoptimumpathdelay. L3

CO4 CreatefloorplanincludingpartitionandroutingwiththeuseofCADalgorithms L3,L4

CO5 DesignCADalgorithmsandexplainhowtheseconceptsinteractinASICdesign. L2,L3

EES 20.06.2023
20/02/2023/V4

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation (OBE)SEMESTER-I
ADVANCEDEMBEDDEDSYSTEMS1
CourseCode 22LVS13 CIEMarks 50
TeachingHours/Week(L:P:SDA) 3:0:2 SEEMarks 50
TotalHoursofPedagogy 40HoursTheory+10-
TotalMarks 100
12slotsforSkillDevelopmentActivi
ties
Credits 04 ExamHours 03

CourseLearningobjectives:
 TounderstandbasicconceptsofEmbeddedSystems.
 ToknowdevelopmentofHardwareSoftwareco-designinEmbeddedSystem.
 TounderstandArchitectureofARM-32bitMicrocontroller.
 ToanalyseInstructionsetsbyAssemblybasics,Instructionlistanddescription.
 TolearnCortex-
M3programmingusingClanguageconceptsandMicrocontrollerSoftwareInterfaceStandardconcepts.
Module-1
Embedded System: Embedded vs General computing system, classification, application and purpose of ES.
Coreof an Embedded System, Memory, Sensors, Actuators, LED, Opto coupler, Communication Interface, Reset
circuits,RTC,WDT,CharacteristicsandQualityAttributesofEmbeddedSystems
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-2
EmbeddedSystem(Continued):HardwareSoftwareCo-
Design,embeddedfirmwaredesignapproaches,computationalmodels,embeddedfirmwaredevelopmentlanguages,
IntegrationandtestingofEmbeddedHardware and firmware, Components in
embeddedsystemdevelopmentenvironment(IDE),Filesgeneratedduringcompilation,simulators,emulators
anddebugging
Teaching- Chalkandtalk/Powerpointpresentation
LearningProces
s
Module-3
ARM-32 bit Microcontroller: Thumb-2 technology and applications of ARM, Architecture of ARM Cortex
M3,VariousUnitsinthearchitecture,GeneralPurposeRegisters,SpecialRegisters,exceptions,interrupts,stackoperation,
resetsequence.

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-4
InstructionSets:Assembly basics, Instruction list and description, useful instructions,
MemorySystems:Memorymaps,Memoryaccessattributes,DefaultMemoryAccessPermissions,Bitbandoperations,E
ndianMode.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-5
Exceptions,NestedVectorinterruptcontrollerdesign,SystickTimer,Cortex-
M3ProgrammingusingassemblyandClanguage,CMSIS.
Teaching- Chalkandtalk/Powerpointpresentation
LearningPr
ocess
EES 20.06.2023
20/02/2023/V4

AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(ContinuousInternalEvaluation)andSEE (SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1. ThreeUnitTestseachof20Marks
2. Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattaintheCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
theoutcomedefinedforthecourse.

SemesterEndExamination:
1. TheSEEquestionpaperwillbesetfor100marksandthemarksscoredwillbeproportionatelyreducedto50.
2. Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3. Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-questions)fromeachmodule.
4. Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5. Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
.

SuggestedLearningResources:
Books
1. K.V.Shibu,“Introductiontoembeddedsystems”,TMHeducationPvt.Ltd.2009
2. JosephYiu,“TheDefinitiveGuidetotheARMCortex-M3”,Newnes,(Elsevier)2ndedn,2010.
3. JamesK.Peckol,“Embeddedsystems-Acontemporarydesigntool”,JohnWiley,2008

WeblinksandVideoLectures(e-Resources):
 https://youtu.be/GaZBpY9Ys1Y
 https://youtu.be/SUusup7FfJo
 https://youtu.be/dHsHP9RrXBw?list=PLJ5C_6qdAvBH-JNRIlupFb44miyx9M8JD
 https://youtu.be/vn7aT9-cYzQ
 https://youtu.be/-rWGzFDLnAY

SkillDevelopmentActivitiesSuggested

1. Interactwithindustry(small,medium,andlarge).
2. Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemetho
dstosolvetheproblem.
3. Involveincasestudiesandfieldvisits/fieldwork.
4. Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5. Handleadvancedinstrumentstoenhancetechnicaltalent.
6. Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermal
study,etc.
7. Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclu
de.
All activities should enhance student’s abilities to employment and/or self-employment
opportunities,management skills, Statistical analysis, fiscal expertise, etc. Students and the course
instructor/s to involveeither individually or in groups to interact together to enhance the learning and
application skills of
thestudytheyhaveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprelevanttechnical
–activitieswhichwillenhancetheirskill.Theprepared reportshallbeevaluatedforCIEmarks.
EES 20.06.2023
20/02/2023/V4

Courseoutcome(CourseSkillSet)

Attheendofthecoursethe studentwillbeableto:
Sl.No. Description BloomsLevel
CO1 Understandthebasichardwarecomponentsandtheirselectionmethodbasedonthechara L2
cteristics andattributesofanembeddedsystem.

CO2 Explainthehardwaresoftwareco-designandfirmwaredesignapproaches. L5

CO3 UnderstandthesuitabilityoftheinstructionsetsofARMprocessorstodesignof L2
embeddedsystems.
CO4 AcquiretheknowledgeofthearchitecturalfeaturesofARMCORTEXM3,a32- L5
bitmicrocontrollerincludingmemorymap,interrupts andexceptions.
CO5 ApplytheknowledgegainedforProgrammingARMCORTEXM3fordifferentapplications L3
EES 20.06.2023

20/02/2023/V4

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEMES
TER-I
DIGITALVLSIDESIGN
CourseCode 22LVS14 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2 SEEMarks 50
TotalHoursofPedagogy 25HoursTheory+10-
TotalMarks 100
12slotsforSkillDevelopmentActivi
ties
Credits 3 ExamHours 3

CourseLearningobjectives:
 TounderstandtheoperationofMOStransistor,ScalingandSmallGeometryEffects.
 TostudyStaticCharacteristics,SwitchingCharacteristicsandInterconnectEffectofMOSInverter.
 ToprovidetheinsightofSemiconductorMemories,DynamicLogicCircuitsandBiCMOSLogicCircuits.

Module-1
MOSTransistor:TheMetalOxideSemiconductor(MOS)Structure,TheMOSSystemunderExternalBias,Structureand
OperationofMOSTransistor,MOSFETCurrent-VoltageCharacteristics,MOSFETScalingandSmall-GeometryEffects.
MOSInverters-StaticCharacteristics:Introduction,Resistive-LoadInverter,Inverterswithn_TypeMOSFET
Load.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-2
MOSInverters-StaticCharacteristics:CMOSInverter.
MOSInverters:SwitchingCharacteristicsandInterconnectEffects:Introduction,Delay-
TimeDefinition,CalculationofDelayTimes,InverterDesignwithDelayConstraints,EstimationofInterconnectParasit
ics,CalculationofInterconnectDelay,SwitchingPowerDissipationofCMOSInverters.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-3
SemiconductorMemories:Introduction,DynamicRandomAccessMemory(DRAM),StaticRandomAccessMemory(
SRAM)

Teaching-Learning Chalkandtalk/Powerpointpresentation
Process
Module-4
DynamicLogicCircuits:Introduction,BasicPrinciplesof
PassTransistorCircuits,VoltageBootstrapping,SynchronousDynamicCircuitTechniques,DynamicCMOSCircuitTechni
ques,HighPerformanceDynamicCMOScircuits

Teaching-Learning Chalkandtalk/Powerpointpresentation
Process
Module-5
BiCMOSLogicCircuits: Introduction,BipolarJunctionTransistor
(BJT):StructureandOperation,DynamicBehaviorofBJTs,BasicBiCMOSCircuits:StaticBehavior,SwitchingDelayinBiC
MOSLogicCircuits,BiCMOS
Applications.
Teaching-Learning Chalkandtalk/Powerpointpresentation
Process

21
EES 20.06.2023

20/02/2023/V4

AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(ContinuousInternalEvaluation)andSEE (SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1. ThreeUnitTestseachof20Marks
2. Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattaintheCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
theoutcomedefinedforthecourse.

SemesterEndExamination:
1. TheSEEquestionpaper willbesetfor100marksandthemarksscoredwillbeproportionatelyreducedto50.
2. Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3. Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-questions)from
eachmodule.
4. Eachfullquestion willhaveasub-questioncoveringallthetopicsunderamodule.
5. Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
.

SuggestedLearningResources:
Books

1. “SungMoKang&YusufLeblebici”,CMOSDigitalIntegratedCircuits:AnalysisandDesign,TataMcGraw-Hill,Third
Edition.
2. “NeilWesteandK.Eshraghian”,PrinciplesofCMOSVLSIDesign:ASystemPerspectivePearsonEducation(Asia)Pvt.Ltd.Se
condEdition,2000.
3. “Wayne,Wolf”,Modern VLSI Design: SystemonSilicon,
PrenticeHallPTR/PearsonEducationSecondEdition,1998.
4. “DouglasAPucknell&KamranEshraghian”,BasicVLSIDesignPHI3rdEdition
WeblinksandVideoLectures(e-Resources):
 https://www.youtube.com/watch?v=57uTCtSQV50&list=PLHO2NKv71TvsSqYwVvUCZwNkY-jUyUHdS
 https://www.youtube.com/watch?v=oL8SKNxEaHs&list=PLLy_2iUCG87Bdulp9brz9AcvW_TnFCUmM

SkillDevelopmentActivitiesSuggested:
1. Interactwithindustry(small,medium,andlarge).
2. Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemetho
dstosolvetheproblem.
3. Involveincasestudiesandfieldvisits/fieldwork.
4. Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5. Handleadvancedinstrumentstoenhancetechnicaltalent.
6. Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermal
study,etc.
7. Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclu
de.

All activities should enhance student’s abilities to employment and/or self-employment

opportunities,management skills, Statistical analysis, fiscal expertise, etc. Students and the course
instructor/s to involveeither individually or in groups to interact together to enhance the learning and
application skills of
thestudytheyhaveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprelevanttechnical
–activitieswhichwillenhancetheirskill.Theprepared reportshallbeevaluatedforCIEmarks.

22
EES 20.06.2023

20/02/2023/V4

Courseoutcome(CourseSkillSet)
Attheendofthecoursethe studentwillbeableto:
Sl.No. Description BloomsLevel
CO1 AnalyseissuesofOn-chipinterconnectModellingandInterconnectdelaycalculation. L4
CO2 AnalysetheSwitchingCharacteristicsinDigitalIntegratedCircuits. L4
CO3 UsetheDynamicLogiccircuitsinstate-of-the-artVLSIchips. L3
CO4 StudycriticalissuessuchasESDprotection,Clockdistribution,Clockbuffering,and L2
Latchphenomenon
CO5 UseBipolarandBi-CMOScircuitsinveryhighspeeddesign. L3

23
EES 20.06.2023

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M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SE
MESTER-I
VLSITESTING
CourseCode 22LVS15 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2 SEEMarks 50
TotalHoursofPedagogy 25hoursTheory+10-
TotalMarks 100
12slotsforSkillDevelopmentActiv
ities
Credits 03 ExamHours 03

CourseLearningobjectives:
 ToknowthevarioustypesoffaultsinVLSIbaseddigitalcircuits.
 Toexaminevarioustechniquesavailableforefficientfaultdetectionincombinationalcircuits.
 Tolearnthetechniquestoenhancetestabilityofcombinationalcircuits.
 Tolearnvarioustechniquesthatcanbeusedtomakesequentialcircuitseasilytestable.
TounderstandtestgenerationandresponseevaluationtechniquesusedinBISTschemesforVLSIChips.

Module-1
Faultsindigitalcircuits:FailuresandFaults,Modelingoffaults,TemporaryFaults.
Logic Simulation: Applications, Problems in simulation based design verification, types of simulation,
Theunknown logic values, compiled simulation, event-driven simulation, Delay models, Element evaluation,
HazardDetection,Gate-levelevent-drivenSimulation

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-2
TestgenerationforCombinationalLogiccircuits:FaultDiagnosisofdigitalcircuits,Testgenerationtechniquesforcombina
tionalcircuits,DetectionofmultiplefaultsinCombinationallogiccircuits.

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-3
Testable Combinational logic circuit design: Testable design of multilevel combinational circuits, Synthesis
ofrandom pattern testable combinational circuits, Path delayfault testable combinational logic design, Testable
PLAdesign.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-4
Designoftestablesequentialcircuits:Controllabilityandobservability,Ad-
Hocdesignrulesforimprovingtestability,designofdiagnosablesequentialcircuits,thescan-
pathtechniquefortestablesequentialcircuitdesign,LevelSensitiveScanDesign(LSSD),RandomAccessScanTechnique,Par
tialscan,testablesequentialcircuitdesignusingNonscanTechniques,Crosscheck,BoundaryScan.

.
Teaching- Chalkandtalk/Powerpointpresentation
LearningPro
cess
Module-5
Built-InSelfTest:TestpatterngenerationforBIST,Outputresponseanalysis,CircularBIST,BISTArchitectures.

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process

24
EES 20.06.2023

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AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(ContinuousInternalEvaluation)andSEE (SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1. ThreeUnitTestseachof20Marks
2. Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattaintheCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
theoutcomedefinedforthecourse.

SemesterEndExamination:
1. TheSEEquestionpaperwillbesetfor100marksandthemarksscoredwillbeproportionatelyreducedto50.
2. Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3. Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4. Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5. Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
.

SuggestedLearningResources:

Books
1. LalaParagK,”DigitalCircuitTestingandTestabilityNewYork”,AcademicPress1997.
2. AbramoviciM,BreuerMAandFriedmanA“DigitalSystemsTestingandTestableDesign”DWiley1994.
3. VishwaniDAgarwal”EssentialofElectronicTestingforDigital,MemoryandMixedSignalCircuits”Springer2002.

4. Wang,WuandWenMorgan”VLSITestPrinciplesandArchitectures”Kaufmann,2006.

WeblinksandVideoLectures(e-Resources):
1. https://www.youtube.com/watch?v=O5lyBoWR-PA&list=PLx98Qgh5zPjh6oWI73QfQHZAmAiyt8Wkf
2. https://www.youtube.com/watch?v=Abld-fSxjNM&list=PLbMVogVj5nJTClnafWQ9FK2nt3cGG8kCF
3. https://www.youtube.com/watch?v=MEaMm423t0w&list=PLZjlBaHNchvOFBWBAtAP9exwQgYpKqsO4&index=
1
4. VTUe-learningResources.
SkillDevelopmentActivitiesSuggested
2. Interactwithindustry(small,medium,andlarge).
3. Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemetho
dstosolvetheproblem.
4. Involveincasestudiesandfieldvisits/fieldwork.
5. Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
6. Handleadvancedinstrumentstoenhancetechnicaltalent.
7. Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermal
study,etc.
8. Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclu
de.
All activities should enhance student’s abilities to employment and/or self-employment
opportunities,management skills, Statistical analysis, fiscal expertise, etc. Students and the course
instructor/s to
involveeitherindividuallyoringroupstointeracttogethertoenhancethelearningandapplicationskillsofthe
studytheyhaveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprelevanttechnical

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Courseoutcome(CourseSkillSet)
Sl.No. Description BloomsLevel
CO1 Analyzetheneedforfaultmodellingandtestingofdigitalcircuits L4
CO2 Generatefaultlistsfordigitalcircuitsandcompressthetestsforefficiency L6
CO3 Applythevarioustechniquestoenhancetestabilityofcombinationalcircuits L3
CO4 Applyboundaryscantechniquetovalidatetheperformanceofdigitalcircuits L3

CO5 Designbuilt-inself-testsforcomplexdigitalcircuits L6

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M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
Choice BasedCreditSystem (CBCS)and
OutcomeBasedEducation(OBE)SEMESTER-I
VLSI&ESLab-1
CourseCode 22LVSL17 CIEMarks 50
TeachingHours/Week(L:P:SDA) 1:2:0 SEEMarks 50
TotalHoursofPedagogy - TotalMarks 100
Credits 02 ExamHours 03
Sl. Experiments
No
Part–A:VLSIDigitalDesign
ExperimentstobedoneusingsuitableCADtools&FPGA/CPLDBoards.

FPGADIGITALDESIGN

VLSIFrontEndDesignprograms:

Programmingcanbedoneusinganycompiler.DownloadtheprogramsonFPGA/CPLDboardsandusepatte
rn generator (32 channels and logic analyzer)/Chipscope pro apart from verification bysimulation

1. WriteVerilogcodeforthedesignof8-bit
i. CarryRippleAdder
ii. CarryLookAheadadder
iii. CarrySkipAdder

2. WriteVerilogCodefor8-bit
i. ArrayMultiplication(SignedandUnsigned)
ii. BoothMultiplication(Radix-4)

3. WriteVerilogcodefor4/8-bit
i. MagnitudeComparator
ii. LFSR
iii. ParityGenerator
4. Develop a Verilog model for a thermostat that has two 8-bit unsigned binary inputs representing
thetargettemperatureandtheactualtemperatureindegreesFahrenheit(˚F).Assumethatbothtemperat
uresareabovefreezing(32˚F).Thedetectorhastwooutputs:onetoturnaheateronwhenthe actual
temperature is more than 5˚F below target, and one to turn a cooler on when the
actualtemperature ismorethan5˚Fabovetarget.
5. Develop a Verilog model of the 7-segment decoder, exercise a testbench ,synthesize and do
theinitialtiming verificationwithgatelevelsimulation.
6. Develop a Verilog model of a debouncer for a pushbutton switch that uses a debounce interval
of10ms.Assumethesystemclockfrequencyis50MHz.
7. Design a Mealy and Moore Sequence Detector using Verilog to detect Sequence. Eg 11101
(withandwithoutoverlap)anysequencecanbespecified.

Part–B:ExperimentstobedoneusingARMCortexM3
ARM Cortex M3 Programs- Programming to be done using suitableCADtooland download
theprogramontoaM3evaluationboard.

a)WriteanAssemblylanguage programtocalculate
thesumanddisplaytheresultfortheadditionoffirsttennumbers.SUM=10+9+8+.+1

b) WriteanAssemblylanguageprogramtostoredatainRAM

c) WriteaCprogramtooutputthe“HelloWorld”messageusingUART

d) WriteaCprogramtooperateabuzzerusingCortexM3

e) WriteaCprogramtodisplaythetemperaturesensedusingCortexM3.

f) WriteaCprogramtocontrolsteppermotorusingCortexM3.

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Courseoutcomes:
Attheendofthecoursethestudentwillbeableto:
1. UnderstandthefeaturesofCADtoolinVLSIdesign.
2. Designandverifythebehaviorofdigitalcircuitsusingdigitalflow
3. Verifythedesignusingalogicanalyzer
4. Analysephysicaldesign
5. DevelopAssemblylanguageprogramsandClanguageprogramsfordifferentapplicationsusingARM
-CortexM3Kitand KeiluVision-4tool.
ConductofPracticalExamination:
Alllaboratoryexperimentsaretobeincludedforpracticalexamination.
Forexamination,oneexperimentfromPart-AandOneexperimentfromPart-
Bistobeset.Studentsareallowedtopickone experimentfromthelot.
Strictlyfollowtheinstructionsasprintedonthecoverpageofanswerscriptforbreakupofmarks.Change
ofexperimentisallowedonlyonceandMarksallottedtothe Procedureparttobe made
zero.
Referencebook:PeterJ.AshendenDigitalDesign(Verilog):AnEmbeddedSystemsApproachUsingVerilog1
stEdition,KindleEdition

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M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEME
STER–II
Design of Analog and Mixed Mode VLSI Circuits
CourseCode 22LVS21 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2
SEEMarks 50
TotalHoursofPedagogy 25HoursTheory +10-12sessionsofSkill
TotalMarks 100
DevelopmentActivities.
Credits 03 ExamHours 03
CourseLearningobjectives:
 TounderstandthebasicphysicsandoperationofMOSdevices.
 TostudySingle-StageandDifferentialAmplifiers.
 TolearnDataConverterSpecificationsandArchitectures.
 TounderstandSingleendedDifferentialAmplifierandoperations.
 TolearnarchitectureofDataconverterincludesADC(AnalogtoDigital)andDAC(DigitaltoAnalog)Conve
rters.
Module-1
BasicMOSDevicePhysics:Generalconsiderations,MOSI/VCharacteristics,secondordereffects,MOSdevicemodels.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-2
SinglestageAmplifier:BasicConcepts,CommonSourcestage,Sourcefollower.

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-3
SinglestageAmplifier:common-gatestage,CascodeStage,choiceofdevicemodels.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-4
DifferentialAmplifiers:Singleendedanddifferentialoperation,Basicdifferentialpair,Commonmoderesponse,Differen
tialpairwithMOS loads,Gilbertcell.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-5
DataConverterArchitectures:DAC&ADCSpecifications,CurrentSteeringDAC,ChargeScalingDAC,FlashADC,Successi
veApproximationADC.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(Continuous InternalEvaluation)andSEE(SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1) ThreeUnitTestseachof 20Marks
2) Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattain theCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks

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CIEmethods/questionpaperisdesignedtoattainthedifferentlevelsofBloom’staxonomyaspertheoutcomedefin
edforthecourse.

SemesterEndExamination:
1) TheSEE questionpaperwillbesetfor100marksandthemarksscoredwillbeproportionatelyreducedto50.
2) Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3) Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4) Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5) Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule

SuggestedLearningResources:
Books
1) “BehzadRazavi”,DesignofAnalogCMOSIntegratedCircuits,TMH2007.
2) “R.JacobBaker”,CMOSCircuitDesign,Layout,andSimulation,WileySecondEdition
3) “PhillipE.Allen,DouglasR.Holberg”,CMOSAnalogCircuitDesignOxfordUniversityPressSecondEdition.
WeblinksandVideoLectures(e-Resources):
1. https://www.youtube.com/watch?v=Q3WYZF5wzgU&list=PLbMVogVj5nJQB44z6h0XO2644Vbv7OM8_
2. https://www.youtube.com/watch?v=311XkpNGs8c&list=PL3pGy4HtqwD0rl7gQoESHR-chSq4OPN5p
3. https://www.youtube.com/watch?v=eLTpf_5di2o&list=PLbMVogVj5nJRlMz5diOg9wBizaU6-egJc
4. https://www.youtube.com/watch?v=dcCj_xAXm4k&list=PLLDC70psjvq5vtrb0EdII4xIKA15ec-Ij
5. VTUe-learningResources.
SkillDevelopmentActivitiesSuggested:
1) Interactwithindustry(small,medium,andlarge).
2) Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemethodstosolveth
eproblem.
3) Involveincasestudiesandfieldvisits/fieldwork.
4) Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5) Handleadvancedinstrumentstoenhancetechnicaltalent.
6) Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-
stateoperations,thermalstudy,etc.
7) Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclude.

Allactivitiesshouldenhancestudent’sabilitiestoemploymentand/orself-employmentopportunities,

Courseoutcomes
Attheendofthecoursethestudentwillbeableto:
Sl.No. Description BloomsLevel
CO1 Useefficientanalyticaltoolsforquantifyingthebehaviourofbasiccircuitsbyinspection. L2,L3

CO2 Designhigh-performance,amplifiercircuitswiththetrade- L3,L4

offsbetweenspeed,precisionand powerdissipation.
CO3 Designandstudythebehaviourofphase-locked-loopsfortheapplications. L3,L4
CO4 Identifythecriticalparametersthataffecttheanalogandmixed- L3
signalVLSIcircuits’performance
CO5 Performcalculationsinthedigitalordiscretetimedomain,moresophisticateddataconverte L5
rstotranslatethedigitaldatatoandfrom inherentlyanalogworld.

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M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SE
MESTER-II
AdvancedEmbeddedSystems2
CourseCode 22LVS22 CIEMarks 50
TeachingHours/Week(L:P:SDA) 3:2:0 SEEMarks 50
TotalHoursofPedagogy 40hoursTheory+10-12Labslots TotalMarks 100
Credits 04 ExamHours 03

CourseLearningobjectives:
 TounderstandtheAdvancedProgrammingfeaturesinARMCortex-M3microcontrollers
 TounderstandbriefHistoryofReal-TimeSystemandResources.
 ToknowSchedulerconceptsandtimingdiagram.
 ToexaminevarioustypesofMemoryofRealTimeandI/O.
MODULE-1
ExceptionProgramming:UsingInterrupts, exception/Interrupt handlers ,softwareInterrupts,
exampleofVectorTablerelocation,UsingSVC,SVCexample:Use forTextMessageOutputFunctions,UsingSVCwithC.

Advanced ProgrammingFeatures andSystemBehavior:Runninga systemwithTwoseparatestacks,Double-

Wordstackalignment,NonbaseThreadenable,PerformanceConsiderations,Lockupsituations,FAULTMASK.

MemoryProtectionunit:MPUregisters,settingUptheMPU,Typicalsetup.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProc
ess
MODULE-2
OtherCortex-M3Features:PowerManagement,MultiprocessorCommunication,self-resetControl.
Debug Architecture: Debugging Features Overview ,Coresight Overview ,Debug Modes ,Debugging events
,BreakpointintheCortex-M3,accessingregisterContentinDebug.
DebuggingComponents:TraceComponents:DWT,TraceComponents:ITMTraceComponents:eTM,TraceComponent
s: TpIU ,The Flash patch and Breakpoint Unit The advanced high-performance Bus access port , ROMTable
Porting Applicationsfrom the ARM7 to theCortex-M3:System Characteristics, Assembly Language
Files,CprogramFiles.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProces
s
MODULE-3
Real-Time Systems and Resources: Brief history of Real Time Systems, A brief history of Embedded
Systems.System Resources, Resource Analysis, Real-Time Service Utility, Scheduler concepts, Real-Time OS, State
transitiondiagramandtables,Thread SafeReentrantFunctions.
ProcessingwithRealTimeScheduling:SchedulerConcepts,PreemptiveFixedPrioritySchedulingPolicieswith
timingdiagramsandproblemsandissues,Feasibility
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
MODULE-4
ProcessingwithRealTimeScheduling(Continued):RateMonotonicleastupperbound,NecessaryandSufficientfeasibi
lity,Deadline–Monotonic Policy,Dynamic prioritypolicies,Alternativeto RM policy.
MemoryandI/O:Worstcaseexecutiontime,IntermediateI/O,ECCmemory,Multi-resourceServices,Blocking,
Deadlockandlivelock,Criticalsectionstoprotectsharedresources,Misseddeadline,QoS,ReliabilityandAvailability,Similarities
anddifferences,Reliablesoftware,Availablesoftware.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProc
ess
MODULE5
Firmware Components: The 3 firmware components, RTOS system software mechanisms,
DebuggingComponents,Exceptions,assert,Checkingreturncodes,Single-stepdebugging,Testaccessports,TracePorts.

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ProcessandThreads:Processandthreadcreations,Programsrelatedtosemaphores,messagequeue,sharedbufferappli
cationsinvolving intertask/threadcommunication.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProc
ess

PRACTICALCOMPONENTOFIPCC
Sl.NO Experiments
WriteaCProgramforthefollowing

1 ToTest4X4keypadusingCortexM3microcontrollers.

2
ToDisplaymessageonGraphicLCDdisplayusingCortexM3microcontrollers.

3 ToTestworkingonInternal ADCusingCortexM3microcontrollers.

4 ToTestworkingofInternalDACusingCortexM3microcontrollers.
5 TotestworkingofInterruptusingCortexM3microcontrollers.

6 TotestonPWMtechniqueusingCortexM3/M4microcontrollers.

WriteaAssemblylanguageprogramusingsuitableCADsoftware/Tools

7 Tolinkmultipleobjectfilesandlinkthemtogether

8 TolockingaMutex

9 WriteaSVChandlerinC.Usethewrappercodetoextractthecorrectstackframestartinglocation.TheChandlercant
henusethistoextractthestackedPClocationandthestackedregistervalues.

10 WriteaC-
programforFCFSFirstcomefirstserveusingsuitableCADsoftwaretoPresenttheOutputofCPUSchedulingalgori
thm.
11 WriteaC-
programforSJFShortestjobfirstusingsuitableCADsoftwaretoPresenttheOutputofCPUSchedulingalgorithm
12 WriteaC-programforPriorityusingsuitableCADsoftwaretoPresenttheOutputofCPUSchedulingalgorithm

AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE. A student shall be deemed to have satisfied the academic requirements and earned
thecreditsallottedtoeachsubject/courseifthestudentsecuresnotlessthan50%(50marksoutof100)inthesumtotalof
theCIE(ContinuousInternalEvaluation)andSEE (SemesterEndExamination)takentogether
CIEforthetheorycomponentofIPCC
1.TwoTestseachof20Marks

1. Twoassignmentseachof10Marks/OneSkillDevelopmentActivityof20marks
2. TotalMarksoftwotestsandtwoassignments/oneSkillDevelopmentActivityaddedwillbeCIEfor60marks,markss
coredwill beproportionallyscaleddownto30marks.

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CIEforthepracticalcomponentofIPCC

 On completion of every experiment/program in the laboratory, the students shall be evaluated and
marksshallbeawardedonthesameday.The15marksareforconductingtheexperimentandpreparationofthela
boratory record,theother 05marksshallbefor thetestconductedattheendofthesemester.
 TheCIEmarks awardedinthecaseofthePracticalcomponentshallbebasedonthecontinuousevaluationof the
laboratory report. Each experiment report can be evaluated for 10 marks. Marks of all experiments’write-
upsareaddedandscaleddown to15marks.

 Thelaboratorytestattheend/aftercompletionofalltheexperimentsshallbeconductedfor50marksandscaledd
ownto05 marks.

Scaled-downmarksofwrite-
upevaluationsandtestsaddedwillbeCIEmarksforthelaboratorycomponentofIPCCfor20 marks.
.
SEEforIPCC
TheorySEEwillbeconductedbyUniversityasperthescheduledtimetable,withcommonquestionpapersforthecourse
(duration03 hours)
1. The question paper will be set for 100 marks and marks scored will be scaled down proportionately to
50marks.

2. Thequestionpaperwillhavetenquestions.Eachquestionissetfor20marks.
3. Therewillbe2questions fromeachmodule.Eachofthetwoquestionsundera module(withamaximumof3sub-
questions), shouldhaveamixoftopics underthat module.
4. Thestudentshavetoanswer5fullquestions,selectingonefullquestionfromeachmodule.

ThetheoryportionoftheIPCCshallbeforbothCIEandSEE,whereasthepracticalportionwillhaveaCIEcomponent
only. Questions mentioned in the SEE paper shall include questions from the practicalcomponent).
 TheminimummarkstobesecuredinCIEtoappearforSEEshallbethe15(50%ofmaximummarks-30)inthe
theory component and 10 (50% of maximum marks -20) in the practical component. The
laboratorycomponentoftheIPCCshallbeforCIEonly.However,inSEE,thequestionsfromthelaboratorycompon
entshallbeincluded.Themaximumof04/05questionstobesetfromthepracticalcomponentofIPCC,thetotalmar
ks ofallquestionsshouldnotbemorethanthe20marks.
 SEEwillbeconductedfor100marksandstudentsshallsecure40%ofthemaximummarkstoqualifyintheSEE.Mar
kssecuredwillbescaleddownto50.(Studenthastosecureanaggregateof50%ofmaximum
marksofthecourse(CIE+SEE)

SuggestedLearningResources:
Books.
1. K.V.Shibu,“Introductiontoembeddedsystems”,TMHeducationPvt.Ltd.2009
2. JosephYiu,“TheDefinitiveGuidetotheARMCortex-M3”,Newnes,(Elsevier)2ndedn,2010.
3. JamesK.Peckol,“Embeddedsystems-Acontemporarydesigntool”,JohnWiley,2008
4. SamSiewert,Real-TimeEmbeddedSystemsandComponents,CengageLearningIndiaEdition2007.
5. Dr.K.V.K.KPrasad,Embedded/RealTimeSystems,Concepts,DesignandProgramming,BlackBook,,DreamTech
Press,Newedition,2010
6. JamesW SLiu,RealTimeSystem,PearsonEducation,2008
7. DreamTechSoftwareTeam,ProgrammingforEmbeddedSystems,JohnWiley,IndiaPvt.Ltd.,2008
WeblinksandVideoLectures(e-Resources):

 ARMArchitectureFundamentals–https://youtu.be/7LqPJGnBPMM
 https://www.youtube.com/watch?v=cP6NxivTY94&list=PLbMVogVj5nJRDS4w20GO7l4SepLhuAj9X&index=17
 https://www.youtube.com/watch?v=Kju5UMLC7hg

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ActivityBasedLearning(SuggestedActivitiesinClass)/PracticalBasedlearning
RealworldProblemSolving:ApplyingtheCortexM3Microcontrollerconcepts

Courseoutcome(CourseSkillSet):
Attheendofthecoursethe studentwillbeableto:
Sl.No. Description BloomsLevel
CO1 Developprogramsforrealtimeservices,firmwareandRTOS,usingthefundamentalsof L6
Real Time Embedded System, real time service utilities, debugging
methodologiesandoptimizationtechniques.
CO2 Selecttheappropriatesystemresources(CPU,I/O,Memory,Cache,ECCMemory,Microcon L4
troller/FPGA/ASICtoimprove thesystem performance.

CO3 Applyprioritybasedstaticanddynamicrealtimeschedulingtechniquesforthegivenspecifi L3
cations.

CO4 Analyzedeadlockconditions,sharedmemoryproblem,criticalsectionproblem,missedde L4
adlines,availability,reliability and QoS.

CO5 Develop L6
programsformultithreadedapplicationsusingsuitabletechniquesanddatastructure

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M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEMESTER-II
Advances in VLSI Design
CourseCode 22LVS231 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2 SEEMarks 50
TotalHoursofPedagogy 25HoursTheory+10-
TotalMarks 100
12slotsforSkillDevelopmentActivi
ties
Credits 03 ExamHours 03

CourseLearningobjectives:
 TounderstandImplementationstrategiesfordigitalICSfromcustomtosemicustomArrayDesign.
 ToknowperformanceparametersofCMOScircuits,
 TolearnTimingissuesofdigitalsystem,MemorydesignandProgrammablelogicdevice(PLD).

Module-1
Implementation Strategies For Digital ICS: Introduction, From Custom to Semicustom and Structured
ArrayDesignApproaches,CustomCircuitDesign,Cell-
BasedDesignMethodology,StandardCell,CompiledCells,Macrocells,MegacellsandIntellectualProperty,Semi-
CustomDesignFlow,Array-BasedImplementationApproaches, Pre-diffused (or Mask-Programmable) Arrays, Pre-
wired Arrays, Perspective-The ImplementationPlatformoftheFuture.
Teaching- Chalkandtalk/Powerpointpresentation
LearningPro
cess
Module-2
CopingWithInterconnect:Introduction,CapacitiveParasitics,CapacitanceandReliability-CrossTalk,Capacitance
and Performance in CMOS, Resistive Parasitics, Resistance and Reliability-Ohmic Voltage
Drop,Electromigration,ResistanceandPerformance-RCDelay,InductiveParasitics,InductanceandReliability-
VoltageDrop, Inductance andPerformance-TransmissionLine Effects, Advanced Interconnect
Techniques,Reduced-SwingCircuits,Current-ModeTransmissionTechniques,Perspective:Networks-on-a-Chip.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProces
s
Module-3
TimingIssuesInDigitalCircuits:Introduction,TimingClassificationofDigitalSystems,SynchronousInterconnect,M
esochronousinterconnect,PlesiochronousInterconnect,AsynchronousInterconnect,Synchronous Design — An
In-depth Perspective, Synchronous Timing Basics, Sources of Skew and Jitter, Clock-Distribution Techniques,
Latch-Base Clocking, Self-Timed Circuit Design, Self-Timed Logic - An AsynchronousTechnique,Completion-
SignalGeneration,Self-TimedSignaling,PracticalExamplesofSelf-
TimedLogic,SynchronizersandArbiters,Synchronizers-ConceptandImplementation,Arbiters,ClockSynthesisand
SynchronizationUsingaPhase-LockedLoop,BasicConcept,BuildingBlocksofaPLL.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-4
Designing Memory and Array Structures: Introduction, Memory Classification, Memory Architectures
andBuildingBlocks,TheMemoryCore,Read-OnlyMemories,NonvolatileRead-WriteMemories,Read-
WriteMemories(RAM),Contents-AddressableorAssociativeMemory(CAM),MemoryPeripheralCircuitry,The
AddressDecoders,SenseAmplifiers,VoltageReferences,Drivers/Buffers,TimingandControl.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProc
ess
Module-5
Designing Memory and Array Structures: Memory Reliability and Yield, Signal-to-NoiseRatio, Memory
yield,PowerDissipationinMemories,SourcesofPowerDissipationinMemories,Partitioningofthememory,Addressin
gtheActivePowerDissipation,Dataretentiondissipation,CaseStudiesinMemoryDesign:TheProgrammableLogicArr
ay(PLA),A4MbitSRAM,A1GbitNANDFlashMemory,Perspective:Semiconductor
MemoryTrendsandEvolutions.

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Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(ContinuousInternalEvaluation)andSEE (SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1. ThreeUnitTestseachof20Marks
2. Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattaintheCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
theoutcomedefinedforthecourse.

SemesterEndExamination:
1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced
to50.
2. Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3. Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4. Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5. Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
.
SuggestedLearningResources:
Books
1. JanMRabey,AnanthaChandrakasan,BorivojeNikolic,“DigitalIntegratedCircuits-
ADesignPerspective”,PHI,2ndEdition
2. M.Smith,“ApplicationSpecificIntegratedcircuits”,AddisonWesley,1997
3. Wang,WuandWen,“VLSITestPrinciplesandArchitectures”,MorganKaufmann,2006
4. H.Veendrick,“MOSICs:FromBasicstoASICs”,Wiley-VCH,1992

WeblinksandVideoLectures(e-Resources):
 https://www.youtube.com/watch?v=kcJi8gJ1kBo&list=PLbMVogVj5nJTDr6KqQXNcxCvooSMnBuXj
 https://www.youtube.com/watch?v=ZxhaktnuBk8&list=PLbMVogVj5nJTDr6KqQXNcxCvooSMnBuXj
&index=2

SkillDevelopmentActivitiesSuggested
1. Interactwithindustry(small,medium,andlarge).
2. Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemetho
dstosolvetheproblem.
3. Involveincasestudiesandfieldvisits/fieldwork.
4. Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5. Handleadvancedinstrumentstoenhancetechnicaltalent.
6. Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermal
study,etc.
7. Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclu
de.

Allactivitiesshouldenhancestudent’sabilitiestoemploymentand/orself-
employmentopportunities,managementskills,Statisticalanalysis,fiscalexpertise,etc.Studentsandthecoursein
structor/stoinvolve
eitherindividuallyoringroupstointeracttogethertoenhancethelearningandapplicationskillsofthestudytheyh
aveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprelevanttechnical

38
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Courseoutcome(CourseSkillSet)
Attheendofthecoursethe studentwillbeableto:
Sl.No. Description BloomsLevel
CO1 Applydesignautomationforcomplexcircuitsusingthedifferentimplementation L3
methodologylikecustomversussemi-
custom,hardwiredversusfixed,regulararrayversusad-hoc.
CO2 Usetheapproachestominimizetheimpactofinterconnectparasiticsonperformance,powerdi L5
ssipationandcircuit reliability

CO3 Imposetheorderingoftheswitchingeventstomeetthedesiredtimingconstraintsusingsy L3
nchronous,clockedapproach.

CO4 Inferthereliabilityofthememory L6

CO5 Understandtheroleofperipheralcircuitrysuchasthedecoders,senseamplifiers,driversan L2
dcontrolcircuitry in thedesign ofreliableandfastmemories

39
EES 20.06.2023
01.02.2023
05/12/2022

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEMESTER-II
Nano electronics
CourseCode 22LVS232 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2 SEEMarks 50
TotalHoursofPedagogy 25HoursTheory+10-
TotalMarks 100
12slotsforSkillDevelopmentActivi
ties
Credits 03 ExamHours 03

CourseLearningobjectives:
 TounderstandOverviewofNanoscienceandengineering.
 TolearnQuantumconfinementinsemiconductornanostructures.
 Toanalyzedifferentfabricationprocessandphysicalprocess.
 TounderstandvarioustypesofmethodsofmeasuringpropertiesandapplicationsofNanoelectronics.
Module-1
Introduction:Overviewofnanoscienceandengineering.Developmentmilestonesinmicrofabricationandelectronici
ndustry.Moores’lawandcontinuedminiaturization,ClassificationofNanostructures,
Electronic properties of atoms and solids: Isolated atom, Bonding between atoms, Giant molecular solids,
Freeelectron models and energy bands, crystalline solids, Periodicity of crystal lattices,Electronic conduction,
effectsofnanometerlengthscale,Fabricationmethods:Topdownprocesses,Bottomupprocessesmethodsfor
templatingthegrowthofnanomaterials,orderingofnanosystems.
Teaching- Chalkandtalk/Powerpointpresentation
LearningPro
cess
Module-2
Characterization:Classification,Microscopictechniques,Fieldionmicroscopy,scanningprobetechniques,diffraction
techniques: bulk and surface diffraction techniques, spectroscopy techniques: photon,
radiofrequency,electron,surfaceanalysisanddeptprofiling:electron,mass,Ionbeam,Reflectrometry,Techniquesforpro
perty
measurement:mechanical,electron,magnetic,thermalproperties
Teaching- Chalkandtalk/Powerpointpresentation
LearningProces
s
Module-3
Inorganicsemiconductornanostructures:overviewofsemiconductorphysics.Quantumconfinementinsemicond
uctor nanostructures: quantum wells, quantum wires, quantum dots, super-lattices, band offsets, andelectronic
densityof states.
CarbonNanostructures: Carbon molecules, Carbon Clusters, Carbon Nanotubes, application of Carbon
Nanotubes.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProc
ess
Module-4
Fabrication techniques: requirements of ideal semiconductor, epitaxial growth of quantum wells,
lithographyandetching,cleaved-
edgeovergrowth,growthofvicinalsubstrates,straininduceddotsandwires,electrostatically induced dots and wires,
Quantum well width fluctuations, thermally annealed quantum wells,semiconductor nanocrystals,
colloidalquantumdots,self-assemblytechniques.
.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProc
ess
Module-5
Physical processes: modulation doping, quantum hall effect, resonant tunneling, charging effects, ballistic
carriertransport, Inter band absorption, intra band absorption, Light emission processes, phonon bottleneck,
quantumConfinedstarkeffect,nonlineareffects,coherenceanddephasing,characterizationofsemiconductor
nanostructures:opticalelectricalandstructural

40
EES 20.06.2023
01.02.2023
05/12/2022
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process

40
EES 20.06.2023

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AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(ContinuousInternalEvaluation)andSEE (SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1. ThreeUnitTestseachof20Marks
2. Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattaintheCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
theoutcomedefinedforthecourse.

SemesterEndExamination:
1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced
to50.
2. Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3. Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4. Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5. Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
.
SuggestedLearningResources:
Books
1. EdRobertKelsall,IanHamley,MarkGeoghegan,“NanoscaleScienceandTechnology”,JohnWiley,2007
2. CharlesPPoole,Jr,FrankJOwens,“IntroductiontoNanotechnology”,JohnWileyCopyright2006,Reprint2011.
3. EdWilliamAGoddardIII,DonaldWBrenner,SergeyE.Lyshevski,GeraldJIafrate,“HandBookofNanoscienceEngineerin
gandTechnology”,CRCpress,2003.

WeblinksandVideoLectures(e-Resources):
 https://www.youtube.com/watch?v=wdNFCWLuC10&list=PLbMVogVj5nJT8RG5Q4CpsJXiGqXE6t8N1
 https://www.youtube.com/watch?v=Oq5TweDVyKQ

SkillDevelopmentActivitiesSuggested
1. Interactwithindustry(small,medium,andlarge).
2. Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemetho
dstosolvetheproblem.
3. Involveincasestudiesandfieldvisits/fieldwork.
4. Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5. Handleadvancedinstrumentstoenhancetechnicaltalent.
6. Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermal
study,etc.
7. Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclu
de.

All activities should enhance student’s abilities to employment and/or self-employment

opportunities,management skills, Statistical analysis, fiscal expertise, etc. Students and the course
instructor/s to involveeither individually or in groups to interact together to enhance the learning and
application skills of
thestudytheyhaveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprelevanttechnical
–activitieswhichwillenhancetheirskill.Theprepared reportshallbeevaluatedforCIEmarks.

41
EES 20.06.2023

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Courseoutcome(CourseSkillSet)

Attheendofthecoursethe studentwillbeableto:
Sl.No. Description BloomsLevel
CO1 KnowtheprinciplesbehindNanoscienceengineeringandNanoelectronics. L2
CO2 Applytheknowledgetoprepareandcharacterizenanomaterials. L3
CO3 Knowthe effect of particles size on mechanical, thermal, optical and electrical L2
propertiesofnanomaterials.
CO4 Designtheprocessflowrequiredtofabricatestateofthearttransistortechnology. L6

CO5 Analyzethe requirements for new materials and device structure in the future L4

42
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M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEMESTER-II
Static Timing Analysis
CourseCode 22LVS233 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2 SEEMarks 50
TotalHoursofPedagogy 25HoursTheory+10-
TotalMarks 100
12slotsforSkillDevelopmentActivi
ties
Credits 03 ExamHours 03

CourseLearningobjectives:
 TounderstandtheSTAEnvironmentandconcepts.
 Toknowstandardcelllibrarywithtimingmodelanddelaymodel.
 Tostudydelaycalculationsandtimingverificationconceptsofflip-flops.
Module-1
Introduction: Nanometer Designs, What is Static Timing Analysis?Why Static Timing Analysis?, Crosstalk
andNoise, Design Flow, CMOS Digital Designs, FPGA Designs, Asynchronous Designs, STA at Different
DesignPhases,LimitationsofStaticTimingAnalysis,PowerConsiderations,ReliabilityConsiderations
STA Concepts:CMOSLogicDesign,Basic MOS Structure, CMOS Logic Gate, Standard Cells, Modeling
ofCMOSCells,SwitchingWaveform,PropagationDelay,SlewofaWaveform,SkewbetweenSignals,TimingArcsandUnatene
ss,MinandMaxTimingPaths,ClockDomains,Operating Conditions
Teaching- Chalkandtalk/Powerpointpresentation
LearningProc
ess
Module-2
StandardCellLibrary:Pin Capacitance,TimingModeling,LinearTimingModel,Non-LinearDelayModel,Example of
Non-Linear, Delay Model Lookup,Threshold Specifications andSlew DeratingTiming Models -Combinational
Cells, Delay and Slew Models, Positive or Negative Unate, General Combinational Block, TimingModels -
Sequential Cells, Synchronous Checks: Setup and Hold, Example of Setupand Hold Checks, NegativeValues in
Setup and Hold Checks, Asynchronous Checks, Recovery and Removal Checks Pulse Width Checks,Example of
Recovery, Removal and Pulse Width Checks, Propagation Delay, State- Dependent Models
XOR,XNORandSequentialCells,InterfaceTimingModelforaBlackBox,Advanced
TimingModeling,ReceiverPinCapacitance, Specifying Capacitance at the Pin Level, Specifying Capacitance at the
Timing Arc Level, OutputCurrent, Models for Crosstalk Noise Analysis, DC Current, Output Voltage, Propagated
Noise, Noise Models forTwo-Stage Cells, Noise Models for Multi-stage and sequential Cells, Other Noise Models,
Power DissipationModeling,ActivePower,

Teaching- Chalkandtalk/Powerpointpresentation
LearningProces
s
Module-3
Interconnect Parasitics:RLCfor Interconnect,Wireload Models,Interconnect Trees, SpecifyingWireloadModels,
Representation of Extracted Parasitic, Detailed Standard Parasitic Format ,Reduced Standard ParasiticFormat,
Standard Parasitic Exchange Format, Representing Coupling Capacitances, Hierarchical Methodology,Block
Replicated in Layout, Reducing Parasitic for Critical Nets, Reducing Interconnect Resistance, Increasing
WireSpacing,Parasiticsfor CorrelatedNets.
DelayCalculation:Overview,DelayCalculationBasics,DelayCalculationwithInterconnect,Pre-layoutTiming,Post-
layoutTiming,CellDelayusingEffectiveCapacitance,InterconnectDelay,ElmoreDelay,HigherOrderInterconnect
Delay Estimation, Full Chip Delay Calculation, Slew Merging, Different Slew Thresholds,
DifferentVoltageDomains,PathDelayCalculation,CombinationalPathDelay,PathtoaFlip-flop,InputtoFlip-flopPath,
Flip-floptoFlip-flopPath,MultiplePaths,SlackCalculation.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProc
ess
Module-4
ConfiguringtheSTAEnvironment:WhatistheSTAEnvironment?
Specifying Clocks, Clock Uncertainty, Clock Latency, Generated Clocks, Example of Master Clock at Clock
GatingCell Output, Generated Clock using Edge and Edge shift Options, Generated Clock using Invert Option,
ClockLatencyforGenerated Clocks, Typical Clock GenerationScenario,Constraining
43
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InputPaths,ConstrainingOutput

44
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20/02/2023/V4

Paths,ExampleA,ExampleB,ExampleTimingPathGroups,ModelingofExternalAttributes,ModelingDriveStrengths,Mo
delingCapacitiveLoad,DesignRuleChecks,VirtualClocks,

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-5
Timing Verification: Setup Timing Check, Flip-flop to Flip-flop Path, Input to Flip-flop Path, Input Path with
ActualClock, Flip flop to Output Path, Input to Output Path, Frequency Histogram, Hold Timing Check, Flip-flop
to Flip-flop Path, Hold Slack Calculation, Input to Flip-flop Path, Flip-flop to Output Path, Flip-flop to OutputPath
withActual Clock, Input to Output Path, Multicycle Paths, Crossing Clock Domains, FalsePaths, Half- Cycle
Paths,Removal Timing Check, Recovery Timing Check, Timing across Clock Domains, Slow toFastClock Domains,
FasttoSlowClockDomains,Half-cyclePath-Case1,Half-cyclePath-Case2,FasttoSlowClockDomain,Slowto
FastClockDomain,
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(ContinuousInternalEvaluation)andSEE(SemesterEnd Examination)takentogether.
ContinuousInternalEvaluation:
1. ThreeUnitTestseachof20Marks
2. Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattaintheCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
theoutcomedefinedforthecourse.

SemesterEndExamination:
1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced
to50.
2. Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3. Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4. Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5. Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
.
SuggestedLearningResources:
Books
1. J.Bhasker,RChadha,“StaticTimingAnalysisforNanometerDesigns:APracticalApproach”,Springer2009Refere
nceBooks
2. SridharGangadharan,SanjayChuriwala,“ConstrainingDesignsforSynthesisandTimingAnalysis–APracticalGuide
toSynopsisDesignConstraints(SDC)”,Springer,2013
3. NareshMaheshwariandSachinSapatnekar,“TimingAnalysisandOptimizationofSequentialCircuits”,SpringerScienc
eandBusinessMedia,1999

WeblinksandVideoLectures(e-Resources):
 https://www.youtube.com/watch?v=KlUn2GjNOfY&list=PLYdInKVfi0Ka5c6kraib5qiCFhPWE9G6e
 https://www.youtube.com/watch?v=yYR8BzysTmM&list=PLYdInKVfi0Ka5c6kraib5qiCFhPWE9G6e&index=
2

45
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SkillDevelopmentActivitiesSuggested
1. Interactwithindustry(small,medium,andlarge).
2. Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemetho
dstosolvetheproblem.
3. Involveincasestudiesandfieldvisits/fieldwork.
4. Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5. Handleadvancedinstrumentstoenhancetechnicaltalent.
6. Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermal
study,etc.
7. Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclu
de.

All activities should enhance student’s abilities to employment and/or self-employment

opportunities,management skills, Statistical analysis, fiscal expertise, etc. Students and the course
instructor/s to involveeither individually or in groups to interact together to enhance the learning and
application skills of
thestudytheyhaveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprelevanttechnical
–activitieswhichwillenhancetheirskill.ThepreparedreportshallbeevaluatedforCIEmarks.
Courseoutcome(CourseSkillSet)

Attheendofthecoursethe studentwillbeableto:
Sl.No. Description BloomsLevel
CO1 Evaluatethedelayofanygivendigitalcircuits. L5
CO2 PreparetheresourcestoperformthestatictiminganalysisusingEDAtool. L6

CO3 Preparetimingconstraintsforthedesignbasedonthespecification. L6

CO4 GeneratethetiminganalysisreportusingEDAtoolfordifferentchecks. L5,L6

CO5 Perform verification and analyse the generated report to identify critical issues L3
andbottleneck for the violation and suggest the techniques to make the design to
meettiming

46
EES 20.06.2023

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M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SE
MESTER -III
Embedded Linux System Design and Development
CourseCode 22LVS234 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2 SEEMarks 50
TotalHoursofPedagogy 25HoursTheory+10-
TotalMarks 100
12slotsforSkillDevelopmentActivi
ties
Credits 03 ExamHours 03

CourseLearningobjectives:

 TounderstandtheimportanceofEmbeddedLinuxinembeddedsystemdesign.
 ToGaintheknowledgeofBoardSupportPackage.
 ToAnalysethememoryrequirementsfordesign.
 Tolearntheembeddeddriversandkernelmodules.
 TolearntheportingapplicationsfromtraditionalRTOS
Module-1
Introduction:HistoryofEmbeddedLinux,WhyEmbeddedLinux,EmbeddedLinuxVersusDesktopLinux,FrequentlyAs
kedQuestions,EmbeddedLinux Distributions,PortingRoadmap.
GettingStarted: Architecture of Embedded Linux, Linux Kernel Architecture, User Space, Linux Start-Up
Sequence,GNUCrossPlatformToolchain.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-2
BoardSupportPackage:InsertingBSPinKernelBuildProcedure,MemoryMap,InterruptManagement,ThePCISubs
ystem,Timers,UART,PowerManagement.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-3
EmbeddedStorage:FlashMap,MTD—Memory TechnologyDevice,MTDArchitecture,SampleMTDDriver
forNORFlash,TheFlash-
MappingDrivers,MTDBlockandCharacterDevices,MtdutilsPackage,EmbeddedFileSystems,OptimizingStorage
Space,TuningKernelMemory.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-4
EmbeddedDrivers:LinuxSerialDriver,EthernetDriver,I2CSubsystemonLinux,USBGadgets,WatchdogTimer,Kernel
Modules
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-5
PortingApplications:ArchitecturalComparison,ApplicationPortingRoadmap,ProgrammingwithPthreads,Operatin
gSystemPortingLayer(OSPL),KernelAPI Driver.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process

47
EES 20.06.2023

20/02/2023/V4

AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(ContinuousInternalEvaluation)andSEE (SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1. ThreeUnitTestseachof20Marks
2. Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattaintheCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
theoutcomedefinedforthecourse.

SemesterEndExamination:
1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced
to50.
2. Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3. Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4. Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5. Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
.
SuggestedLearningResources:
Books
1. P.Raghavan,AmolLad,SriramNeelakandan”EmbeddedLinuxSystemDesignAndDevelopment”,AuerbachPublicati
ons,Taylor&FrancisGroup,2006
2. KarimYaghmour,JonMasters,GiladBenYossef,andPhilippeGerum“BuildingEmbeddedLinuxSystems”O’Reillypub
lications,2ndedition

WeblinksandVideoLectures(e-Resources):
 https://www.youtube.com/watch?v=9vsu67uMcko

SkillDevelopmentActivitiesSuggested
1. Interactwithindustry(small,medium,andlarge).
2. Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemethodstosolvet
heproblem.
3. Involveincasestudiesandfieldvisits/fieldwork.
4. Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5. Handleadvancedinstrumentstoenhancetechnicaltalent.
6. Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermalstudy,etc.
7. Workondifferentsoftware/s(tools)tosimulate,analyseandauthenticatetheoutputtointerpretandconclude.

Allactivitiesshouldenhancestudent’sabilitiestoemploymentand/orself-
employmentopportunities,managementskills,Statisticalanalysis,fiscalexpertise,etc.
Studentsandthecourseinstructor/stoinvolveeitherindividuallyoringroupstointeracttogethertoenhancethelearnin
gandapplicationskillsofthestudytheyhaveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprele
vanttechnical–activitieswhichwillenhancetheirskill.ThepreparedreportshallbeevaluatedforCIEmarks.

48
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Courseoutcome(CourseSkillSet)

Attheendofthecoursethe studentwillbeableto:
Sl.No. Description BloomsLevel
CO1 UnderstandtheembeddedLinuxdevelopmentenvironment. L1,L2
CO2 UnderstandandcreateLinuxBSPforahardwareplatform L1,L2
CO3 UnderstandtheLinuxmodelforembeddedstorageandwritedriversandapplications L1,L2
forthesame.
CO4 UnderstandvariousembeddedLinuxdriverssuchasserial,I2C,andsoon. L1,L2
CO5 PortapplicationstoembeddedLinuxfromatraditionalRTOS L3

49
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M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)

IISemester VLSI Process Technology

CourseCode 22LVS235 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2 SEEMarks 50
TotalHoursofPedagogy 25HoursTheory+10-
TotalMarks 100
12slotsforSkillDevelopmentActivities
Credits 03 ExamHours 03
CourseLearningobjectives:
 Tounderstandthetheoreticalandpracticalaspectofverylargescaleintegration
 ToanalysedopingprofilesandmaterialpropertieswithSOItechnology.
 Tolearntheartoflithographywithdifferenttechniques.
 Toanalyseplasmadischargepropertiesandthediagnostictechniques.
 Tounderstandimplantationprocessandapplicabilityofmetallizationscheme.

Module-1

CrystalGrowth and Wafer Preparation:Introduction, Electronic-

GradeSilicon,CzochralskiCrystalGrowing.
Epitaxy:Introduction,Vapour-PhaseEpitaxy.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-2
Lithography:Introduction,Optical Lithography, ElectronLithography, X-ray
Lithography,IonLithography.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-3

ReactivePlasmaEtching:Introduction,PlasmaProperties,Feature-
SizeControlandAnisotropicEtchMechanisms,OtherPropertiesofEtchProcesses,ReactivePlasma-
EtchingTechniquesandEquipment,SpecificEtchProcesses.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-4

IonImplantation:Introduction,RangeTheory,ImplantationEquipment,Annealing,ShallowJunctions,
High-EnergyImplantation.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-5
Metallization:Introduction,MetallizationApplications,MetallizationChoices,PhysicalVaporDeposit
ion,Patterning,Metallizationproblems.
Teaching-Learning Chalkandtalk/Powerpointpresentation
Process
AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(Continuous InternalEvaluation)andSEE(SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1) ThreeUnitTestseachof20Marks
2) Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
41
0
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20/02/2023
/V4

toattain theCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIEmethods/questionpaperisdesignedtoattainthedifferentlevelsofBloom’staxonomyaspertheoutcomedefin
edforthecourse.
SemesterEndExamination:
1) TheSEEquestionpaperwillbesetfor100marksandthemarksscoredwillbeproportionatelyreducedto50.
2) Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3) Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4) Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5) Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
SuggestedLearningResources:
Books

1. S.M.Sze,“VLSITechnology”,McGraw-Hill,SecondEdition.
2. S.K.Ghandhi,"VLSIFabricationPrinciples",JohnWileyInc.,NewYork,1994,SecondEdition.

WeblinksandVideoLectures(e-Resources):
https://www.youtube.com/watch?v=EbWmRJeNM9w&list=PLbMVogVj5nJSkDoV3lpZpZUEnzNIRsDpl

SkillDevelopmentActivitiesSuggested:
1) Interactwithindustry(small,medium,andlarge).
2) Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemethodstosolvet
heproblem.
3) Involveincasestudiesandfieldvisits/fieldwork.
4) Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5) Handleadvancedinstrumentstoenhancetechnicaltalent.
6) Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermalstudy,etc.
7) Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclude.

Allactivitiesshouldenhancestudent’sabilitiestoemploymentand/orself-
employmentopportunities,managementskills,Statisticalanalysis,fiscal expertise,etc.
Studentsandthecourseinstructor/stoinvolveeitherindividuallyoringroupstointeracttogethertoenhancethelearnin
gandapplicationskillsofthestudytheyhaveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprelev
anttechnical–activitieswhichwillenhancetheirskill.Thepreparedreportshallbeevaluatedfor
CIEmarks.

Courseoutcomes(CourseSkillSet)
Attheendofthecoursethestudentwillbeableto:
Sl.No. Description BloomsLevel
CO1 UnderstandthemajorstepsinthefabricationprocessofVLSIcircuits. L1,L2

CO2 Illustrateparticularprocessingstepsinachievingrequiredparameters. L1

CO3 Applystandardengineeringfordifferentlithographicmethods. L3

CO4 Analysethespecificplasmaprocessusedinsemiconductorindustry L4,L5

CO5 ApplyimplantationprocessforVLSIdevicesanddiscussthelimitationsofvariousmetalliza L3,L4

tionschemes.

50
EES 20.06.2023

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEMESTER-II
IISemester Low Power VLSI Design
CourseCode 22LVS241 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2
SEEMarks 50
TotalHoursofPedagogy 25HoursHoursTheory+10-
TotalMarks 100
12sessionsforSkillDevelopmentActivities
Credits 3 ExamHours 03
CourseLearningobjectives:
 TostudyState-of-theartapproachesofpowerestimationandreduction.
 Tounderstandpowerdissipationatvariouslevelsofdesign 

Module-1
Introduction:Needforlow powerVLSIchips,charginganddischargingcapacitance,shortcircuit current
inCMOSleakagecurrent,staticcurrent,basicprinciplesoflowpowerdesign,lowpowerfigureof merits.
Simulationpoweranalysis: SPICEcircuitsimulation, MonteCarlosimulation.
Teaching- Chalkandtalkmethod/PowerPointPresentation
LearningProcess
Module-2
Circuit:Transistorandgatesizing,equivalentpinordering,networkrestructuringandreorganization,speciallatchesandfl
ipflops,lowpower digitalcell library,adjustabledevicethresholdvoltage.
Teaching- Chalkandtalkmethod/PowerPointPresentation
LearningProcess
Module-3
Logic:Gatereorganization,signalgating,logicencoding,statemachineencoding,pre-
computationlogic.LowpowerClockDistribution:Powerdissipationinclockdistribution,singledriverVsdistributedbuf
fers.
Teaching- Chalkandtalkmethod/PowerPointPresentation
LearningProcess
Module-4
LowpowerArchitecture&Systems:Power&performancemanagement,switchingactivity
reduction,flowgraphtransformation.
Lowpowermemorydesign:Introduction,sourcesandreductionsofpowerdissipationinmemorysubsystem.
Teaching- Chalkandtalkmethod/PowerPointPresentation
LearningProcess
Module-5
Algorithm&ArchitecturalLevelMethodologies:Introduction,designflow,Algorithmiclevelanalysis&optimization,A
rchitecturallevelestimation&synthesis.
AdvancedTechniques:Adiabaticcomputation,Asynchronouscircuits.
Teaching- Chalkandtalkmethod/PowerPointPresentation
LearningProcess
AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(Continuous InternalEvaluation)andSEE(SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1) ThreeUnitTestseachof 20Marks
2) Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattain theCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIEmethods/questionpaperisdesignedtoattainthedifferentlevelsofBloom’staxonomyaspertheoutcomedefin
edforthecourse.
SemesterEndExamination:

51
EES 20.06.2023

1) TheSEE questionpaperwillbesetfor100marksandthemarksscoredwillbeproportionatelyreducedto50.
2) Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3) Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4) Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5) Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
SuggestedLearningResources:
Books
1) GaryK.Yeap,“PracticalLowPowerDigitalVLSIDesign”,KluwerAcademic,1998.
2) JanM.Rabaey,MassoudPedram,“LowPowerDesignMethodologies”,KluwerAcademic,2010.
3) KaushikRoy,SharatPrasad,“Low-PowerCMOSVLSICircuitDesign”Wiley,2000
4) A.P.ChandrasekaranandR.W.Broadersen,“LowpowerdigitalCMOSdesign”,KluwerAcademic,1995.
5) ABellamourandMIElmasri,“LowpowerVLSICMOScircuitdesign”,KluwerAcademic,1995.
WeblinksandVideoLectures(e-Resources):
1. https://archive.nptel.ac.in/courses/106/105/106105034/
2. https://www.youtube.com/watch?v=TFOO1JAll2Y
3. https://www.youtube.com/watch?v=ORtlxpW_LMU
SkillDevelopmentActivitiesSuggested
1) Interactwithindustry(small,medium,andlarge).
2) Involvein research/testing/projectstounderstandtheirproblemsand helpcreative
andinnovativemethodstosolvetheproblem.
3) Involveincasestudiesandfieldvisits/fieldwork.
4) Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5) Handleadvancedinstrumentstoenhancetechnicaltalent.
6) Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermalstudy,etc.
7) Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclude.

Allactivitiesshouldenhancestudent’sabilitiestoemploymentand/orself-
employmentopportunities,managementskills,Statisticalanalysis,fiscalexpertise,etc.
Studentsandthecourseinstructor/stoinvolveeitherindividuallyoringroupstointeracttogethertoenhancethe
learning and application skills of the study they have undertaken. The students with the help of the
courseteacher can take up relevant technical –activities which will enhance their skill. The prepared report
shall beevaluatedforCIEmarks.

Courseoutcome(CourseSkillSet)
Attheendofthecoursethestudentwillbeableto:
Sl.No. Description BloomsLevel
CO1 IdentifythesourcesofpowerdissipationinCMOScircuits. L1,L2
CO2 Performpoweranalysisusingsimulation-basedapproachesandprobabilisticanalysis.
L2,L3
CO3 Useoptimizationandtrade-
L2,L3
offtechniquesthatinvolvepowerdissipationofdigitalcircuits.
CO4 Makethepowerdesignarealitybymakingpowerdimensionanintegralpartofthedesignpr
L2,L3
ocess.
CO5 Usepracticallowpowerdesigntechniquesandtheiranalysisatvariouslevelsofdesignabstr
actionandanalysehowthesearebeingcapturedinthelatestdesign L3,L4
automationenvironments.

52
EES 20.06.2023

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEMESTER-II
SoC Design
CourseCode 22LVS242 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2 SEEMarks 50
TotalHoursofPedagogy 25HoursTheory + 10-
12sessions for Skill TotalMarks 100
DevelopmentActivities
Credits 03 ExamHours 3

CourseLearningobjectives:
 ToDescribetheorganizationandimplementationofthe3-and5-stagepipelineARMprocessorcores
 ToUnderstandtheneedshigh-levellanguage(inthiscase,C)inapplicationdevelopment
 ToKnowtheissuesinvolvedindebuggingsystemsinembeddedprocessorcoresandintheproductiontesting
ofboard-levelsystems.
 TolearndifferentARMintegercores,conceptofmemoryhierarchyandmanagement.
Module-1
ARMOrganizationandImplementation:3-stagepipelineARMorganization,5-
stagepipelineARMorganization,ARMinstructionexecution, ARMimplementation,TheARMcoprocessorinterface.
TheARMInstructionSet:Introduction,Exceptions, Conditionalexecution,Branchand Branchwith Link(B,BL),
Branch,BranchwithLinkandexchange(BX,BLX),SoftwareInterrupt(SWI).
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-2
The ARM Instruction Set (Continued ) Data processing instructions, Multiply instructions, Count leading
zeros(CLZ - architecture v5T only), Single word and unsigned byte data transfer instruction, Half-word and
signed bytedata transfer instructions, Multiple register transfer instructions, Swap memory and register
instructions (SWP),Status register to general registertransfer instructions, General register to status register
transfer instructions,Coprocessorinstructions, Coprocessordata operations, Coprocessor data transfers, Coprocessor
register transfers,Breakpointinstruction (BRK-architecture
v5Tonly),Unusedinstructionspace,Memoryfaults,ARMarchitecture
Teaching- Chalkandtalk/Powerpointpresentation
LearningProces
s
Module-3
Architectural Support for High-Level Languages: Abstraction in software design, Data types, Floating-
pointdata types, The ARM floating-point architecture, Expressions, Conditional statements ,Loops, Functions
andprocedures,Useof memory, Run-timeenvironment.

Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-4
ArchitecturalSupportforSystemDevelopment:TheARMmemoryinterface,TheAdvancedMicrocontrollerBusArchi
tecture(AMBA),TheARMreferenceperipheralspecification,Hardwaresystemprototypingtools,TheARMulator,TheJT
AGboundaryscantestarchitecture,TheARMdebugarchitecture,EmbeddedTrace,Signal
processingsupport
Teaching- Chalkandtalk/Powerpointpresentation
LearningProces
s
Module-5
ARM Processor Cores: ARM7TDMI, ARM8, ARM9TDMI, ARM10TDMI, Discussion, Example and
exercises.MemoryHierarchy:Memorysizeandspeed,On-chipmemory,Caches,Cachedesign-
anexample,Memorymanagement,Examplesandexercises.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process

53
EES 20.06.2023

AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(ContinuousInternalEvaluation)andSEE(SemesterEnd Examination)takentogether.
ContinuousInternalEvaluation:
1. ThreeUnitTestseachof20Marks
2. Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattaintheCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
theoutcomedefinedforthecourse.

SemesterEndExamination:
1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced
to50.
2. Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3. Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4. Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5. Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
.
SuggestedLearningResources:Books
 SteveFurber“ARMSystem-On-ChipArchitecture”AddisonWesley,2ndedition
 JosephYiu“TheDefinitiveGuidetotheARMCortex-M3”,Newnes,(Elsevier),2ndedition,2010.
 SudeepPasrichaandNikilDutt,”On-ChipCommunicationArchitectures:SystemonChipInterconnect”,Morgan
KaufmannPublishers,2008.
 MichaelKeating,PierreBricaud“ReuseMethodologyManualforSystemonChipdesigns”,KluwerAcademicPublisher
s,2ndedition,2008.

WeblinksandVideoLectures(e-Resources):
 https://www.ele.uva.es/~jesman/BigSeti/ftp/Microcontroladores/ARM/Arm%20System-On-
Chip%20Architecture.pdf.

SkillDevelopmentActivitiesSuggested:

1. Interactwithindustry(small,medium,andlarge).
2. Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemetho
dstosolvetheproblem.
3. Involveincasestudiesandfieldvisits/fieldwork.
4. Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5. Handleadvancedinstrumentstoenhancetechnicaltalent.
6. Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermal
study,etc.
7. Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclu
de.

Allactivitiesshouldenhancestudent’sabilitiestoemploymentand/orself-
employmentopportunities,managementskills,Statisticalanalysis,fiscalexpertise,etc.
Students and the course instructor/s to involve either individually or in groups to interact together
toenhance the learning and application skills of the study they have undertaken. The students with the
helpofthecourseteachercantakeuprelevanttechnical–
activitieswhichwillenhancetheirskill.ThepreparedreportshallbeevaluatedforCIEmarks.

54
EES 20.06.2023

Courseoutcome(CourseSkillSet)

Attheendofthecoursethe studentwillbeableto:
Sl. Description BloomsLe
No. vel
CO1 Applythe3-and5-stagepipelineARMprocessorcoresandanalysetheimplementationiss ueLs3.

CO2 UsetheconceptsandmethodologiesemployedindesigningaSystem-on-chip(SoC)basedaround L3
amicroprocessorcoreandindesigningthemicroprocessorcoreitself.

CO3 UnderstandhowSoCsandmicroprocessorsaredesignedandused,andwhyamodernprocessoris L2
designedthewaythatitis.

CO4 UseintegratedARMCPUcores(includingStrongARM)thatincorporatefullsupportformemory L3
management.

CO5 AnalyzetherequirementsofamodernoperatingsystemandusetheARMarchitectureto L4
addressthesame

55
EES 20.06.2023

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEMESTER-II
SystemVerilog
CourseCode 22LVS243 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2
SEEMarks 50
TotalHoursofPedagogy 25HoursTheory+ 10- TotalMark
100
12sessionsofSkillDevelopmentActivities. s
Credits 03 Exam
03
Hours
CourseLearningobjectives:
 TounderstandtheconceptsofVerificationprocess.
 ToknowtheconceptsofSystemVerilog.
 TogaintheessentialknowledgetowritetheVerificationCode.
 TolearnRandomizationofsystemVerilog.
 Toexaminefunctionalcoveragedependingupondatasample.

Module-1
VerificationGuidelines:Theverificationprocess,basictestbenchfunctionality,directedtesting,methodology
basics,constrainedrandomstimulus,randomization,functionalcoverage,testbenchcomponents,layeredtestbench.

Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-2
DataTypes: BuiltinDatatypes,fixed
anddynamicarrays,Queues,associativearrays,linkedlists,arraymethods,choosing astoragetype, creating new
typeswith typedef, creatinguserdefined structures,
typeconversion,Enumeratedtypes,constantsandstrings,Expressionwidth.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-3
Connectingthetestbenchanddesign:Separatingthetestbenchanddesign,Theinterfaceconstruct,Stimulustiming,
Interfacedrivingandsampling, SystemVerilogassertions.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-4
Randomization:Introduction,RandomizationinSystemVerilog,Constraintdetails,Solutionprobabilities,Validconstrai
nts,Inlineconstraints,Randomnumber functions,Commonrandomizationproblems.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-5
FunctionalCoverage:Coveragetypes,Coveragestrategies,Simplecoverageexample,AnatomyofCovergroupand
TriggeringaCovergroup,Datasampling,Cross coverage,GenericCovergroups,Coverage
options,Analyzingcoveragedata,measuringcoveragestatistics duringsimulation.
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(Continuous InternalEvaluation)andSEE(SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1) ThreeUnitTestseachof 20Marks
2) Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattain theCOsandPOs

56
EES 20.06.2023

Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIEmethods/questionpaperisdesignedtoattainthedifferentlevelsofBloom’staxonomyaspertheoutcomedefin
edforthecourse.

SemesterEndExamination:
1) TheSEE questionpaperwillbesetfor100marksandthemarksscoredwillbeproportionatelyreducedto50.
2) Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3) Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4) Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5) Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
.
SuggestedLearningResources:
Books
1) ChrisSpear,“SystemVerilogforVerification–
AguidetolearningtheTestbenchlanguagefeatures”,SpringerPublicationsSecondEdition,2010.
2) StuartSutherland,SimonDavidmann,PeterFlake,“SystemVerilogforDesign-AguidetousingsystemVerilog
forHardwaredesignandmodelling”,SpringerPublicationsSecondEdition,2006.
WeblinksandVideoLectures(e-Resources):
1. https://www.udemy.com/course/soc-verification-systemverilog/
2. https://www.udemy.com/course/learn-system-verilog-assertions-and-coverage/

SkillDevelopmentActivitiesSuggested:
1) Interactwithindustry(small,medium,andlarge).
2) Involvein research/testing/projectstounderstandtheirproblemsand helpcreative
andinnovativemethodstosolvetheproblem.
3) Involveincasestudiesandfieldvisits/fieldwork.
4) Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5) Handleadvancedinstrumentstoenhancetechnicaltalent.
6) Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermalstudy,etc.
7) Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclude.

Allactivitiesshouldenhancestudent’sabilitiestoemploymentand/orself-employmentopportunities,

CourseOutcomes(CourseSkillSet)
Attheendofthecoursethestudentwillbeableto:
Sl.No. Description BloomsLevel
CO1 ApplytheSystemVerilogconceptstoverifythedesign. L3
CO2 ApplyconstrainedrandomtestsbenchesusingSystemVerilog. L3
CO3 AppreciateFunctionalCoverage. L3,L4

57
EES 20.06.2023

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEMESTER-II
HIGHF REQUENCYGaNELECTRONICDEVICES
CourseCode 22LVS244 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2 SEEMarks 50
TotalHoursofPedagogy 25HoursTheory+10-
TotalMarks 100
12slotsforSkillDevelopmentActivi
ties
Credits 03 ExamHours 03

CourseLearningobjectives:

 Tounderstandanintegratedtreatmentofthestateoftheartinbothconventional(i.e.,HEMT)scalingaswellasu
nconventionaldevicearchitecturessuitableforamplificationandsignalgeneration
 TounderstandthebothconventionalscaledHEMTs(intothedeepmm-
wave)aswellasunconventionalapproachestoaddressthemm-waveandTHzregimes;
 Toknowrelatedphysics,aswellasnumericalsimulationsandexperimentalrealizations..

Module-1
IntroductionandOverview:
HighPowerHighFrequencyTransistors:AMaterial’sPerspective:Introduction,Johnson’sFigureofMerit,
OutputPowerFigureofMerit2,AchievingMobileCarriersforWideBandGapSemiconductors,LowFieldMobilityConsideration
s,ChannelTemperature Considerations,HeterojunctionAdvantages
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-2
Isotope Engineering of GaN for Boosting Transistor Speeds: Introduction, Current Saturation, The Effect
ofNon-equilibriumLOPhononsisTwofold,DerivationoftheElectron-
LOPhononInteractionHamiltonian,EvaluatingtheProbabilityofScatteringintotheLOPhononMode
q,EvaluationofthePhononPopulationinEachMode,CalculatingVelocityvs.FieldDependence,Analysis,“Creative
Disorder”,SummaryoftheTheoreticalAnalysis,ExperimentalFeasibilityofIntroducingIsotopicDisorderinGaN
HEMTs.
Linearity Aspects of High Power Amplification in GaN Transistors: “Creative Disorder”, Summary of
theTheoretical Analysis, Experimental Feasibility of Introducing Isotopic Disorder in GaN HEMTs, Overview of
Non-linearityandItsImpacts,Trade-OffsAgainstOtherMetrics,OriginsofNon-
linearityinGaNHEMTs,Transconductance,Capacitance,Self-heating,Trapping,Large-
SignalModelling,SpecialConcernsforGaN,Available Models, Physically Derived Models, Circuit Models, Device-
Level Design for Linearity, Linearizing theTransconductance Profile,BRIDGEFETTechnology.
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-3
III-NitrideTunnelingHotElectronTransferAmplifier(THETA):
Overview of the Chapter Analysis of Hot Electron Transport and Monte Carlo Simulation, Electron
TransportScattering Mechanisms, Monte Carlo Simulation Small Signal Models for High-Frequency Performance
,EffectofBase Thickness and Doping on β, gm, Delay Component, ft, and fmax, Effect of Emitter-Base Current
Density onDelay Component, ft, and fmax , Unipolar Transport in III-Nitride Alloys, Polarization-Engineered Vertical
Barriers,Leakage in Vertical AlGaN/GaN Heterojunctions, Polarization-Engineered Base-Collector Barriers, Design,
Growth,Fabrication, and Characterization of THETA ,Generation I: Common-Emitter Current Gain , Ga Polar
THETA withCurrentGain>1,NPolarTHETAHotElectronTransportinVerticalAlGaN/GaNHeterostructures,Negative
DifferentialResistanceinIII-NitrideTHETA,GenerationII:CurrentGain>10inIII-NitrideHETs
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-4

58
EES 20.06.2023

Plasma-WavePropagationinGaNandItsApplications:
Electron PlasmaWaves: Physical Origin, Drude Conductivity and Distributed Models for HEMTs,
HydrodynamicTransport Equations and Non-linear Effects, Electron PlasmaWaves in GaN Experimental
Demonstration, DirectElectricalProbing,Quasi-OpticalExcitation,ProspectiveApplications,RTD-GatedHEMT.

59
EES 20.06.2023

NumericalSimulationofDistributedElectromagneticandPlasmaWaveEffectDevices:HydrodynamicModeling
of the 2DEG Channel ,Electrodynamic Equations (or Maxwell’s Equation), Finite Difference TimeDomain(FDTD)
Solution, Time-Space Discretization of HD Equations, Time-Space Discretization of Maxwell’sEquation
4VerificationUsingAnalyticalModelsandExperimentalData,ModelValidationViaAnalytical Method,ModelValidation
ViaPrior Measurements 5 HEMT-Based Terahertz Emitters Using PlasmaWaveInstability , ModelingofHEMT-
BasedTerahertzEmitters,Full-WaveHydrodynamicModelingofTerahertzEmissionsfromanShort
ChannelHEMT[24],Dyakonov-ShurInstability,Instability Mechanism,InstabilityinUngatedInGaAsHEMT,
Teaching- Chalkandtalk/Powerpointpresentation
Learning
Process
Module-5
ResonantTunnelingTransportinPolarIII-Nitride:
Introduction, Background on Resonant Tunneling Devices, III-Nitride-Based Resonant Tunneling Devices,
PolarDouble-Barrier Heterostructures, Molecular Beam Epitaxy of III-Nitride RTDs, GaN/AlN Resonant
TunnelingDiodes, Polar RTD Model,New Tunneling Features in Polar RTDs, Polar RTD at Resonance,
Polarization- InducedThresholdVoltage,

Teaching- Chalkandtalk/Powerpointpresentation
LearningPro
cess
AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(ContinuousInternalEvaluation)andSEE (SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1. ThreeUnitTestseachof20Marks
2. Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks
toattaintheCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
theoutcomedefinedforthecourse.

SemesterEndExamination:
1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced
to50.
2. Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3. Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4. Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5. Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule
SuggestedLearningResources:
Books
1. PatrickFay,DebdeepJena,PaulMaki,“High-
FrequencyGaNElectronicDevice”,SpringerInternationalPublishing,2020
WeblinksandVideoLectures(e-Resources):
1. https://www.youtube.com/watch?v=BboadvgRTYI
2. https://www.youtube.com/watch?v=o3369LXjt3o

51
0
EES 20.06.2023

SkillDevelopmentActivitiesSuggested
1) Interactwithindustry(small,medium,andlarge).
2) Involveinresearch/testing/projectstounderstandtheirproblemsandhelpcreativeandinnovativemethodstosolvet
heproblem.
3) Involveincasestudiesandfieldvisits/fieldwork.
4) Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5) Handleadvancedinstrumentstoenhancetechnicaltalent.
6) Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermalstudy,etc.
7) Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclude.

Allactivitiesshouldenhancestudent’sabilitiestoemploymentand/orself-
employmentopportunities,managementskills,Statisticalanalysis,fiscal expertise,etc.
Studentsandthecourseinstructor/stoinvolveeitherindividuallyoringroupstointeracttogethertoenhancethelearnin
gandapplicationskillsofthestudytheyhaveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprelev
anttechnical–activitieswhichwillenhancetheirskill.Thepreparedreportshallbeevaluatedfor
Courseoutcome(CourseSkillSet)

Attheendofthecoursethe studentwillbeableto:
Sl.No. Description BloomsLevel
CO1 Describetheroleandimpactof nitrogenisotopic L2
selectioninmaterialgrowthanditsimpactoncarriertransportforincreasingdevicespeeda
ndpower.
CO2 Analyse two distinct perspectives on novel approaches for improving the linearity L4
ofGaN-based devices (a key metric for emerging high-speed communications
applications)intermsofunconventionaldeviceconceptsintheIII-Nmaterialsystem.
CO3 Analysehot-carrierinjection-baseddevices,plasma-wave- L4
baseddevices,andresonanttunnelingdiodes.
CO4 Understandtheemergenceofhigh- L2
speeddevicesdemandsnewtechniquesforcharacterization ofdevices and
alsonewapproaches tonumericalsimulationofdevices.
CO5 Describeemergingnoncontactfabricationandcharacterizationtechniquesforultrahigh- L5
speeddevices

60
EES 20.06.2023

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)SEMESTER-II
IISemester MachineLearningandDeepLearning
CourseCode 22LVS245 CIEMarks 50
TeachingHours/Week(L:P:SDA) 2:0:2
SEEMarks 50
TotalHoursofPedagogy 25HoursTheory+10- TotalMark
100
12sessionsofSkillDevelopmentActivities. s
Credits 03 Exam
03
Hours
CourseLearningobjectives:
 Tounderstandvariouskeyparadigmsformachinelearningapproaches
 Tofamiliarizewiththemathematicalandstatisticaltechniquesusedinmachinelearning
 Tounderstandanddifferentiateamongvariousmachinelearningtechniques
 ToknowtechnicaldetailsaboutvariousrecentalgorithmsrelatedtoMachineLearningwithspecificfocusonDee
pLearning
Module-1
SupervisedLearning-
Introduction:Motivation,Differenttypesoflearning,Linearregression,LogisticregressionSupportVectorMachines:Hard
SVM,SoftSVM,Optimalityconditions,Duality,Kerneltrick,ImplementingSoftSVM
withKernels
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-2
DecisionTrees:DecisionTreealgorithms,Randomforests
NeuralNetworks:Feedforwardneuralnetworks,Expressivepowerofneuralnetworks,SGDandBackpropagationModelselecti
onandvalidation:Validationformodelselection,k-foldcross-validation,TrainingValidation-Testing
split,Regularizedlossminimization
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-3
Unsupervised Learning and Generative Models - Nearest Neighbour: k-nearest neighbour, Curse of
dimensionalityClustering:Linkage-basedclusteringalgorithms,k-
meansalgorithm,SpectralclusteringDimensionalityreduction: PrincipalComponent
Analysis,Randomprojections,Compressedsensing
Teaching-Learning Chalkandtalk,Powerpointpresentation,NPTEL,VTUE-learningresources,Experimental
Process learning,Problembasedlearning
Module-4
FoundationsofDeepLearning:DNN,CNN,Autoencoders

Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess
Module-5
IntroductiontoDeepLearning-
ModelSearch:Optimization,Regularization,AutoMLApplications:Neurallanguagemod
els
Teaching- Chalkandtalk/Powerpointpresentation
LearningProcess

61
EES 20.06.2023

AssessmentDetails(bothCIEandSEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
Theminimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of
themaximum marks of SEE.A student shall be deemed to have satisfied the academic requirements and earned
thecredits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the
sumtotaloftheCIE(Continuous InternalEvaluation)andSEE(SemesterEndExamination)takentogether.
ContinuousInternalEvaluation:
1) ThreeUnitTestseachof20Marks
2) Twoassignmentseachof20MarksoroneSkillDevelopmentActivityof40marks

62
EES 20.06.2023

toattain theCOsandPOs
Thesumofthreetests,twoassignments/skillDevelopmentActivities,willbescaleddownto50marks
CIEmethods/questionpaperisdesignedtoattainthedifferentlevelsofBloom’staxonomyaspertheoutcomedefin
edforthecourse.

SemesterEndExamination:
1) TheSEEquestionpaperwillbesetfor100marksandthemarksscoredwillbeproportionatelyreducedto50.
2) Thequestionpaperwillhavetenfullquestionscarryingequalmarks.
3) Eachfullquestionisfor20marks.Therewillbetwofullquestions(withamaximumoffoursub-
questions)fromeachmodule.
4) Eachfullquestionwillhaveasub-questioncoveringallthetopicsunderamodule.
5) Thestudentswillhavetoanswerfivefullquestions,selectingonefullquestionfromeachmodule

SuggestedLearningResources:
Books
1) Shalev-Shwartz,S.,Ben-
David,S.,(2014),UnderstandingMachineLearning:FromTheorytoAlgorithms,CambridgeUniversityPress
2) R.O.Duda,P.E.Hart,D.G.Stork(2000),PatternClassification,Wiley-Blackwell,2ndEdition
3) Goodfellow,I.,Bengio.,Y.,andCourville,A.,(2016),DeepLearning,TheMITPress
4) MitchellTom(1997).MachineLearning,TataMcGraw-Hill
5) C.M.BISHOP(2006),PatternRecognitionandMachineLearning,Springer-VerlagNewYork,1stEdition.
6) Charniak,E.(2019),Introductiontodeeplearning,TheMITPress.
WeblinksandVideoLectures(e-Resources):
3. DepartmentofComputerScience,StanfordUniversity,https://see.stanford.edu/Course/CS229
4. https://www.deeplearningbook.org/

SkillDevelopmentActivitiesSuggested:
1) Interactwithindustry(small,medium,andlarge).
2) Involvein research/testing/projectstounderstandtheirproblemsand helpcreative
andinnovativemethodstosolvetheproblem.
3) Involveincasestudiesandfieldvisits/fieldwork.
4) Accustomtotheuseofstandards/codesetc.,tonarrowthegapbetweenacademiaandindustry.
5) Handleadvancedinstrumentstoenhancetechnicaltalent.
6) Gainconfidenceinmodellingofsystemsandalgorithmsfortransientandsteady-stateoperations,thermalstudy,etc.
7) Workondifferentsoftware/s(tools)tosimulate,analyzeandauthenticatetheoutputtointerpretandconclude.

Allactivitiesshouldenhancestudent’sabilitiestoemploymentand/orself-
employmentopportunities,managementskills,Statisticalanalysis,fiscal expertise,etc.
Studentsandthecourseinstructor/stoinvolveeitherindividuallyoringroupstointeracttogethertoenhancethelearnin
gandapplicationskillsofthestudytheyhaveundertaken.Thestudentswiththehelpofthecourseteachercantakeuprelev
anttechnical–activitieswhichwillenhancetheirskill.ThepreparedreportshallbeevaluatedforCIEmarks.

Courseoutcome(CourseSkillSet)
Attheendofthecoursethestudentwillbeableto:
Sl.No. Description BloomsLevel
CO1 Formulateamachinelearningproblem L1,L2
CO2 Selectanappropriatepatternanalysistoolforanalyzingdatainagivenfeaturespace L4
CO3 Applypatternrecognitionandmachinelearningtechniquessuchasclassificationtopractic L3
alapplicationsanddetect patternsinthedata
CO4 Designefficientalgorithmsrelatedtorecentmachinelearningtechniques,trainmodels,an L3
ddevelop real-worldML-basedapplications

63
EES 20.06.2023

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEd
ucation(OBE)SEMESTER-III
MINIPROJECTWITHSEMINAR
CourseCode 22LVS25 CIEMarks 100
TeachingHours/Week(L:P:SDA) 0:4:2 SEEMarks -
TotalHoursofPedagogy - TotalMarks 100
Credits 03 ExamHours -
Courseobjectives:
 Tosupportindependentlearningandinnovativeattitude.
 Toguidetoselectandutilizeadequateinformationfromvariedresourcesupholdingethics.
 Toguidetoorganizetheworkintheappropriatemannerandpresentinformation(ack
nowledgingthesources)clearly.
 Todevelopinteractive,communication,organization,timemanagement,andpresentationskills.
 Toimpartflexibilityandadaptability.
 Toinspireindependenceandteamworking.
 Toexpandintellectualcapacity,credibility,judgment,intuition.
 Toadheretopunctuality,settingand meetingdeadlines.
 Toinstillresponsibilitiestooneselfandothers.
 To train students to present the topic of project work in a seminar without any fear, face
theaudienceconfidently,enhancecommunication skills,involvein groupdiscussion topresent
andexchangeideas.
Mini-Project with seminar :Eachstudentshall involve in carrying out the project work jointly
inconstantconsultationwithInternalguide,co-guide,andexternalguideandpreparetheprojectreportasper
thenormsavoidingplagiarism.
Courseoutcomes:
Attheendofthecoursethestudentwillbeableto:
 Presentthemini-projectandbeabletodefendit.
 Makelinksacrossdifferentareasofknowledgeandgenerate,developandevaluateidea
sandinformationso astoapplytheseskillstothe project task.
 Habituatedtocriticalthinkinganduseproblem-solvingskills.
 Communicateeffectivelyandtopresentideasclearlyandcoherentlyinbothwrittenandoralforms.
 Workinateamtoachieve acommongoal.
 Learnontheirown,reflectontheirlearningandtakeappropriateactionstoimproveit.

CIEprocedureforMini-Project:
The CIE marks awarded for Mini - Project, shall be based on the evaluation of Mini - Project Report,
ProjectPresentation skill and Question and Answer session in the ratio 50:25:25.The marks awarded for
Mini -Projectreportshallbethesameforallthebatchmates.

64
EES 20.06.2023

M.TECHVLSIDESIGN&EMBEDDEDSYSTEMS(LVS)
ChoiceBasedCredit System (CBCS)and
OutcomeBasedEducation(OBE)SEMESTER-II
VLSI&ESLab-2
CourseCode 22LVSL26 CIEMarks 40
TeachingHours/Week(L:T:P) 1:2:0 SEEMarks 60
Credits 02 ExamHours 03
Sl. Experiments
NO
PARTA:VLSIDesign.
ExperimentstobeconductedusingsuitableCADtool

1 DesignanInverterwithgivenspecifications*,completingthedesignflowmentionedbelow:
a. Drawtheschematicandverifythefollowing
i) DCAnalysis
ii) TransientAnalysis
b. DrawtheLayoutandverifytheDRC,ERC
c. CheckforXX
d. ExtractRCand backannotatethesameand verifytheDesign
e. Verify&OptimizeforTime,PowerandAreatothegivenconstraint***

2 Designthefollowingcircuitswithgivenspecifications*,completingthedesignflowmentionedbelow:
a. Drawtheschematicandverifythefollowing
i) DCAnalysis
ii) ACAnalysis
iii) TransientAnalysis
b. DrawtheLayoutandverifytheDRC,ERC,LVS
c. CheckforXX
d. ExtractRCand backannotatethesameand verifytheDesign
i) SingleStagedifferentialamplifier
ii) Commonsourceamplifier
iii) Designanop-
ampwithgivenspecification*usingdifferentialamplifierCommonsourc
eamplifierinlibrary**
iv) Designa4bitR-2RbasedDACforthegivenspecification**
3 DesignanIntegratorusingOPAMP(FirstOrder)

4 DesignaDifferentiatorusingOPAMP(FirstOrder)

5 DesignandcharacterizeabasicSigmadeltaADCfromtheavailabledesigns.

(Anyotherexperimentsmaybeaddedinsupportiveofthecourse)
*Appropriatespecificationshouldbegiven.
**ApplicableLibraryshouldbeadded&informationshouldbegiventotheDesigner.
***Anappropriateconstraintshouldbegiven

PARTB:RTOSprogramsusingClanguageinLINUXOS.

1 Developprogramsto(a)createchildprocessanddisplayitsidand
(b)Executechildprocessfunctionusingswitchstructure

2 Develop and test program foramultithreadedapplication,wherecommunicationis

throughabufferfortheconversionoflowercasetexttouppercasetext,usingsemaphoreconcept.

3 Developandtestprogramforamultithreadedapplication,wherecommunicationisthroughsharedmemor
yfortheconversionoflowercase texttouppercasetext.

4 Develop program for inter-thread communication using

messagequeue.Dataistobeinputfromthekeyboardforthechosenapplication.

65
EES 20.06.2023

5 Create‘n’numberofchildthreads.Eachthreadprintsthemessage“I’minthreadnumber…”andsleepsfor 50
ms and then quits. The main thread waits for complete execution of all the childthreads
andthenquits.Compileandexecute inLinux.

6 Implementtheusageofanonymouspipewith512bytesfordatasharingbetweenparentandchildprocesses
using handleinheritancemechanism.

Courseoutcomes:
Attheendofthecoursethestudentwillbeableto:
1. Design,implementandanalyseanalog,digitalandmixedmodecircuits
2. LearnthevariousissuesinMixedsignaldesignsbasicallydataconverters.
3. Acquirehands-
onskillsofusingCADtoolsinVLSIdesignandAppreciatethedesignprocessinVLSIthrough amini-
projectonthedesignofaCMOSsub-system.
4. ImplementdifferenttechniquesofmessagepassingandIntertaskcommunication.
5. Implementdifferentdatastructuressuchaspipes,queuesandbuffersinmultithreadedprogramminganda
lsoselect asuitabletaskswitchingtechniqueinamultithreadedapplication.
ConductofPracticalExamination:
All laboratory experiments are to be included for
practicalexamination.Forexamination,twoquestionsusingdifferent
tooltobeset.
Studentsareallowedtopickoneexperimentfromthelot.
Strictlyfollowtheinstructionsasprintedonthecoverpageofanswerscriptforbreakupof
marks.ChangeofexperimentisallowedonlyonceandMarksallottedtotheprocedureparttobemade
zero.

66
EES 20.06.2023

M.TECHVLSIDESIGN & EMBEDDEDSYSTEMS(LVS )

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)
SEMESTER-III
CADofDIGITALSYSTEMS
Course Code 22LVS31 CIE Marks 50
Teaching Hours/Week (L:P:SDA) 3:0:2 SEE Marks 50
Total Hours of Pedagogy 40Hours Theory + 10 -12 slots for
Total Marks 100
Skill Development Activities
Credits 04 Exam Hours 3

Course Learning objectives:

 To learn the algorithms to design digital systems .
 To understand the optimization methods .
 To learn minimization the area of the design .
 To learn the selection of CAD problems and algorithms to solve them with simulation, logic synthesis,
highlevel synthesis, and several aspects of layout design, the wide range of VLSI design automation tools .
Module-1
IntroductiontoDesignMethodologies:TheVLSIDesignProblem,TheDesignDomains,DesignActions,DesignMethod
sandTechnologies.
VLSIDesignAutomationtools:AlgorithmicandSystemDesign,StructuralandLogicDesign,Transistor-
levelDesign,LayoutDesign, VerificationMethods.
Algorithmicgraphtheoryandcomputationalcomplexity:Terminology,DataStructuresfortheRepresentationofGr
aphs,Computational Complexity, ExamplesofGraphAlgorithms.
Tractableandintractableproblems:DecisionProblems,ComplexityClasses,NP-completenessandNP-hardness,
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-2
Generalpurposemethodsforcombinationaloptimization:BacktrackingandBranch-and-
bound,DynamicProgramming, Integer Linear Programming, Local Search, Simulated Annealing, Tabu Search,
Genetic Algorithms,AFewFinal RemarksonGeneral-purpose Methods.
Layoutcompaction:DesignRules,SymbolicLayout,ProblemFormulation,AlgorithmsforConstraint-
graphCompaction,OtherIssues.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-3
Placementandpartitioning:CircuitRepresentation,Wire-
lengthEstimation,TypesofPlacementProblem,PlacementAlgorithm, Partitioning.
Floorplanning:FloorplanningConcepts,ShapeFunctionsandFloorplanSizing.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-4
Routing:TypesofLocalRoutingProblems,AreaRouting,ChannelRouting,IntroductiontoGlobalRouting,Algorithms
for Global Routing.
Simulation:GeneralRemarksonVlSlSimulation,Gate-levelModelingandSimulation,Switch-
levelModelingandSimulation.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-5
Logic Synthesis and Verification: Introduction to Combinational Logic Synthesis, Binary-decision Diagrams,
Two-levelLogic Synthesis
Highlevelsynthesis:HardwareModelsforHighLevelSynthesis,InternalRepresentationoftheInputAlgorithm,All
ocation, Assignment and Scheduling, Some Scheduling Algorithm, Some Aspects of the Assignment Problem.
Teaching- Chalk and talk/Power point presentation 67
Learning
Process
EES 20.06.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of the
maximum marks of SEE. A student shall be deemed to have satisfied the academic requirements and earned the
credits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
1. Three Unit Tests each of 20 Marks
2. Two assignments each of 20 Marks or one Skill Development Activity of 40 marks
to attain the COs and POs
The sum of three tests, two assignments/skill Development Activities, will be scaled down to 50 marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per the
outcome defined for the course.

Semester End Examination:

1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to
50.
2. The question paper will have ten full questions carrying equal marks.
3. Each full question is for 20 marks. There will be two full questions (with a maximum of four sub-questions)
from each module.
4. Each full question will have a sub-question covering all the topics under a module.
5. The students will have to answer five full questions, selecting one full question from each module
.
Suggested Learning Resources:
Books.
 S H Gerez Algorithms for VLSI Design Automation ,Wiley, India 2nd Edition
 N.A. Sherwani Algorithms for VLSI Physical Design Automation Springer International edition 3rd Edition

Web links and Video Lectures (e-Resources):

 https://www.youtube.com/watch?v=FVmsr-c6g3k
 https://www.youtube.com/watch?v=gRC7C_PtfYw

Skill Development Activities Suggested

1) Interact with industry (small, medium, and large).
2) Involve in research/testing/projects to understand their problems and help creative and innovative
methods to solve the problem.
3) Involve in case studies and field visits/ fieldwork.
4) Accustom to the use of standards/codes etc., to narrow the gap between academia and industry.
5) Handle advanced instruments to enhance technical talent.
6) Gain confidence in modelling of systems and algorithms for transient and steady-state operations, thermal
study, etc.
7) Work on different software/s (tools) to simulate, analyze and authenticate the output to interpret and
conclude.

All activities should enhance student’s abilities to employment and/or self-employment opportunities,
management skills, Statistical analysis, fiscal expertise, etc.
Students and the course instructor/s to involve either individually or in groups to interact together to enhance
the learning and application skills of the study they have undertaken. The students with the help of the course
teacher can take up relevant technical –activities which will enhance their skill. The prepared report shall be
evaluated for CIE marks.

68
EES 20.06.2023

Course outcome (Course Skill Set)

At the end of the course the student will be able to :

Sl. No. Description Blooms Level
CO1 Understand the various design methodologies. L2
CO2 Solve graph theoretic problems. L3 ,L5
CO3 Evaluate the computational complexity of an algorithm. L5
CO4 Write algorithms for VLSI Automation. L1
CO5 Simulate and synthesize digital circuits using VLSI automation tools. L4

69
EES 20.06.2023

M.TECHVLSIDESIGN & EMBEDDEDSYSTEMS(LVS)

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation (OBE)
SEMESTER–III
FinFETs and Other Multi-Gate Transistors
Course Code 22LVS321 CIE
50
Marks
3:0:0 SEE
Teaching Hours/Week (L:P:SDA) 50
Marks
Total Hours of Pedagogy 40 Total
100
Marks
Credits 03 Exam
3
Hours
Course Learning Objectives:
 To learn the evolution of SOI MOS transistor.
 To have an insight into thin film formation techniques and advanced gate stack deposition.
 To enable the students to analyse physics behind BSIM-CMG.
 To analyse the electrostatics of the multi-gate MOS system.
 To realise the interrelationship between the multi-gate FET device properties and digital and analog circuits.
Module-1
The SOI MOSFET: From Single Gate to MultiGate:
A brief history of Multiple - Gate MOSFETs, MultiGate MOSFET physics.

Teaching- Chalk and talk method/Power Point Presentation

Learning Process
Module-2
Multigate MOSFET Technology : Introduction, Active Area:Fins, Gate Stack

Teaching- Chalk and talk method/Power Point Presentation

Learning Process
Module-3
BSIM- CMG: A Compact Model for Mult-Gate Transistors : Introduction, Framework for MultiGate FET Modeling,
MultiGate Models, BSIM-CMG and BSIM-IMG, BSIM-CMG.

Teaching- Chalk and talk method/Power Point Presentation

Learning Process
Module-4
Physics of the MultiGate MOS system : Device electrostatics, Double gate MOS system, Two-dimensional
confinement.
Teaching- Chalk and talk method/Power Point Presentation
Learning Process
Module-5
Multi-Gate MOSFET circuit Design : Introduction, Digital Circuit Design, Analog Circuit Design
Teaching- Chalk and talk method/Power Point Presentation, Demonstration of circuits.
Learning Process
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of the
maximum marks of SEE. A student shall be deemed to have satisfied the academic requirements and earned the
credits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
1) Three Unit Tests each of 20 Marks
2) Two assignments each of 20 Marks or one Skill Development Activity of 40 marks
to attain the COs and POs 61
0
The sum of three tests, two assignments/skill Development Activities, will be scaled down to 50 marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per the
outcome defined for the course
Semester End Examination:
EES 20.06.2023

1) The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to 50.
2) The question paper will have ten full questions carrying equal marks.
3) Each full question is for 20 marks. There will be two full questions (with a maximum of four sub-questions)
from each module.
4) Each full question will have a sub-question covering all the topics under a module.
5) The students will have to answer five full questions, selecting one full question from each module

Suggested Learning Resources:

Books
1) J.P.Colinge,: FinFETs and other Multi-Gate Transistors, springer, Series on Integrated Circuits and Systems.
2) Samar Saha, : Fin FET Devices for VLSI Circuits and Systems, CRC Press, First Edition, 2020
3) Weihua Han,Zhiming M. Wang, : Toward Quantum FinFET , Springer Cham, First Edition 2021.
4) Yogesh singh Chauhan, Darsen D, et.al , FinFET Modeling for IC Simulation and Design: using the BSIM-CMG
standard, Academic Press, 2015.

Web links and Video Lectures (e-Resources) :

1. http://www.ee.iitb.ac.in
2. http://online courses.nptel.ac.in
3. http;//icmaskdesign.com
4. http;//link.springer.com
Skill Development Activities Suggested
 Assignments
 Seminar
 Literature survey
Skill Development Activities Suggested:
1) Interact with industry (small, medium, and large).
2) Involve in research/testing/projects to understand their problems and help creative and innovative methods to
solve the problem.
3) Involve in case studies and field visits/ fieldwork.
4) Accustom to the use of standards/codes etc., to narrow the gap between academia and industry.
5) Handle advanced instruments to enhance technical talent.
6) Gain confidence in modelling of systems and algorithms for transient and steady-state operations, thermal
study, etc.
7) Work on different software/s (tools) to simulate, analyze and authenticate the output to interpret and conclude.

All activities should enhance student’s abilities to employment and/or self-employment opportunities,
management skills, Statistical analysis, fiscal expertise, etc.
Students and the course instructor/s to involve either individually or in groups to interact together to enhance
Course outcome
the learning and(Course Skillskills
application Set)of the study they have undertaken. The students with the help of the course
At the end of the course the student will be able to:
–
Sl. Description Blooms
No. Level
CO List out the advantages and challenges of Multi-gate Fin FETs. L2
1
CO Describe thin film formation technique, gate stack deposition and physics beyond BSIM- L3
2 CMG.
CO Analyse electrostatics of multi-gate MOS system and corelate multigate FET device L3
3 properties and elementary digital and analog circuits.

61
1
EES 20.06.2023

M.TECHVLSIDESIGN & EMBEDDEDSYSTEMS(LVS)

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation (OBE)
SEMESTER-III
Internetof Things
Course Code 22LVS322 CIE Marks 50
Teaching Hours/Week (L:P:SDA) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 3
Course Learning objectives:
 To understand the concepts of IOT and its applications in today’s scenario.
 To study the IoT network architecture and design.
 To Understand IOT content generation and transport through networks use cases of IoT.
 To Understand the devices employed for IOT data acquisition.

Module-1
WhatisIoT?
Genesis,Digitization,Impact,ConnectedRoadways,Buildings,Challenges
IoTNetworkArchitectureandDesign
DriversbehindnewnetworkArchitectures,ComparingIoTArchitectures,M2Marchitecture,IoTworldforumstandard,I
oTReference Model, Simplified IoTArchitecture.
Teaching- Chalk and talk , Power point presentation ,NPTEL ,VTU E-learning resources , Experimental
Learning learning, Problem based learning
Process
Module-2
IoTNetworkArchitectureandDesign
CoreIoTFunctionalStack,Layer1(SensorsandActuators),Layer2(CommunicationsSublayer),Accessnetworksublayer,
Gatewaysand backhaulsublayer,Networktransportsublayer,IoTNetwork management.
Layer3(ApplicationsandAnalytics)–AnalyticsvsControl,DatavsNetworkAnalytics,IoTDataManagementand
Compute Stack

Teaching- . Chalk and talk , Power point presentation ,NPTEL ,VTU E-learning resources , Experimental
Learning learning, Problem based learning
Process
Module-3
EngineeringIoTNetworks
Things in IoT – Sensors, Actuators, MEMS and smart
objects.Sensornetworks,WSN,CommunicationprotocolsforWSN
CommunicationsCriteria,Range,Frequencybands,powerconsumption,Topology,ConstrainedDevices,Constrained
Node Networks
IoTAccessTechnologies,IEEE802.15.4
CompetitiveTechnologies–OverviewonlyofIEEE802.15.4g,4e,IEEE1901.2aStandard Alliances–LTECat0, LTE-M,NB-
IoT
Teaching- Chalk and talk , Power point presentation ,NPTEL ,VTU E-learning resources , Experimental
Learning learning, Problem based learning
Process
Module-4
EngineeringIoTNetworks
IPasIoT
networklayer,KeyAdvantages,Adoption,Optimization,ConstrainedNodes,ConstrainedNetworks,IPversions,Optimizi
ngIPfor IoT. ApplicationProtocolsforIoT–
TransportLayer,ApplicationTransportlayer,BackgroundonlyofSCADA,Genericwebbasedprotocols,
IoTApplicationLayer
DataandAnalyticsforIoT–Introduction,StructuredandUnstructureddata,IoTDataAnalyticsoverviewandChallenges.
Teaching- Chalk and talk , Power point presentation ,NPTEL ,VTU E-learning resources , Experimental
Learning learning, Problem based learning
Process 61
Module-5 2
IoTinIndustry(ThreeUsecases)
IoTStrategyforConnectedmanufacturing,ArchitectureforConnectedFactory
Utilities–Powerutility,IT/OTdivide,Gridblocksreferencemodel,ReferenceArchitecture,Primarysubstationgrid
blockandautomation.
EES 20.06.2023

Smart andConnectedcities–Strategy,Smartcity networkArchitecture,Streetlayer,city

layer,Datacenterlayer,serviceslayer, Smartcitysecurityarchitecture,Smartstreet lighting.

Teaching- Chalk and talk/Power point presentation

Learning
Process
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of the
maximum marks of SEE. A student shall be deemed to have satisfied the academic requirements and earned the
credits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
1. Three Unit Tests each of 20 Marks
2. Two assignments each of 20 Marks or one Skill Development Activity of 40 marks
to attain the COs and POs
The sum of three tests, two assignments/skill Development Activities, will be scaled down to 50 marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per the
outcome defined for the course.
Semester End Examination:
1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to
50.
2. The question paper will have ten full questions carrying equal marks.
3. Each full question is for 20 marks. There will be two full questions (with a maximum of four sub-questions)
from each module.
4. Each full question will have a sub-question covering all the topics under a module.
5. The students will have to answer five full questions, selecting one full question from each module
.
Suggested Learning Resources:
1. David Hanes, Gonzalo Salgueiro, Patrick Grossetete, Robert Barton, Jerome Henry, “Cisco, IOT Fundamentals
– Networking Technologies, Protocols, Use Cases for IOT”, Pearson Education; First edition 2017, ISBN: 978-
9386873743.
2. Arshdeep Bahga and Vijay Madisetti, “Internet of Things – A Hands on Approach”, Orient Blackswan Private
Limited - New Delhi; First edition

Web links and Video Lectures (e-Resources):

1. https://archive.nptel.ac.in/courses/106/105/106105166/
2. https://www.youtube.com/watch?v=urUBLmXFKl0&list=PLgMDNELGJ1CaBrefq-0eYatfOnoncW0y-
3. https://www.youtube.com/watch?v=Yci9PfPppiw&list=PLgMDNELGJ1CZoUIF-iKcH9TSVcmG6IBcU
Skill Development Activities Suggested
1) Interact with industry (small, medium, and large).
2) Involve in research/testing/projects to understand their problems and help creative and innovative methods
to solve the problem.
3) Involve in case studies and field visits/ fieldwork.
4) Accustom to the use of standards/codes etc., to narrow the gap between academia and industry.
5) Handle advanced instruments to enhance technical talent.
6) Gain confidence in modelling of systems and algorithms for transient and steady-state operations, thermal
study, etc.
7) Work on different software/s (tools) to simulate, analyze and authenticate the output to interpret and
conclude.
All activities should enhance student’s abilities to employment and/or self-employment opportunities,
management skills, Statistical analysis, fiscal expertise, etc.
Students and the course instructor/s to involve either individually or in groups to interact together to enhance
the learning and application skills of the study they have undertaken. The students with the help of the course
teacher can take up relevant technical –activities which will enhance
61 their skill. The prepared report shall be
3
evaluated for CIE marks.
EES 20.06.2023

Course outcome (Course Skill Set)

At the end of the course the student will be able to :

Sl. No. Description Blooms Level
CO1 Understand the basic concepts IoT Architecture and devices employed. L1, L2
CO2 Analyze the sensor data generated and map it to IoT protocol stack for transport. L2, L3
CO3 Apply communications knowledge to facilitate transport of IoT data over various
L2, L3
available communications media.
CO4 Design a use case for a typical application in real life ranging from sensing devices to
L3, L4
analyzing the data available on a server to perform tasks on the device.
CO5 Apply knowledge of Information technology to design the IoT applications. L3, L4

61
4
EES 20.06.2023

M.TECHVLSIDESIGN & EMBEDDEDSYSTEMS(LVS)

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation (OBE)
SEMESTER-III
VLSIDesignforSignalProcessing
Course Code 22LVS323 CIE Marks 50
Teaching Hours/Week (L:P:SDA) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 03

Course Learning objectives:

 To learn the Transformations for high speed design using pipelining, retiming, and parallel processing
techniques
 To understand the Power reduction transformations for supply voltage reduction as well as for strength or
capacitance reduction
 To analyse area reduction using folding techniques
 To create Strategies for arithmetic implementation
 To understand Synchronous, wave, and asynchronous pipelining
Module-1
IntroductiontoDSPSystems:TypicalDSPAlgorithms,DSPApplicationDemandsandScaledCMOSTechnologies,Repre
sentationsofDSPAlgorithms.
IterationBounds:DataflowgraphRepresentations,loopboundandIterationbound.AlgorithmsforComputingIterati
onBound, IterationBound ofmultirate dataflow graphs.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-2
Pipeliningand ParallelProcessing: pipelining of
FIRDigitalFilters,parallelprocessing,Pipeliningandparallelprocessing for lowpower.
Retiming:DefinitionandProperties,SolvingSystemsofInequalities,RetimingTechniques.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-3
Unfolding:AnAlgorithmforUnfolding,PropertiesofUnfolding,Criticalpath,UnfoldingandRetiming,ApplicationofUnfo
lding.
Folding:FoldingTransformation,RegisterMinimizationTechniques,RegisterMinimizationinFoldedArchitectures,F
oldingofMultirate Systems.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-4
Systolic Architecture Design: systolic array design Methodology, FIR systolic array, Selection of
SchedulingVector, Matrix-Matrix Multiplication and 2D systolic Array Design, Systolic Design forspace
representationcontainingDelays.
Fast convolution: Cook-Toom Algorithm, Winograd Algorithm, Iterated convolution, cyclic convolution
DesignoffastconvolutionAlgorithmbyInspection.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-5
Pipelined and Parallel Recursive and Adaptive Filter: Pipeline Interleaving in Digital Filter, first order
IIRdigital Filter, Higher order IIR digital Filter, parallel processing for IIR filter, Combined pipelining and
parallelprocessingforIIRFilter,LowpowerIIRFilterDesignUsingPipeliningandparallelprocessing,pipelined
adaptivedigitalfilter.
Teaching- Chalk and talk/Power point presentation 61
Learning 5
Process
EES 20.06.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of the
maximum marks of SEE. A student shall be deemed to have satisfied the academic requirements and earned the
credits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
1. Three Unit Tests each of 20 Marks
2. Two assignments each of 20 Marks or one Skill Development Activity of 40 marks
to attain the COs and POs
The sum of three tests, two assignments/skill Development Activities, will be scaled down to 50 marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per the
outcome defined for the course.

Semester End Examination:

1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to
50.
2. The question paper will have ten full questions carrying equal marks.
3. Each full question is for 20 marks. There will be two full questions (with a maximum of four sub-questions)
from each module.
4. Each full question will have a sub-question covering all the topics under a module.
5. The students will have to answer five full questions, selecting one full question from each module
.
Suggested Learning Resources:
Books.
1. Keshab K.Parthi ,VLSI Digital Signal Processing systems, Design and implementation,Wiley,1999
2. Mohammed Isamail and Terri Fiez ,Analog VLSI Signal and Information Processing,Mc Graw-Hill,1994
3. S.Y. Kung, H.J. White House, T. Kailath,VLSI and Modern Signal Processing,Prentice Hall,1985
4. Jose E. France, Yannis Tsividis,Design of Analog - Digital VLSI Circuits for Telecommunication and
Signal Processing.Prentice Hall,1994
5. Lars Wanhammar,DSP Integrated Circuits,Academic Press Series in Engineering,1stEdition

Web links and Video Lectures (e-Resources):

 https://www.youtube.com/watch?v=3UZdP-bTJtQ&list=PL3p-ZpXPqK6vvxeTp1k4kDMJj74WIetyC
 https://www.youtube.com/watch?v=BJE0wWb5HL4&list=PL3pZpXPqK6vvxeTp1k4kDMJj74WIetyC&index=
2

Skill Development Activities Suggested

1) Interact with industry (small, medium, and large).
2) Involve in research/testing/projects to understand their problems and help creative and innovative methods
to solve the problem.
3) Involve in case studies and field visits/ fieldwork.
4) Accustom to the use of standards/codes etc., to narrow the gap between academia and industry.
5) Handle advanced instruments to enhance technical talent.
6) Gain confidence in modelling of systems and algorithms for transient and steady-state operations, thermal
study, etc.
7) Work on different software/s (tools) to simulate, analyze and authenticate the output to interpret and
conclude.

All activities should enhance student’s abilities to employment and/or self-employment opportunities,
management skills, Statistical analysis, fiscal expertise, etc.
Students and the course instructor/s to involve either individually or in groups to interact together to enhance
the learning and application skills of the study they have undertaken. The students with the help of the course
teacher can take up relevant technical –activities which will enhance
61 their skill. The prepared report shall be
6
evaluated for CIE marks.
Course outcome (Course Skill Set)
At the end of the course the student will be able to :
EES 20.06.2023

Sl. No. Description Blooms Level

CO1 Illustrate the use of various DSP algorithms and addresses their representation using L3 ,L6
block diagrams, signal flow graphs and data-flow graphs
CO2 Use pipelining and parallel processing in design of high-speed /low-power L6
applications
CO3 Apply unfolding in the design of parallel architecture. L3
CO4 Evaluate the use of look-ahead techniques in parallel and pipelined IIR Digital filters. L5
CO5 Develop an algorithm or architecture or circuit design for DSP applications L6

61
7
EES 20.06.2023

M.TECHVLSIDESIGN & EMBEDDEDSYSTEMS(LVS)

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)
SEMESTER-II
ADVANCES IN IMAGE PROCESSING
Course Code 22LVS324 CIE Marks 50
Teaching Hours/Week (L:P:SDA) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 03
Course Learning objectives:
 Acquirefundamentalknowledgeinunderstandingtherepresentationofthedigitalimageanditsp
roperties
 Equipwithsomepre-
processingtechniquesrequiredtoenhancetheimageforfurtheranalysispurpose.
 Selecttheregionofinterestintheimageusingsegmentationtechniques.
 Representtheimagebasedonitsshapeandedgeinformation.
 Describetheobjectspresentintheimagebasedonitspropertiesand structure .

Module-1
The image, its representations and properties:
Imagerepresentationsafewconcepts,Imagedigitization,Digitalimage
properties,Colorimages.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-2
Image Pre-processing: Pixel brightness
transformations,geometrictransformations,localpre-processing.

Teaching- Chalk and talk/Power point presentation

Learning
Process
Module-3
Segmentation: Thresholding; Edge-based segmentation –
Edgeimagethresholding,Edgerelaxation,Bordertracing,Houghtransforms;Region–
basedsegmentation–Regionmerging,Region splitting, Splitting and merging, Watershed
segmentation,Regiongrowingpost-processing.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-4
Shaperepresentationanddescription:Regionidentification;Contour-
basedshaperepresentationanddescription–
Chaincodes,Simplegeometricborderrepresentation,Fouriertransformsofboundaries,Boundarydesc
riptionusingsegmentsequences,B-splinerepresentation;Region-
basedshaperepresentationanddescription–Simplescalarregiondescriptors, Moments,Convexhull.

Teaching- Chalk and talk/Power point presentation

Learning
Process
Module-5
MathematicalMorphology:Basicmorphologicalconcepts,Fourmorphologicalprinciples,Binarydilati
onanderosion, Skeletonsandobjectmarking,Morphologicalsegmentationsand watersheds

Teaching- Chalk and talk/Power point presentation

Learning
Process
61
8
EES 20.06.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of the
maximum marks of SEE. A student shall be deemed to have satisfied the academic requirements and earned the
credits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
1. Three Unit Tests each of 20 Marks
2. Two assignments each of 20 Marks or one Skill Development Activity of 40 marks
to attain the COs and POs
The sum of three tests, two assignments/skill Development Activities, will be scaled down to 50 marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per the
outcome defined for the course.

Semester End Examination:

1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to
50.
2. The question paper will have ten full questions carrying equal marks.
3. Each full question is for 20 marks. There will be two full questions (with a maximum of four sub-questions)
from each module.
4. Each full question will have a sub-question covering all the topics under a module.
5. The students will have to answer five full questions, selecting one full question from each module
.
Suggested Learning Resources:
Books
 MilanSonka,Vaclav Hlavac, Roger Boyle, “Image Processing,
Analysis,andMachineVision”,CengageLearning,2013,ISBN:978-81-315-1883-0

 GeoffDoughertry,DigitalImageProcessingforMedicalApplications,CambridgeuniversityPres
s,2010
 S.Jayaraman,SEsakkirajan,T.Veerakumar,DigitalImageProcessing,TataMcGrawHill,2011

Web links and Video Lectures (e-Resources):

https://www.youtube.com/watch?v=EcSvZIFIz6c
https://www.youtube.com/watch?v=RXLPYdBQRtU

Skill Development Activities Suggested

1. Interact with industry (small, medium, and large).
2. Involve in research/testing/projects to understand their problems and help creative and innovative
methods to solve the problem.
3. Involve in case studies and field visits/ fieldwork.
4. Accustom to the use of standards/codes etc., to narrow the gap between academia and industry.
5. Handle advanced instruments to enhance technical talent.
6. Gain confidence in modelling of systems and algorithms for transient and steady-state operations,
thermal study, etc.
7. Work on different software/s (tools) to simulate, analyze and authenticate the output to interpret and
conclude.

All activities should enhance student’s abilities to employment and/or self-employment opportunities,
management skills, Statistical analysis, fiscal expertise, etc. Students and the course instructor/s to involve
either individually or in groups to interact together to enhance the learning and application skills of the
study they have undertaken. The students with the help of the course teacher can take up relevant
technical –activities which will enhance their skill. The prepared report shall be evaluated for CIE marks.

61
9
EES 20.06.2023

Course outcome (Course Skill Set)

At the end of the course the student will be able to :

Sl. No. Description Blooms Level
CO1 Understandtherepresentationofthedigitalimageanditsproperties L1
CO2 Applypre-processingtechniquesrequiredtoenhancetheimageforits L1,L2
furtheranalysis.
CO3 Usesegmentationtechniquestoselecttheregionofinterestintheimageforanal L1,L2,L3
ysis
CO4 Representtheimagebasedonitsshapeandedgeinformation. L1,L2,L3
CO5 Describetheobjectspresentintheimagebasedonitspropertiesandstructure. L1,L2,L3

62
0
EES 20.06.2023

M.TECHVLSIDESIGN & EMBEDDEDSYSTEMS(LVS)

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)
SEMESTER-III
Advanced Computer Architecture
Course Code 22LVS325 CIE Marks 50
Teaching Hours/Week (L:P:SDA) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 03

Course Learning objectives:

 To understand the advanced design principles of modern processors and parallelism.

 To learn different Pipelining&SuperscalarTechnologies for processors.
 To know different techniques of ParallelProgrammingModels, Languages&Compilers.

Module-1
ParallelComputerModels:TheStateofComputing,Multiprocessorsandmulticomputers,MultivectorandSIMDcomp
uters.
ProgramandNetworkProperties:Conditionsofparallelism,ProgramPartitioning&Scheduling,ProgramFlowMech
anisms.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-2
PrinciplesofScalablePerformance:PerformanceMetricsandMeasures,ParallelProcessingApplications,Speedup
Performance Laws, ScalabilityAnalysisandApproaches.
Processors&MemoryHierarchy:Advancedprocessortechnology,SuperScalars&VectorProcessors,MemoryHierar
chyTechnology, Virtual MemoryTechnology.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-3
Bus,CacheandSharedMemory:BusSystems,CacheMemoryOrganizations,SharedMemoryOrganizations,Sequential
&WeakConsistencyModel.
Pipelining&SuperscalarTechnologies:LinearPipelineProcessors,NonlinearPipelineProcessors,InstructionPipel
ineDesign,ArithmeticPipeline Design,SuperscalarPipelineDesign.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-4
Multivector&SIMDComputers:
VectorProcessingprinciples,MultivectorMultiprocessors,CompoundVectorP
rocessing, SIMD ComputerOrganization.
Scalable, Multithreaded and Data Flow Computers: Latency Hiding Techniques, Principles of
Multithreading,FineGrainMultiComputers,
ScalableandMultithreadedArchitectures,DataFlowandHybridArchitectures.
Teaching- Chalk and talk/Power point presentation
Learning
Process
Module-5
ParallelModels,LanguagesandCompilers:ParallelProgrammingModels,ParallelLanguages&Compilers,Dependen
ce Analysis and Data Arrays, Code Optimization and Scheduling, Loop Parallelization and
Pipelining.ParallelProgramDevelopmentandEnvironments:ParallelProgrammingEnvironments,Synchronizati
onand
MultiProcessorModes,SharedVariableProgramStructures. 62
Teaching- Chalk and talk/Power point presentation 1
Learning
Process
EES 20.06.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of the
maximum marks of SEE. A student shall be deemed to have satisfied the academic requirements and earned the
credits allotted to each subject/ course if the student secures not less than 50% (50 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
1. Three Unit Tests each of 20 Marks
2. Two assignments each of 20 Marks or one Skill Development Activity of 40 marks
to attain the COs and POs
The sum of three tests, two assignments/skill Development Activities, will be scaled down to 50 marks
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per the
outcome defined for the course.

Semester End Examination:

1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to
50.
2. The question paper will have ten full questions carrying equal marks.
3. Each full question is for 20 marks. There will be two full questions (with a maximum of four sub-questions)
from each module.
4. Each full question will have a sub-question covering all the topics under a module.
5. The students will have to answer five full questions, selecting one full question from each module
.
Suggested Learning Resources:
Books
1. Kai Hwang & Narendra Jotwani,Advanced Computer Architecture: Parallelism,
Scalability,Programmability,McGraw Hill Education, ISBN: 978-93-392-2092-1,3rd Edition,2016.
2. M.J. Flynn,Computer Architecture, Pipelined and Parallel Processor Design,Narosa Publishing,2002
3. Michael J Quinn,Parallel programming in C with MPI and OpenMP,Tata McGraw Hill,2013
4. Ananth Grama,An Introduction to Parallel Computing: Design and Analysis of Algorithms,Pearson,2nd
Edition,2004

Web links and Video Lectures (e-Resources):

 https://www.youtube.com/watch?v=v7iefsovo9M&list=PLwdnzlV3ogoWJhBxBYu-K4l-q-nNHd24D
 https://www.youtube.com/watch?v=4goj-ajnpOQ&list=PLwdnzlV3ogoWJhBxBYu-K4l-q-
nNHd24D&index=2
Skill Development Activities Suggested
1. Interact with industry (small, medium, and large).
2. Involve in research/testing/projects to understand their problems and help creative and innovative methods to
solve the problem.
3. Involve in case studies and field visits/ fieldwork.
4. Accustom to the use of standards/codes etc., to narrow the gap between academia and industry.
5. Handle advanced instruments to enhance technical talent.
6. Gain confidence in modelling of systems and algorithms for transient and steady-state operations, thermal
study, etc.
7. Work on different software/s (tools) to simulate, analyze and authenticate the output to interpret and conclude.

All activities should enhance student’s abilities to employment and/or self-employment opportunities,
management skills, Statistical analysis, fiscal expertise, etc.
Students and the course instructor/s to involve either individually or in groups to interact together to
enhance the learning and application skills of the study they have undertaken. The students with the help
of the course teacher can take up relevant technical –activities which will enhance their skill. The prepared
report shall be evaluated for CIE marks. 62
2
EES 20.06.2023

Course outcome (Course Skill Set)

At the end of the course the student will be able to :
Sl. No. Description Blooms Level
CO1 Understand the basic concepts for parallel processing L2
CO2 Analyze program partitioning and flow mechanisms L4
CO3 Apply pipelining concept for the performance evaluation L3
CO4 Learn the advanced processor architectures for suitable applications L1
CO5 Understand parallel Programming L2

62
3
 EES 20.06.2023

Reconfigurable Computing Semester III

Course Code 22LVS331 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0:0 SEE Marks 50
Total Hours of Pedagogy 40 10
Total Marks
0
Credits 03 Exam Hours 3
Examination type (SEE) Theory

Course objectives:
This course will enable students to:
 To learn the various Reconfigurable systems.
 To study the different Languages and Compilation.
 To understand the Implementation of FPGA.
 To learn Partial Reconfiguration Design
 To understand the Signal Processing Applications

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Chalk and Talk.
2. Power Presentation and Videos.
3. Flipped Classes.
4. Practice Sessions

Module-1
Introduction: History, Reconfigurable vs Processor based system, RC Architecture.
Reconfigurable Logic Devices: Field Programmable Gate Array, Coarse Grained ReconfigurableArrays.
Reconfigurable Computing System: Parallel Processing on Reconfigurable Computers, A survey
ofReconfigurable Computing System. (Text 1)
Module-2
Languages and Compilation: Design Cycle, Languages, HDL, High Level Compilation, Low level Design
flow, Debugging Reconfigurable Computing Applications. (Text 1)

Module-3
Implementation: Integration, FPGA Design flow, Logic Synthesis.
High Level Synthesis for Reconfigurable Devices: Modelling, Temporal Partitioning Algorithms. (Text 2)

Module-4
Partial Reconfiguration Design: Partial Reconfiguration Design, Bitstream Manipulation with JBits, The
modular Design flow, The Early Access Design Flow, Creating Partially Reconfigurable Designs, Partial
Reconfiguration using Hansel-C Designs, Platform Design. (Text 2)

Module-5
Signal Processing Applications: Reconfigurable computing for DSP, DSP application building blocks, Examples:
Beamforming, Software Radio, Image and video processing, Local Neighbourhood functions, Convolution.
(Text 1) System on a Programmable Chip: Introduction to SoPC, Adaptive Multiprocessing on Chip.(Text 2)
Course outcome (Course Skill Set)
At the end of the course the student will be able to:
1. Understand the fundamental principles and practices in reconfigurable architecture.
2. Simulate and synthesize the reconfigurable computing architectures.
3. Understand the FPGA design principles, and logic synthesis
4. Integrate hardware and software technologies for reconfiguration computing focusing on partial
reconfiguration design. 62
5. Design digital systems for a variety of applications on signal
4 processing and system on chip
configurations
EES 20.06.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation:

 For the Assignment component of the CIE, there are 25 marks and for the Internal Assessment Test
component, there are 25 marks.
 The first test will be administered after 40-50% of the syllabus has been covered, and the second test will
be administered after 85-90% of the syllabus has been covered
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only one
assignment for the course shall be planned. The teacher should not conduct two assignments at the end of
the semester if two assignments are planned.
 For the course, CIE marks will be based on a scaled-down sum of two tests and other methods of
assessment.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Text Books
1.Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays M. Gokhale
and P. Graham Springer, ISBN: 978-0-387-26105-8 2005
2 . Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications C. Bobda
Springer, ISBN: 978-1-4020-6088-5 2007
Reference Books
1.Practical FPGA Programming in C D. Pellerin and S. Thibault Prentice-Hall 2005
2. FPGA Based System Design W. Wolf Prentice-Hall 2004
3. Rapid System Prototyping with FPGAs: Accelerating the Design Process R. Cofer and B. Harding Newnes
2005

Web links and Video Lectures (e-Resources):

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 https://in.video.search.yahoo.com/search/video;_ylt=Awrx.wZl4Ypkq6UWE__mHAx.;_ylu=c2VjA3NlY
XJjaARzbGsDYXNzaXN0;_ylc=X1MDMjExNDcyMzA0NgRfcgMyBGZyA21jYWZlZQRmcjIDc2EtZ3Atc2V
hcmNoBGdwcmlkA2NuaGlIRklzUi55VndlNThEcHUwV0EEbl9yc2x0AzAEbl9zdWdnAzkEb3JpZ2luA2l
uLnZpZGVvLnNlYXJjaC55YWhvby5jb20EcG9zAzEEcHFzdHIDTlBUIEZPUiBWSURPUyBSRUNPTkZPUk
FHQUJMRSBDT01QVVRJTkcEcHFzdHJsAzM4BHFzdHJsAzQ3BHF1ZXJ5A25wdCUyMGZvciUyMHZpZG
VvcyUyMHJlY29uZm9yYWdhYmxlJTIwY29tcHV0aW5nJTIwZGV2aWNlcwR0X3N0bXADMTY4NjgyMz
I4MAR1c2VfY2FzZQM-?p=npt+for+videos+reconforagable+computing+devices&ei=UTF-8&fr2=sa-
gp-
search&fr=mcafee&type=E211IN1274G0#id=1&vid=046ac2290e69d7656fe0294da81a9091&action
=view
 https://in.video.search.yahoo.com/search/video;_ylt=Awrx.waZ4YpkUqQWG.LmHAx.;_ylu=c2VjA3Nl
YXJjaARzbGsDYXNzaXN0;_ylc=X1MDMjExNDcyMzA0NgRfcgMyBGZyA21jYWZlZQRmcjIDc2EtZ3Atc2
VhcmNoBGdwcmlkA0VPaU5zTUtGUmtlazVDSmttZ2VPcEEEbl9yc2x0AzAEbl9zdWdnAzEwBG9yaWd
pbgNpbi52aWRlby5zZWFyY2gueWFob28uY29tBHBvcwMyBHBxc3RyA25wdCBmb3IgdmlkZW9zIHJl
Y29uZm9yYWdhYmxlIGNvbXB1dGluZwRwcXN0cmwDMzkEcXN0cmwDNDcEcXVlcnkDbnB0JTIwZm
9yJTIwdmlkZW9zJTIwcmVjb25mb3JhZ2FibGUlMjBjb21wdXRpbmclMjBzeXN0ZW1zBHRfc3RtcAMxN
jg2ODIzMzM2BHVzZV9jYXNlAw--?p=npt+for+videos+reconforagable+computing+systems&ei=UTF-
8&fr2=sa-gp-
search&fr=mcafee&type=E211IN1274G0#id=1&vid=133c016852187c2eea6cfbf3f0a28dc8&action=v
iew
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
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62
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Pattern Recognition & Machine Learning Semester III

Course Code 22LVS332 CIE Marks 50
Teaching Hours/Week (L:T:P: 3:0:0:0
SEE Marks 50
S)
Total Hours of Pedagogy 40 10
Total Marks
0
Credits 03 Exam Hours 3
Examination type (SEE) Theory

Course objectives:
1. To understand the model selection and different types of variables.
2. To study Supervised Learning Linear Regression Models.
3. To learn the various types of Supervised Learning Kernels.
4. To get familiar with Unsupervised Learning.
5. To learn the Probabilistic Graphical Models.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Chalk and Talk.
2. Power Presentation and Videos.
3. Flipped Classes.
4. Practice Sessions.

Module-1
Introduction: Probability Theory, Model Selection, The Curse of Dimensionality, Decision Theory, Information
Theory Distributions: Binary and Multinomial Variables, The Gaussian Distribution, The Exponential
Family, Nonparametric Methods. (Ch.: 1,2)
Module-2
Supervised Learning Linear Regression Models: Linear Basis Function Models, The Bias-Variance
Decomposition, Bayesian Linear Regression, Bayesian Model Comparison Classification & Linear
Discriminant Analysis: Discriminant Functions, Probabilistic Generative Models, Probabilistic
Discriminative Mode (Ch.:3,4).

Module-3
Supervised Learning Kernels: Dual Representations, Constructing Kernels, Radial Basis Function Network,
Gaussian Processes Support Vector Machines: Maximum Margin Classifiers, Relevance Vector Machines
Neural Networks: Feed-forward Network, Network Training, Error Back propagation (Ch:5,6,7).

Module-4
Unsupervised Learning: Mixture Models: K-means Clustering, Mixtures of Gaussians, Maximum
likelihood, EM for Gaussian mixtures, Alternative View of EM. Dimensionality Reduction: Principal
Component Analysis, Factor/Component Analysis, Probabilistic PCA, Kernel PCA, Nonlinear Latent Variable
Models (Ch.: 9,12).
Module-5
Probabilistic Graphical Models: Bayesian Networks, Conditional Independence, Markov Random Fields,
Inference in Graphical Models, Markov Model, Hidden Markov Models (Ch.:8,13)

Course outcome (Course Skill Set)

At the end of the course the student will be able to:

1. Identify areas where Pattern Recognition and Machine Learning can offer a solution.
2. Describe the strength and limitations of some techniques used in computational Machine Learning for
classification, regression and density estimation problems.
62
3. Describe and model data. 7
4. Solve problems in Regression and Classification.
5. Discuss main and modern concepts for model selection and parameter estimation in recognition,
decision making and statistical learning problems.
EES 20.06.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation:

 For the Assignment component of the CIE, there are 25 marks and for the Internal Assessment Test
component, there are 25 marks.
 The first test will be administered after 40-50% of the syllabus has been covered, and the second test will
be administered after 85-90% of the syllabus has been covered
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only one
assignment for the course shall be planned. The teacher should not conduct two assignments at the end of
the semester if two assignments are planned.
 For the course, CIE marks will be based on a scaled-down sum of two tests and other methods of
assessment.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours).
5. The question paper will have ten questions. Each question is set for 20 marks.
6. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module.
7. The students have to answer 5 full questions, selecting one full question from each module.
8. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Pattern Recognition and Machine Learning Christopher Bishop Springer 2006

Web links and Video Lectures (e-Resources):

 https://www.youtube.com/playlist?list=PLbRMhDVUMngcx-ATexXZH_-u1wsIGIiyS
 https://www.youtube.com/watch?v=s0ZKnU-2Sps

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

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62
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Long Term Reliability of VLSI Systems Semester III

Course Code 22LVS333 CIE Marks 50
Teaching Hours/Week (L:T:P: 3:0:0:0
SEE Marks 50
S)
Total Hours of Pedagogy 40 10
Total Marks
0
Credits 03 Exam Hours 3
Examination type (SEE) Theory

Course objectives:
 To Understand the Various Concepts Related To Electro migration Reliability.
 To study the Fast EM Stress Evolution Analysis.
 To study the EM Assessment for Power Grid Networks.
 To understand the Transistor Aging Effects and Reliability.
 To learn the Aging Effects in Sequential Elements.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Chalk and Talk.
2. Power Presentation and Videos.
3. Flipped Classes.
4. Practice Sessions

Module-1
Electro migration Reliability: Why Electromigration Reliability?,Why system-level EM Reliability
Management? Physics- based EM Modeling, Electromigration Fundamentals, Stress based EM Modeling and
stress diffusion equations, Modeling for transient EM effects and Initial stress conditions, post voiding
stress and void volume evolution, compact physics based EM model for a single wire, other relevant EM
models and analysis methods. (Text Book:1 – 1.1, 1.2, 2.1 up to 2.6, 2.9)
Module-2
Fast EM Stress Evolution Analysis: Introduction, The LTI ordinary differential equations for EM stress
evolution, The presented Krylov fast EM stress analysis, Numerical results and discussions (Text. Book:1 –
3.1 up to 3.4).

Module-3
EM Assessment for Power Grid Networks: New power grid reliability analysis method, cross-layout
temperature and thermal stress characterization, impact of across-layout temperature and thermal stress
on EM. (Text.Book:1 – 7.1, 7.2, 7.4, 7.5).

Module-4
Transistor Aging Effects and Reliability: Introduction, Transistor reliability in advanced technology
nodes, Transistor Aging, BTI- Bias Temperature Instability, HCI – Hot Carrier Injection, Coupling models for
BTI and HCI degradations, RTN – Random Telegraph Noise, TDDB – Time Dependent Dielectric Breakdown.
(Text Book: 1 – 13.1, 13.2)
Module-5
Aging Effects in Sequential Elements: Introduction, Background: flip flop timing analysis, process variation
model, voltage droop model, Robustness analysis, reliability-aware flip-flop design (Text Book: 1 – 16.1 up to
16.4).
63
0
EES 20.06.2023

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. At the end of the course the student will be able to:
2. Comprehend the recent research in the area of interconnect and device reliability. 2. Determine the
impact of device-level reliability on system performance, built upon physics-based models.
3. Understand the physics-based EM modeling.
4. Understand the underlying phenomena of BTI, HCI, TDDB leading to device-level reliability
degradation.
5. Relate to considerations at the circuit-level with both combinational and sequential elements.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation:

 For the Assignment component of the CIE, there are 25 marks and for the Internal Assessment Test
component, there are 25 marks.
 The first test will be administered after 40-50% of the syllabus has been covered, and the second test will
be administered after 85-90% of the syllabus has been covered
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only one
assignment for the course shall be planned. The teacher should not conduct two assignments at the end of
the semester if two assignments are planned.
 For the course, CIE marks will be based on a scaled-down sum of two tests and other methods of
assessment.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours).
9. The question paper will have ten questions. Each question is set for 20 marks.
10. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module.
11. The students have to answer 5 full questions, selecting one full question from each module.
12. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1.Long-Term Reliability of Nanometer VLSI Systems Sheldon X. D. Tan, Mehdi BaradaranTahoori,
Taeyoung Kim, SamanKiamehr, Zeyu Springer International Publishing 1 st Edition, 2019 ISBN: 978-3- 030-
26171-9

Reference Books:

2. Reliability Wearout Mechanisms in Advanced CMOS Technologies Alvin Wayne Strong, Rolf-Peter
Vollertsen, Timothy D. Sullivan, Ernest Y. Wu, Giuseppe La Rosa, Jordi Sune Wiley, Copyright © the
63
Institute of Electrical and Electronics Engineers, Inc. 2009 Print
1 ISBN:978047 1731726
3. Hot-carrier Reliability of MOS VLSI Circuits Yusuf Leblebici, S M Kang Springer Science & Business Media
1 st Edition, 1993
4. Fundamentals of ElectromigrationAware Integrated Circuit Design Matthias Thiele, Jens Lienig Springer
EES 20.06.2023

International Publishing 2018

Web links and Video Lectures (e-Resources):

 https://in.video.search.yahoo.com/search/video;_ylt=Awrx.wZyzopkCaUWKJXmHAx.?fr=mcafee&ei=
UTF-8&type=E211IN1274G0&fr2=p%3As%2Cv%3Av%2Cm%3Asp-qrw-corr-
top&norw=1&p=Long+Term+Reliability+of+VLSI+Systems+nptel+videos#id=6&vid=09c65429e632f
047d89e3ddddbaca53b&action=view
 https://in.video.search.yahoo.com/search/video;_ylt=Awrx.wZyzopkCaUWKJXmHAx.?fr=mcafee&ei=
UTF-8&type=E211IN1274G0&fr2=p%3As%2Cv%3Av%2Cm%3Asp-qrw-corr-
top&norw=1&p=Long+Term+Reliability+of+VLSI+Systems+nptel+videos#id=7&vid=853453dc0d1e
04a80f1416802419aa98&action=view

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

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63
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CMOS RF Circuit Design Semester III

Course Code 22LVS334 CIE Marks 50
Teaching Hours/Week (L:T:P: 3:0:0:0
SEE Marks 50
S)
Total Hours of Pedagogy 40 10
Total Marks
0
Credits 03 Exam Hours 3
Examination type (SEE) Theory

Course objectives:
 To Learn the RF Design, Wireless Technology and Basic Concepts.
 To understand the various Communication Concepts.
 To understand the o learn the Transceiver Architecture.
 To understand the Low Noise Amplifiers and Mixers.
 To study VCO and PLLs Oscillators.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Chalk and Talk.
2. Power Presentation and Videos.
3. Flipped Classes.
4. Practice Sessions.

Module-1
Introduction to RF Design, Wireless Technology and Basic Concepts: A wireless world, RF design is
challenging, The big picture. General considerations, Effects of Nonlinearity, Noise, Sensitivity and dynamic
range, Passive impedance transformation. Scattering parameters, Analysis of nonlinear dynamic systems,
conversion of gains and distortion.
Module-2
Communication Concepts: General concepts, analog modulation, digital modulation, spectral re-
growth, coherent and non-coherent detection, Mobile RF communications, Multiple access techniques,
Wireless standards, Appendix 1: Differential phase shift keying.

Module-3
Transceiver Architecture: General considerations, Receiver architecture, Transmitter architectures, Direct
conversion and two-step transmitters, RF testing for heterodyne, Homodyne, Image reject, Direct IF and
sub sampled receivers.

Module-4
Low Noise Amplifiers and Mixers: General considerations, Problem of input matching, LNA topologies:
common-source stage with inductive load, common-source stage with resistive feedback. Mixers-General
considerations, passive down conversion mixers, Various mixers- working and implementation.

Module-5
VCO and PLLs Oscillators: Basic topologies VCO and definition of phase noise, Noise power and trade off.
Resonator VCO designs, Quadrature and single sideband generators. Radio frequency Synthesizers- PLLS,
Various RF synthesizer architectures and frequency dividers, Power Amplifier design.

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Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Analyse the effect of nonlinearity and noise in RF and microwave design.
2. Exemplify the approaches taken in actual RF products.
3. Minimize the number of off-chip components required to design mixers, Low-Noise Amplifiers, VCO and
PLLs.
4. Explain various receivers and transmitter topologies with their merits and drawbacks.
5. Demonstrate how the system requirements define the parameters of the circuits and the impact on the
performance
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation:

 For the Assignment component of the CIE, there are 25 marks and for the Internal Assessment Test
component, there are 25 marks.
 The first test will be administered after 40-50% of the syllabus has been covered, and the second test will
be administered after 85-90% of the syllabus has been covered
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only one
assignment for the course shall be planned. The teacher should not conduct two assignments at the end of
the semester if two assignments are planned.
 For the course, CIE marks will be based on a scaled-down sum of two tests and other methods of
assessment.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours).
13. The question paper will have ten questions. Each question is set for 20 marks.
14. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module.
15. The students have to answer 5 full questions, selecting one full question from each module.
16. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
Text Books
1. RF Microelectronics B. Razavi PHI second edition.

Reference Books:

1. CMOS Circuit Design, layout and Simulation R. Jacob Baker, H.W. Li, D.E. Boyce PHI 1998.
2. Design of CMOS RF Integrated Circuits Thomas H. Lee Cambridge University press 1998 .
3. Mixed Analog and Digital Devices and Technology Y.P. Tsividis TMH 1996.

Web links and Video Lectures (e-Resources): 63

4
EES 20.06.2023

 https://www.youtube.com/watch?v=oL8SKNxEaHs&list=PLLy_2iUCG87Bdulp9brz9AcvW_TnFCUm
M
 https://www.youtube.com/watch?v=57uTCtSQV50&list=PLHO2NKv71TvsSqYwVvUCZwNkY-
jUyUHdS

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



63
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Machine Learning in VLSI CAD Semester III

Course Code 22LVS335 CIE Marks 50
Teaching Hours/Week (L:T:P: 3:0:0:0
SEE Marks 50
S)
Total Hours of Pedagogy 40 10
Total Marks
0
Credits 03 Exam Hours 3
Examination type (SEE) Theory

Course objectives:
 To understand the Preliminary Taxonomy for Machine Learning in VLSI CAD.
 To study the Process Models and Neural Network Compact Patterning Models.
 To learn the Machine Learning for Mask Synthesis and Machine Learning in Physical Verification.
 To understand the design of Machine Learning in Mask Synthesis and Physical Design.
 To understand the Machine Learning for Yield and Reliability

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Chalk and Talk.
2. Power Presentation and Videos.
3. Flipped Classes.
4. Practice Sessions

Module-1
A Preliminary Taxonomy for Machine Learning in VLSI CAD: Machine learning taxonomy, VLSI CAD
Abstraction levels (Text Book:1 – 1.1, 1.2)
Machine Learning for Compact Lithographic Process Models : Introduction, Lithographic Patterning
Process, Representation of Lithographic Patterning Process – Mask, Imaging, Resist & Etch Transfer
Function (Text Book:1 – 2.1, 2.2).
Module-2
Machine Learning of Compact Lithographic Process Models (Cont.,) :Compact process model
machine learning problem statement, CPM Task, CPM Training Experience, Performance metrics,
Supervised learning of a CPM (Text. Book:1 – 2.3)
Neural Network Compact Patterning Models : Neural Network Mask Transfer Function, Neural
Network Image Transfer Function, Neural Network Resist Transfer Function, Neural Network Etch Transfer
Function (Text. Book:1 – 2.4).

Module-3
Machine Learning for Mask Synthesis: Introduction, Machine Learning guided OPC, MLP Construction,
ML-EPC, EPC Algorithm (TextBook:1 – 3.1, 3.2, 3.2.2.2, 3.3.2, 3.3.2.4). Machine Learning in Physical
Verification: Introduction, Machine Learning in Physical Verification – layout feature extraction & encoding,
models for hotspot detection. (Text.Book:1 – 4.1, 4.2)

Module-4
Machine Learning in Mask Synthesis and Physical Design: Machine Learning inMask Synthesis – mask
synthesis flow, Machine Learning for sub-resolution assist features, Machine Learning for optical proximity
correction. Machine Learning inPhysical Design - for datapath placement, routability driven placement, clock
optimization, lithography friendly routing (Text Book: 1 – 4.3, 4.4).
Machine Learning for Manufacturing: Gaussian Process-Based Wafer-Level Correlation Modeling and
Its Applications (Text Book: 1 – 5.1).
Module-5 63
6
Machine Learning for Yield and Reliability: High-volume manufacturing yield estimation – Histogram with
random sampling, Histogram with GPST-PS, Kernel density estimation. (Text Book: 1 – 5.2.11).
Machine learning based aging analysis (Text Book: 1 – 9.1).
Learning from limited data in VLSI CAD, Iterative feature search (Text Book: 1 – 13.1, 13.2). Comparative study of
EES 20.06.2023

Assertion mining algorithms in GoldMine (Text Book: 1 – 20.1)

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. 1. Use machine learning technologies in VLSI CAD to further automate the design, verification and
implementation of the most advanced chips.
2. 2. Relate to the usage of machine learning algorithms for Compact Lithographic Process Models
3. . 3. Apply Machine Learning in Mask Synthesis and Physical Verification to bear on CAD problems such as
hotspot detection, efficient test generation, post-silicon measurement minimization.
4. 4. Predict the Yield and Reliability of VLSI chips using machine learning methods. 5. Comprehend the
appropriate application of the various supervised, unsupervised and statistical learning in the various
layers of chip design hierarchy.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation:

 For the Assignment component of the CIE, there are 25 marks and for the Internal Assessment Test
component, there are 25 marks.
 The first test will be administered after 40-50% of the syllabus has been covered, and the second test will
be administered after 85-90% of the syllabus has been covered
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only one
assignment for the course shall be planned. The teacher should not conduct two assignments at the end of
the semester if two assignments are planned.
 For the course, CIE marks will be based on a scaled-down sum of two tests and other methods of
assessment.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours).
2. The question paper will have ten questions. Each question is set for 20 marks.
3. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Machine Learning in VLSI Computer Aided Design Editors: Ibrahim (Abe)M Elfadel, Duane SBoning,
Xin Li Springer International Publishing 2019

Reference Books

1. Machine Learning Tom M Mitchell McGraw-Hill 1997 63

2. Machine Learning Anuradha Srinivasaraghavan, Vincy Joseph
7 Wiley 2019

Web links and Video Lectures (e-Resources):

EES 20.06.2023

 https://in.video.search.yahoo.com/search/video;_ylt=Awrx.wZyzopkCaUWl5TmHAx.;_ylu=c2VjA3Nl
YXJjaAR2dGlkAw;_ylc=X1MDMjExNDcyMzA0NgRfcgMyBGZyA21jYWZlZQRmcjIDcDpzLHY6dixtOnNiL
HJnbjp0b3AEZ3ByaWQDTVpkQjZKYWJTcVdMemVFd3A4RG5IQQRuX3JzbHQDMARuX3N1Z2cDMARv
cmlnaW4DaW4udmlkZW8uc2VhcmNoLnlhaG9vLmNvbQRwb3MDMARwcXN0cgMEcHFzdHJsAzAEcX
N0cmwDNDAEcXVlcnkDTWFjaGluZSUyMExlYXJuaW5nJTIwaW4lMjBWTFNJJTIwQ0FEJTIwbnB0bCU
yMHZpZGVvcwR0X3N0bXADMTY4NjgxODY3Mw?p=Machine+Learning+in+VLSI+CAD+nptl+videos&
ei=UTF8&fr2=p%3As%2Cv%3Av%2Cm%3Asb%2Crgn%3Atop&fr=mcafee&type=E211IN1274G0#id
=7&vid=cb7ebd6c1d4ee028490224221b16e987&action=view
 https://in.video.search.yahoo.com/search/video;_ylt=Awrx.wZyzopkCaUWl5TmHAx.;_ylu=c2VjA3Nl
YXJjaAR2dGlkAw;_ylc=X1MDMjExNDcyMzA0NgRfcgMyBGZyA21jYWZlZQRmcjIDcDpzLHY6dixtOnNiL
HJnbjp0b3AEZ3ByaWQDTVpkQjZKYWJTcVdMemVFd3A4RG5IQQRuX3JzbHQDMARuX3N1Z2cDMARv
cmlnaW4DaW4udmlkZW8uc2VhcmNoLnlhaG9vLmNvbQRwb3MDMARwcXN0cgMEcHFzdHJsAzAEcX
N0cmwDNDAEcXVlcnkDTWFjaGluZSUyMExlYXJuaW5nJTIwaW4lMjBWTFNJJTIwQ0FEJTIwbnB0bCU
yMHZpZGVvcwR0X3N0bXADMTY4NjgxODY3Mw?p=Machine+Learning+in+VLSI+CAD+nptl+videos&
ei=UTF8&fr2=p%3As%2Cv%3Av%2Cm%3Asb%2Crgn%3Atop&fr=mcafee&type=E211IN1274G0#id
=12&vid=1422bb4b7e46947b5b3595efd90e117f&action=view

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



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M.TECH VLSIDESIGN & EMBEDDEDSYSTEMS(EVE)

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)S
EMESTER-III
PROJECTWORK PHASE–1
Course Code 20LVS34 CIEMarks 100
Numberof contact Hours/Week(L:T:P) 0:0:06 SEEMarks --
Credits 3 ExamHours --
Courseobjectives:
 Supportindependentlearning.
 Guidetoselectandutilizeadequateinformationfromvaried resourcesmaintainingethics.
 Guidetoorganizethe
workintheappropriatemannerandpresentinformation(acknowledgingthesources)clearly.
 Developinteractive,communication,organisation,timemanagement,andpresentationskills.
 Impartflexibilityandadaptability.
 Inspireindependentandteamworking.
 Expandintellectualcapacity,credibility,judgement,intuition.
 Adheretopunctuality,settingand meetingdeadlines.
 Instilresponsibilitiestooneselfandothers.
 Train students to present the topic of project work in a seminar without any fear, face
audienceconfidently,enhancecommunicationskill,involveingroup
discussiontopresentandexchangeideas.
Project Phase-1 Students in consultation with the guide/s shall carry out literature survey/ visit
industries tofinalize the topic of the Project. Subsequently, the students shall collect the material required
for the selectedproject,prepare synopsisandnarratethemethodologytocarryoutthe projectwork.
Seminar:Eachstudent,undertheguidanceofaFaculty,isrequiredto
 Presenttheseminarontheselectedprojectorallyand/orthroughpowerpointslides.
 Answerthequeriesandinvolveindebate/discussion.
 Submittwocopiesofthetypedreportwithalistofreferences.
Theparticipantsshalltakepartindiscussiontofoster friendlyandstimulatingenvironment
inwhichthestudentsaremotivatedtoreachhighstandardsandbecomeself-confident.
Revised L3–Applying,L4–Analysing,L5–Evaluating, L6–Creating.
Bloom’sTaxono
myLevel
Courseoutcomes:
Attheend ofthecoursethestudent willbeableto:
 Demonstrateasoundtechnicalknowledgeoftheirselectedprojecttopic.
 Undertakeproblemidentification,formulationandsolution.
 Designengineeringsolutionstocomplexproblemsutilisingasystemsapproach.
 Communicatewithengineers andthecommunityatlargeinwrittenanoralforms.
 Demonstratetheknowledge,skillsandattitudesofaprofessionalengineer.
ContinuousInternalEvaluation
CIE marks for the project report (50 marks), seminar (30 marks) and question and answer (20 marks) shall
beawarded(basedonthequalityofreportand presentationskill,participationinthequestionand
answersessionbythe student) by the committee constituted for the purpose by the Head of the Department.
The committee shallconsistofthreefacultyfromthe departmentwiththe seniormostactingastheChairperson.

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EES 20.06.2023

M.TECH VLSIDESIGN & EMBEDDEDSYSTEMS(EVE)

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)S
EMESTER-III
Societal Project
Course Code 22LVS35 CIEMarks 100
NumberofcontactHours/Week(L:T:P) 0:0:6 SEEMarks --
Credits 03 ExamHours/Batch --
Courseobjectives:
 Tosupportindependentlearningandinnovativeattitude.
 Toguidetoselectandutilizeadequateinformationfromvariedresourcesupholdingethics.
 Toguidetoorganizethe workintheappropriatemannerand
presentinformation(acknowledgingthesources)clearly.
 Todevelopinteractive,communication,organization,timemanagement,andpresentationskills.
 Toimpart flexibilityandadaptability.
 Toinspireindependenceandteamworking.
 Toexpandintellectualcapacity,credibility,judgment,intuition.
 Toadheretopunctuality,settingandmeeting deadlines.
 Toinstillresponsibilitiesto oneselfand others.
 To train students to present the topic of project work in a seminar without any fear, face the
audienceconfidently,enhancecommunicationskills,involveingroupdiscussiontopresentandexcha
ngeideas.
Mini-Project:Eachstudentshallinvolveincarryingouttheprojectworkjointlyinconstantconsultationwith
internalguide,co-guide,andexternal guideandpreparetheprojectreportasperthenormsavoidingplagiarism.
Courseoutcomes:
Attheend ofthecoursethestudent willbeableto:
 Presentthemini-projectandbeabletodefendit.
 Makelinksacrossdifferentareasofknowledgeandgenerate,developandevaluateideasandi
nformation soastoapplythese skillstothe projecttask.
 Habituatedtocriticalthinkinganduseproblem-solvingskills.
 Communicateeffectivelyandtopresentideasclearlyandcoherentlyinbothwrittenand oralforms.
 Workinateamto achieveacommongoal.
 Learnontheirown,reflectontheirlearningandtakeappropriateactionstoimproveit.

CIEprocedureforMini - Project:
The CIE marks awarded for Mini - Project, shall be based on the evaluation of Mini - Project Report,
ProjectPresentation skill and Question and Answer session in the ratio 50:25:25.The marks awarded for
Mini - Projectreportshall be the samefor allthe batchmates.

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0
EES 20.06.2023
20/02/2023/V4

M.TECH VLSIDESIGN & EMBEDDEDSYSTEMS(EVE)

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)S
EMESTER-III
INTERNSHIP
Course Code 22EVEI36 CIEMarks 40
NumberofcontactHours/Week SEEMarks 60
Credits ExamHours 03
Courseobjectives:
Internship/Professional practice provide students the opportunity of hands-on experience that include
personaltraining, time and stress management, interactive skills, presentations, budgeting, marketing,
liability and riskmanagement, paperwork, equipment ordering, maintenance, responding to
emergencies etc. The objectives arefurther,
 Toputtheoryintopractice.
 Toexpandthinkingandbroadenthe knowledgeandskillsacquiredthroughcourse workinthefield.
 Torelateto,interact with,andlearnfromcurrentprofessionalsinthefield.
 Togainagreaterunderstandingofthedutiesandresponsibilitiesofaprofessional.
 Tounderstandandadheretoprofessionalstandardsinthefield.
 Togaininsighttoprofessionalcommunicationincludingmeetings,memos,reading,writing,public
speaking,research, clientinteraction, inputofideas, andconfidentiality.
 Toidentifypersonalstrengthsand weaknesses.
 Todeveloptheinitiativeandmotivationtobeaself-starterandworkindependently.

Internship/Professional practice: Students under the guidance of internal guide/s and external guide
shall takepartinalltheactivitiesregularlytoacquireas muchknowledgeaspossible
withoutcausinganyinconvenienceattheplace ofinternship.
Seminar: Eachstudent,isrequiredto
 Presenttheseminarontheinternshiporallyand/orthroughpowerpointslides.
 Answerthequeriesandinvolveindebate/discussion.
 Submitthereportdulycertified bytheexternalguide.
 Theparticipantsshalltakepartindiscussiontofosterfriendlyandstimulatingenvironmentinwhichthe
studentsaremotivated toreachhighstandardsand becomeself-confident.
Courseoutcomes:
Attheend ofthecoursethestudent willbeableto:
 Gainpracticalexperiencewithinindustryin whichtheinternshipisdone.
 Acquireknowledgeoftheindustryinwhichtheinternshipisdone.
 Applyknowledgeandskillslearnedtoclassroomwork.
 Developagreaterunderstandingaboutcareeroptionswhile moreclearlydefiningpersonal careergoals.
 Experiencetheactivitiesandfunctionsofprofessionals.
 Developandrefineoralandwrittencommunicationskills.
 Identifyareasforfutureknowledgeandskilldevelopment.
 Expandintellectualcapacity,credibility,judgment,intuition.
 Acquiretheknowledgeofadministration,marketing,financeandeconomics.

ContinuousInternalEvaluation
CIE marks for the Internship/Professional practice report (20 marks), seminar (10 marks) and
question
andanswersession(10marks)shallbeawarded(basedonthequalityofreportandpresentationskill,participat
ionin the question and answer session by thestudent) by the committee constituted for thepurpose by the
Head ofthe Department. The committee shall consist of three faculty from the department with the senior
most acting astheChairperson.
SemesterEndExamination
SEE marks for the internship report (30 marks), seminar (20 marks) and question and answer 105
session (10marks) shall be awarded (based on the quality of report and presentation skill, participation in
the question andanswer session) bythe examinersappointedbythe University
EES 20.06.2023
20/02/2023/V4

M.TECH VLSIDESIGN & EMBEDDEDSYSTEMS(EVE)

ChoiceBasedCreditSystem(CBCS)andOutcomeBasedEducation(OBE)S
EMESTER-IV
PROJECTWORKPHASE-2
Course Code 22LVS41 CIEMarks 100
NumberofcontactHours/Week(L:T:P) 0:0:08 SEEMarks 100
Credits 18 ExamHours 03
Courseobjectives:
 Tosupportindependentlearning.
 Toguidetoselectandutilizeadequateinformationfromvariedresourcesmaintainingethics.
 Toguidetoorganizethe workintheappropriatemannerand
presentinformation(acknowledgingthesources)clearly.
 Todevelopinteractive,communication,organization,timemanagement,andpresentationskills.
 Toimpart flexibilityandadaptability.
 Toinspireindependentandteamworking.
 Toexpandintellectualcapacity,credibility,judgment,intuition.
 Toadheretopunctuality,settingandmeetingdeadlines.
 Toinstilresponsibilitiestooneselfandothers.
 To train students to present the topic of project work in a seminar without any fear, face
audienceconfidently,enhancecommunicationskill,involveingroup
discussiontopresentandexchangeideas.
ProjectWorkPhase- II: Eachstudentoftheprojectbatchshallinvolveincarryingouttheprojectworkjointly
inconstantconsultationwithinternal guide,co-guide,andexternal
guideandpreparetheprojectreportasperthenormsavoidingplagiarism.
Courseoutcomes:
Attheend ofthecoursethestudent willbeableto:
 Presenttheprojectandbeableto defendit.
 Makelinksacrossdifferentareasofknowledgeandtogenerate,developandevaluateideasandi
nformation soastoapplythese skillstothe projecttask.
 Habituatedtocriticalthinkinganduseproblemsolvingskills
 Communicateeffectivelyandtopresentideasclearlyandcoherentlyinboththewrittenandoralforms.
 Workinateamto achievecommongoal.
 Learnontheir own,reflecton theirlearningand takeappropriateactionstoimproveit.

ContinuousInternalEvaluation:
Project Report: 20 marks. The basis for awarding the marks shall be the involvement of the student in
theprojectandinthepreparationofprojectreport.Tobeawarded
bytheinternalguideinconsultationwithexternalguideifany.
ProjectPresentation:10marks.
TheProjectPresentationmarksoftheProjectWorkPhase-IIshallbeawardedbythecommitteeconstitutedforthe
purpose by the Head of the Department. The committee shall consist of three faculty from the
departmentwiththe seniormostactingasthe Chairperson.
QuestionandAnswer:10marks.
Thestudentshallbeevaluatedbased ontheabilityintheQuestionandAnswer sessionfor10marks.
SemesterEndExamination
SEEmarks for theproject report (30 marks),seminar (20 marks) and question and answersession
(10marks)shall be awarded (based on the quality of report and presentation skill, participation in the
question and answersession)bythe examinersappointedbythe University.

105