Combinationg Logic Circuit, tion : 6.1 intro ee we have learnt about Boolean algebra, logic gates, ros In previ ecific function that car MCh of 5 form. To perform any spt u at can be ox sums ea poser a combination of these logic gates is used, The 2 ea combinational logic circuits. Thus, a combinational circuit consists Of i Tate logic gates and ‘output variables. Logic Circuits can be classifieg as: (a) Combinational Circuit (b) Sequential Circuit In this chapter, we will consider, the combinational circuit. ae 6.2 Combinational Circuit : In combinational circuit, at any instant output entirely depends on the inputs Present at that instant as shown in figure 6.1 —| —— Combinational Ninputs ——>| pia Ty M Outputs | —- FIGURE 6.1 f In this circuit, each output is expressed in terms of N inputs. Therefore, combinational circuits are interconnected circuits of gates according 0 certain rule to produce an output depending on its input value. The output o@ combinational circuit is related to its input by a combinational circuit is related toi input by a combinational function which is independent of time. i 6.2.1 Characteristics of Combinational Logic Characteristics of Combinational Logic are : 1. It isa circuit whose outputs at any time depends only on the inputs a it at that instant of time. pled! pelsy 1 design, due to absence of Memory, 2 3 astern speed. 4 pequires more hardware for its realization, 5. expensive in cost. i procedure for Combinational Logic yh 4 esi combinational logic circuits, you need to Proceed as follows « state the problem in words. y Find out the number of input and output variables, Letter symbols are assigned (or designated) to the input and out Make truth table using the problem statement. Make a Boolean expression for each output. implify the Boolean expression in order to minim on K-map or by laws of Boolean algebra. Ze he numberof vals After simplification, we obtained the simplified Boolean expression for each output. Finally, draw the logic-circuit diagram corresponding to the simplified Boolean expression. [put variables, Pr enrs 3 Half Adder Acombinational circuit that performs the addition of two bits is called a half adder. Ahalf adder is a circuit that has two inputs, A and B Carry. The blolck diagram and Truth Table for a half and table 6.1 respectively. and two outputs, Sum and adder as shown in figure 6.2 | FIGURE 6.2 TABLE 6.1 } Outputs / Carry 0 0 0 1 143)The Boolean expression for Sum and Carry outputs are given by ~ a B 1 Sum =AB+AB=A®B Cary=AB/. Here Sum is the same as the Boolean expression for XOR gate ang c same as the Boolean expression for AND gate. Therefore, there is an iby simplyfy the boolean expression for Sum and Carry. © Need The logic diagram (or circuit) for the half adder is shown in figure 6.3 A A@B gun 7 : FIGURE 6.3 Ahalf adder can be represented in several ways by using combinations of various log gates. The logic circuit for half adder using only NAND gates is shown in figure 64 pet AP p— Poa A+ B B [FIGURE 5.4 (Cc) HALF ADDERy full Adder 4 to perform multibit addition, a half adder has no provision to add a carry coming from the lower order bits. For this we need a full adder. Afull adderisa combinational circuit that performs the sum of three bits (two significant bits and a previous carry). ~ Afull adder is a circuit that has three inputs A, B, C and two outputs, Sum and Carry as shown in figure 6.6 In orde A Sum Full Cc Adder Carry FIGURE 6,6 (BLOCK DIAGRAM) Two of the input variables, denoted by A and B, represent the two significant bits to be added. The third input, C represents the carry from the previous lower significant position. Table of the full-adder is shown in table 6.2 Inputs [Es Outputs A B | c Sum Carry o | o|] o 0 0 o | o}] 14 1 0 o}ifo 1 0 oO ft |at 0 1 1 | o] 0 1 0 vo 4 0 1 1 | 1]00 0 1 1/a]4 1 1 TABLE 6.2 Froy : ™ the table 6.2, the boolean expression for Sum and Carry is obtained as um =A, tee e =ABC+ABC+ABC+ABC Tees +ABC+ABC+ABC Maps for the outputs Sum and Carry are given in figure 6.6 and 67. [145]FIGURE 6.6 (K-MAP FOR SUM) FIGURE 6.7 (K-MAP FOR CARRY) After simplification by K-maps, the boolean expression for Sum and Carry are, sum =ABC+ABC+ABC+ABC Carry =AB+BC+CA Logic diagrams for Sum and Carry are shown in figure 68 sum onmroDrOar 7 Qo> FIGURE 6.8 (LOGIC DIAGRAM OF FULL ADDER) fllogic diagram for Full Adder using only NAND gates is given in figure 6.9 he A B || Cc A B c . Sum A B c A B Cc A B c Carry c ee fon eet ict aN by a» © expressed as a combination of two half adders as shown in Pe ; (a7)6.5 A@B sum Half A Half (A®B)@C B adder 1 AB adder 2 (A @B).C +AB Carry FIGURE 6.10 The output Sum can be expressed as Sum = (A@B).8C (AB+AB)®C " (AB+AB).C +(AB+AB).C (AB+AB).C+ABC+ABC. = ABC+ABC+ABC+ABC The output Carry can be expressed as Cary = — (A@B).C+AB = (AB+AB)C+AB = ABC+ABC+A.B = ABC+ABC+AB-1 = ABC+ABC+AB(C+0)(..c+6 =1) = ABC+ABC+ABC+ABG Parallel Binary Adder j : isan In the Previous section we have discussed full adder capable of adding two ee 0 one previous carry. When two binary numbers of n bits each are to be 4 numbers of full adders are required. 10, Binary Adder Is the combinational circuit that is used to find the sum ° binary numbers of any length. { 48)=A,A,A, and B = B, BB, are to -bit binary numbers say A=A,A, A,, z , B, B, a samples if we al eae are required as shown in figure 6.11 porn ag, then ded pe! c 4] 1 1 > Carry o AA 14004. 1° 3 4st number 7 a a 1 0 1 > 2ndnumber , BB ass 8% 1 1:00 > Sum 3 _ A BS A,B, A, B, Full adder MM Full adder " Full adder 1 FIGURE 6.11 (BINARY ADDER OF 3-BT) E a a adds the respective digits in a column of the numbers A and B and it TeDresente mee successively connected to the next full adder. Since first adder Cx0, ns the least signficant bits, it has no input carry and therefore its input carry 46 ’ ‘att Subtractor usta Sune are half and full adders, there are half and full subtractors. Ha Ss their aiezetor 'S.a combinational circuit that subtract two bits and produce ference, x : ifference) 8 oot 'S@ circuit that has two inputs X and Y and two outputs Cited S812 ang phe block diagram and Truth Table of half subt. Table 6.3 respectively (1491D } : Half | Subtractor B i 1 FIGURE 6.12 (BLOCK DIAGRAM) > Inputs. Outputs x Y D B 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 TABLE 6.3 The boolean expression for two outputs are given by D=XY+XY=x@yY B=XY The logic diagram for the half subtractor is shown in figure 6.13

—D, | L5—p; | | FIGURE 6.16 (BLOCK DIAGRAM) iey ; rable for 2.x 4 decoder is shown in table 6.6 fe Inputs A 0 0 1 1 TABLE 6.6 From the Truth Table, the boolean expressit lachae pression for the outputs D,, D,, D, and D, can D,=A.B D, =A.B D3 =A.B The logic di gic diagram from 2 x 4 decoder is shown in figure 6.17 FIGURE 6.17 [153]is ji i i id more than on - Itis sometimes convenient to include one ant 1 © enable decoder to control the circuit operation. All output will be equal to Oifthe is 0. When the enable input is 1, then circuit operates ; diagram of a 2x4 decoder with enable input is shown in fi aS a decog, ek igure 6.18. That A—> a 2-4 A, decoder rs A 3s— > | po 4, | =— | (enable) E | FIGURE 6.18 6.8.2 3 x 8 decoder Similary, for n = 3, the decorder will have 2° = 8 outputs. For n = 4, the decoders have maximum 2¢ = 16 outputs. Block diagram of 3x 8 decoder is shown in figure 6.19 FIGURE 6.19 Fi The Truth Table for 3 x 8 decoder is shown in Table 6.6 I"a OUTPUTS se c | D [D2 D, D, | 0, «| 0, sto yt f° 0 0 Ogi=a0; |= ocho ‘i i ol4 0 0 0 0 Oo lo _ o | o 1 0 0} olf olo t + | 4 0, 21.0 0 1 ol of} ojo | o}|o|ol|fo jo 0 1] 0 | o]}o i 0 1 o |o 0 0 0 1 o |o | il 0 0 0 0 oO oO 0 il 0 1 id 0 O Oo 0 0 0 0 1 \ TABLE 6.6 ' The logic diagram for 3 x 8 decoder is shown in fig 6.20 | {| | | B: 1 =AeBeC | ! } D,=AeBeC D, =AeBeC | D, =AeBeG | _ Dy=AeBeC D,=AeBeC D, =AeBeC Se ee FIGURE 6.20 155]i ders 6.8.3 4 x 16 decoder with 3 x'8 deco 46 decoder with 3 x 8 ae For this, we need two 3, 4 We can pote input as shown in figure 6. decoder at si FIGURE 6.21 decode! When D=0, the top decoder is enabled and the other is disabled. The eat ottth Output are alll 0's and the top decoder provides Outputs from D, to D, (0 When D=1, the enable Conditi jecoder™ ions are Teversed, the outputs of the ton 4114): all 0's and the bottom decoder Provides outputs from D, to D,, (1000 6.8.4 5 x 32 decoder with 3x8 decoders able in To design 5 x 32 decoder, we Need four 3 x g decoders and two @! | Figure 6.22 shows the 5 x 32 decoder with 3 x 8 decoders. (f3-8 4, 10 A, decoder #—>—__ 3:8 A, 1A, decoder -—>——— [ror 8 Ay, TO decoder sy 4a )) or JT -——_—— Poe Lae | le || ey pt i) ---— [oer pues Saree FIGURE 6.22 7 [157]A, B, C are the three inputs of 3x8 decoder and Dand E are two ¢ When E = 0 and D = 0 then the top decoder provide outputs from D, top, 00111) and other are disabled. When E = 0 and D =1, then the (doen Provide outputs from D, to D,, (01000 to 01111) an E =1 and D =0 then only decoder number III Provide to 10111). Lastly, when E = 1 and D = 1 then the dec. from D,, to D,, (11000 to 11111). id others are qj outputs from, Oo, oder number ly Provi Pat 6.8.5 BCD to decimal decoders BCD to decimal decode: fs consist of 4 input lines and 10 Output lines as . Truth Table 6.7 a INPUTS OUTPUTS By |e ete: pores oe ele 5 | 96 oO oO oO ot clot 9}0}0}oTo]o]o | TABLE 6.7 iei 1S SNOWN IN NQUIe O.c5 F000 to decimal decoders wu n gag eee 5 = ; 1) = AeBeCeD " 0 = AeBeCeD [ 159)6.9 Encoders Anencoder is a combinational logic circult that performs an Peration y, to that of a decoder. Very Therefore, an encoder will have 2" or less input lines and n Output lines, For example, the octal to binary encoders consist of 8 i the eight digits, and three outputs lines that generate number. The truth table for octal to binary encodes is sh input lines, ong for e; the corresponding 14 own in Table ea” bi INPUTS OUTPUTS 2 A ee D, [A] BTS ne eB ee oo Popes ce ee eer ott ojo [i Toto fo fetes Tho Es i )o 0 0 0 ofaly : 7 2 0 [ea 0 0 0 1 0 fo ey Ooi om |Gola| GEeleolao jad 0} eee Pope pe pe te o |°fo fo [eo 7 ey eae TABLE 6.8 Logic diagram of octal to binary encoder is shown in figure 6.24 A=D, +D,+D.+ D D, Dy A 6 B=D,+D,+0e*" ‘S Ds 0: =D, #05495" D,it i der is constructed with OR gat : 24, it is clear that enco gates whose omit fg termined from the truth table 6.8. inp! as column of output C from truth table 6.8, then we find that Output bit C is t! we re octal digits D,, Ds, Dg and D, . Therefore {or C=D,+D,+D,+D, =D,+D, +D, +D. similarly A=D, +D, +Dg+D, B=D,+D,+D,+D, Note that D, is not connected to any OR gate, because the binary output must be all (sin this case and that is not possible. ; ‘The encoder shown in figure 6.24 assumes that only one input line can be equal to tatany time. Otherwise, 8 inputs can have 28= 266 combinations and the Circuit wilhave no meaning. Only 8 of these combinations as shown in table 6.8 have any meaning and the remaining input combinations are don't care conditions. 41 Decimal to BCD Encoders The decimal to BCD encoders consist of 10 input lines and 4 output lines as shown inttuth table 6.9 INPUTS OUTPUTS 2 [p, D,|D,)D,|D,|D,)D,|A |B }|c|D [o | 0 ololo|lofo 0 ofolo]o}1 0 rofolol+lo] 0 o| IE 1 0 ofoli|o lo 9 | |0 fo [o|1 - : ojoj1 o}o}o|t lo | ololo ofofo[1|tI* [o fo bolo 0 ava Oa le o fete o |ololo 0 [0 1 [1 fopot 3 TABLE 6.9 [161]i tl From the truth table, the boolean expression for the outputs ABo andy.) written as 5 = D,+D, i = D,+0,+D,+D, D, +D, +D, + D, = D,+D,+D,+D,+D, ooo0 > " Logic diagram of decimal to BCD encoder is shown in figure 6.26 rr Dy D, D, Ds Dy Ds Dy Dy Dg Dy e B=D, +D, +D,+0; =D, +D,+Di* “FIGURE 6.26 ("ee * er ywaltiplex combinational circuit that accept input from 2" lines and a rears a single output line. the 0! articular input line is controlled by a set of selection lines. oseation ae 2 input lines and n selection lines whose bit combination there are cereal. rich input is selected. ine, which inpt ae a of 4 to 1 line multiplexer is shown in figure 6.26 Bloc |, ——> |, —— 4:1 y ——» Mux | —4| Ss |S, FIGURE 6.26 we fer sy ls, ate the 4 inputs, Y is the one output and S,. S, are the two lines, mectonal le ot 4:1 uliploxer is given in table 6.10. The function table lists Putto-output Path for each possible bit combination of the selection lines. From TABLE 6.10 le 3.8 0, the Output Y can be expressed as 0S = 4 o+1.S,.8, 41,88, +1,8,.S, [163] bhic diagram of 4 : 1 multiplexer is shown in figure 6.27 The logic : a ee ee sb FIGURE 6.27 Similarly 8 : 1 and 16: 1 multiplexers can be designed. Block diagram of t shown in Figure 6.28. 1 in L \ Is 8:1 i Mux Y 1, SS Ss FIGURE 6.28 One does not Tequire to simplify logic expression. The IC Package cost is less, Logic design is simple Changes in. design can be easily done.) jtiplexer UX) is the OPP ie i asing! hows & block diagram of is oy "4 demultiplexer geo ‘osite of multiplexer inits operation. A demultiplexer le input and distributes it over several outputs. 4:4 demultiplexer. Table 6.11 shows the truth D, | 1:4 -?—D, | : DMUX [>—D, | t»—D, i FIGURE 6.29 Select lines Outputs lines s, | s, | D,]D,|p,|D, 0 0 1)/0];/0/]0 0 i o};1}/0]0 1 0 oj;o;1]o pec eee eee eae | ott TABLE 6.11 The it tyre lines are used to select an output on which the input data is present. The Multiplexer is shown in figure 6.30. FIGURE 6.30 [1651Note that the decoder can functions as a comics if the enable line ig) a data input line and input lines are taken as the select fines, Because de Lae, demultiplexer operations are obtains from the Same Circuit. So a decoder a enable input is referred to as a decoder / demultiplexer. Wit 6.12 Comparators A comparator is a combinational circuit that Performs the co, 4 e MParison, of numbers and determines, which one number is greater than, equal 10, ore than the other number. Consider the two numbers A and B, each consisting of 1 bit. Then there are the Possible outputs. 1. F,=1ifA=Bie. either both A and B are 0 or 1 2 F,=1ifA>Bie.A=1andB=0 3. F,=1ifA| Comparators F, (A>B) o.. F, (AcB) FIGURE 6.31 Table 6.12 shows the truth table of the comparator. Outputs TABLE 6.12 ‘ . r From table 6.12, we can write the boolean expression as (g<64AB eh? aeht eB m of 1-bit comparator is shown in figure 6.32 jc diagrat oak A cept B yo FIGURE 6.32 B7-Segment Display (BCD. The 7-segmer Mostly digital gs. si 'M Such as computers, numbers whicti a: -to-7 Segment Decoder) #8 ‘egment codes. The seven segments &-gare shown in figure 6.33 : : Faure 8 FIGURE 6.33 ich must be illuminated for each of the numerals. Wie JUCe 74 Shows the Segment whi J ah tala [167]is display device, the data which is in the BCD format has to q ani ror this nasee: a BCD-to-7 segment decoder is required, ra circuit has four input lines for receiving the BCD and seven Output lines tod ns segment display. A block diagram of BCD-to-7 segment decoder is shoy inf 6.36. Finally a 7-segment LED (light-emitting diode) display system ig shyt figure 6.36. Nn & The Truth table of BCA-to-7 segment decoder is shown in Table 6.13 a b rok c 2 B d~ | 7-Segment olel S Output ale2 f g 3 . FIGURE 6.36 FIGURE 6.36 TABLE 6.1." Inputs. Decimal Seven Segments AB CD Equivalents ef 9 0 0 0 0 + 0 Tv O00 0 1 io 0 0 O10 4 6 2 10 | e008 ay 3 O08 ot 4 ou) a. . 5 o1 0-1 1 °«0 6 1 i ot Oni 4 4 7 0 | 10 0 8 i ie <0 1 9 :y ing 4 vari map. In ession of all outputs (a to g) using 4 variable K-map implified expr the sim| it are assumed as enti 1s (from 0 to 9) from the eee : yon sotist 10 er for output ‘a’ is shown in fig (100 re entries not C2! FIGURE 6.37 (K-MAP FOR ‘a’ ) Sinpliied expression of a is a=A+CD+BD+BD Smilaty the simplified expression of other output b to g can be obtained as =CD+D 4B PASS 05 +BC Fray Make y ¢ 0 . de Converter de Mom one sate is a combin; re f kay . Truth table o| way tome Consider the code Converter of 8421 to cyclic code. le code ig Shown in table 6.14 (169) the logic diagram yourself. mation ational circuit used to convert the Infor ‘orm to another,TABLE 6.14 Inputs (8421) Outputs (Cyctigy SS | Digit ae) x v zy 0 orF 0 0-40 0 0 0 1 CLL ’ 0 oy 2 0 eae 0 o 1 14 3 0 0 1 1 0 0 1 0 4 0 4 0 oO Oo 1 1 0 5 o 1 0 1 1 1 1 0 6 0 1 1 0 1 0 Al 0 7 Oe et dl 1 0 1 1 8 1 0 0 0 1 0 o 4 9 1 o o 1 1 0 0 0 Now, our aim is to find the simplifed expression of all outputs i.e, XYZ,W. Consite he K-MAP of X as shown in figure 6.36 FIGURE 6.36 (K-MAP OF xX) Note that we made enteries from 0 t he simplified expre care" wet "do not care’ 0 9 and considered rest as "do M' ression of X as X=A+BD4BC essen! similarly make the K-map for Y, Z and W and get the simplified exp ind W as: Y=BCCircuit for X, ¥, 4 and W as shown in figure 6. make the ig 36 an? A eae ene a Y Xx oa c (CIRCUIT FoR Y) D B (CIRCUIT FOR X) ==) (CIRCUIT FOR z) Ee gow> Se FOR ee ne FIGURE 6.36 Rap Sam wen 421 converter, fay M8 can make the cyclic to 8421 converter, 8421 102 T conve erter @ p71)6.15 Analysis Procedure of Combinational Logic 1 e analysis procedure of a Combinational circuit Is the raver, erie Seae process of a Combinational Circuit. It starts vty ee 4 diagram and culminates with a set of Boolean functions, a truth tablo, Oey: explanation of the circuit operation. Steps of Analysis procedure of Com a Ciruit are : 1. Check that given circult In Combinational : The first step is to that the given circuit is combinational or sequential. If a given Circuit hag} gates with no feedback paths or memory elements, then it is combi hea Circuit. Note that feedback path is a connection from the output of One gate, the input of a second gate. 2. Obtain the output Boolean functions : Once the lo a Combinational circuit, one can proceed to get the Steps are : (a) First mark the outputs of various arbitrary symbols. (b) Find the boolean functions for each output gates in terms of input varatls and arbitrary symbols. (c) By repetitive substitutions, we obtain the output variable as a functiond the input variables. Find truth table for logic diagram : Now find the truth table of output booles functions. Finally interpret the operation of the circuit from the derived truth table. Remarks : If the logic diagram to be analyzed is accompanied by a function nat or an explanation of what itis assumed to accomplish, then either the output functions or the truth table is sufficient for verification. va gic diagram is Verified a output boolean function, gates of given logic diagram wi 3. 4 Example 6.1 Analysis of the following logic diagram. Solution : A | | B. | | FIGURE 6.37ee : Given circuit has no feedback path or memory element, therefore, itis a set national circuit. ‘ a Obtain the output boolean functions 2: the outputs of various gates with arbitrary symbols as shown in figure 6.38 Mark FIGURE 6.38 Now =Ay (AB) SA+AB “(A+A)(AxB) (By distibutive law) iy3 (sA+A=1) 1173)T, =B(AB) =B+(AB) =B+AB =(B+A)(B+B) (Gydistributive law) =B+A (-B+B=1) Finally F, Ts =(+8)+(6+A) =(A.B)+(B.A) -B+BA TABLE 6.15 1 0 0 1 1 0 1 ° moe eo oo hl Step 4 : Finally, inspection of the truth table and output boolean functions (Fy Fas we can conclude that given logic diagram is a logic diagram of half adder. pal/ Subtractor (2'S complement) gaer nd subtraction operations can be combi si XOR gate with a full-adder as shown i includ yin { ined into one : common circu; in figure 6.39, sa ‘Truth Table of XOR FIGURE 6.39 Now if M=0 then output of F.A. (Full Adder) is A,+B, (A, is direct entry). If M=1 then ouput of XOR Gate is By - Mis also directly feed to F.A. Therefore input to Full Adder is Ao +(B+1)=A,-By . 8 +1=1s complement + 1 ' Mich is 25 complement and 2's complement is called -ve sign. i ‘ Parallel Binary Adder / Subtractor (2'S complement) fis 1 Adder / id Binary Adder, when we connect more than one 2's CO parallel actin parallel is known as Parallel Binary Adder / Subtractor. ®r/ Subtractor is shown in figure 6.30. bingy [175] FIGURE 6.40So if M=0 The Circuit gives S,=A,+B, and if M=1 S, = A,-B, i eae iar a faker In this circuit at each state two-bits are a ry to new Fe Exercise © OnAAPoNV> SePNSSRSNAS What do you mean by combinational circuit? Describe the design procedure of combinational circuit by giving example, Design the half adder and full adder. Design the half adder using only NAND gate. Draw the logic diagram of full adder by using only NAND gate. Explain the binary adder. Explain the half-subtractor and full-subtractor. Distinguish between encoders and decoders. Design a 6 x 32 decoder with the help of 3 x 8 decoders. Explain and draw the logic diagram of BCD to decimal decoder. Explain and draw the logic’ diagram of decimal to BCD encoder. Explain and draw the logic diagram of octal to binary encoder. Explain the multiplexer by using an example. Distinguish between multiplexer and demultiplexer. Design the 8 : 1 multiplexer. Explain the working of comparator. Explain the characteristics of digital integrated circuits. Explain'the steps of Analysis Procedure of Combinational Circuit. Analysis of the following Logic diagram Ao