Module 5: Integrated Circuits

ICs are the electronic circuits that are formed on small piece of semiconductor material , which
performs same function as large circuit made from discrete components.

5.1 Background
5.1.1 Advantages of Integration

 ICs are relatively Inexpensive

• The basic reason is that many identical circuits can be built simultaneously on a single Si wafer, this
process is called batch fabrication.
• Although the processing steps for the wafer are complex and expensive, the large number of resulting
IC makes the ultimate cost of each fairly low.
• The processing steps are essentially the same for both simple and complex circuits.
• As a result, the number of components in each circuit increases without a proportional increase in the
ultimate cost of the system.
• Unlike discrete components circuits, ICs allows extra components without increasing the cost of final
product.

 Reliability
• Reliability is also improved since all devices and interconnections are made on a single rigid substrate,
greatly minimizing failures due to the soldered interconnections of discrete component circuits.

 Miniaturization
• The advantages of ICs in terms of miniaturization are obvious.
• Since many complex circuit functions can be packed into a small space and it can be employed in many
applications where weight and space are critical (such as in aircraft or space vehicles).

 High- frequency and switching speed improvements

• For example, in high- frequency circuits it is necessary to keep the separation of various components
small to reduce time delay of signals.
• Similarly, in very high- speed computers it is important that the various logic and information storage
circuits be placed close together.
• Since electrical signals are ultimately limited by the speed of light, physical separation of the circuits can
be an important limitation.

 Parasitic Reduction
• Integration can reduce parasitic capacitance and inductance between circuits.
• Reduction of these parasitics can provide significant improvement in the operating speed of the system.

 Percentage of usable device/yield improvement

• Another important advantage has to do with percentage of usable devices (often called the yield) which
results from batch fabrication.
• Faulty devices usually occur because of some defect in the Si wafer or in the fabrication steps.
• Defects in the Si can occur because of lattice imperfections and strains introduced in the crystal growth,
cutting, and handling of the wafers.
• Usually such defects are extremely small, but their presence can ruin devices built on or around them.
• Reducing the size of each device greatly increases the chance for a given device to be free of such
defects.
5.1.2 Types of Integrated Circuits

• There are several ways of categorizing ICs as to their use and method of fabrication.
• According to application
1. Linear
2. Digital
• According to fabrication
1. Monolithic
2. Hybrid

Linear ICs Digital ICs

Linear ICs (Linear Integrated Circuits) are

Digital ICs (Digital Integrated Circuits) are
called as analog IC, it performs amplification/
also called as non linear IC.
linear operations on signals

Examples: microprocessor chips, memory

Examples: operational amplifiers, voltage
chips, analog to digital chips , digitals to
multipliers, voltage comparator, regulators,
analog chips, logic gates, flip flops, counters,
microwave amplifiers etc.
registers etc.

Its consist of very less number of transistor as Its consist of more number of transistor as
compared to digital ICs. compared to linear ICs.

• Large volume of ICs has been used in the digital field, since large numbers of such circuits are required.
• Because digital circuits generally require only the “on– off” operation of transistors, the design
requirements for integrated digital circuits are often less stringent than for linear circuits.

Monolithic ICs Hybrid ICs

Monolithic integrated circuits which Hybrid integrated circuits are fabricated by inter-
are fabricated entirely on a single chips. connecting a number of individual chips.

A monolithic integrated circuit has the full A Hybrid circuit often ceramic substrate
circuit constructed on a single piece of silicon. carrying one or more silicon chips.

Small in size as compared to hybrid ICs Large in size as compared to monolithic ICs

Monolithic ICs are expensive. Hybrid ICs are less expensive.

Speed is high as compared to hybrid ICs. Speed is low as compared to monolithic ICs.

Monolithic ICs provide smaller flexibility in Hybrid ICs provide greater flexibility in circuit
circuit design. design.

Advantage: hybrid circuits offer excellent

Advantage: All the components are contained isolation between components and allow the use
in a single structure that can be batch fabricated. of more precise resistors
and capacitors.
5.2 Evolution of ICs
• The IC was invented in February 1959 by Jack Kilby of Texas Instruments.
• The planar version of the IC was developed independently by Robert Noyce at Fairchild in July 1959.
• Since then, the evolution of this technology has been extremely fast.
• Figure 1 shows the number of transistors used in MOS microprocessor IC chips as a function of time.
• A straight line over four decades, indicates that there has been an exponential growth in the complexity
of chips.
• The component count follows “Moore’s Law” by Gordon Moore of Intel corporation.
• Moore’s prediction number of component /transistor on a chip doubles every 18 Months.

Figure 1: Moore’s law for integrated circuits:

Exponential increase in transistor count as a
function of time for different generations of
microprocessors

Eras of IC depending on component count

 Small- scale integration(SSI)- 1-102 devices,
 Medium- scale integration (MSI)-102 – 103
 Large- Scale Integration(LSI )103-105 devices
 Very large- scale integration(VLSI) 105-106 devices and
 Ultra large-scale integration (ULSI) -106-109 devices.
• The main factor that enabled complexity is the ability to scale/shrink device.

Figure 2: Exponential decrease in typical

feature size with time for different
generations of dynamic- random- access
memories (16- kb to 32- Gb DRAMs).
• Figure 2 shows typical dimensions or feature sizes of dynamic random- access memories (DRAMs) at
different times.
• There is an exponential decrease in the typical feature sizes with time over four decades.
• Advantages of scaling - faster ICs which consume less power.
• While scaling represents an opportunity, it also presents tremendous technological challenges(challenges
lie in lithography and etching).
• In addition, small features and large chips require device fabrication in extremely clean environments.
• Particles that may not have caused yield problems in a 100nm IC technology can have catastrophic
effects for a 22 nm process, which requires purer chemicals, cleaner equipment, and more stringent clean
rooms.

• In spite of the costs, the economic payoff for ULSI is tremendous.

• The total annual economic output of all the countries in the world, or (GWP), is about 85 trillion US
dollars.
• The US gross national product is about 16 trillion dollars.
• The worldwide IC industry output is about 350 billion dollars.
• The entire worldwide electronics industry in which these Ics participate is about 2 trillion dollars.
• As a single industry, electronics is one of the biggest in terms of the dollar amount.
• The cost per electronic function has dropped dramatically over the same period.
• For example, the cost per bit of semiconductor memory (DRAM) has dropped from about 1 cent/bit in
1970 to about 10-5 cent per bit today, an improvement of five orders of magnitude in 45 years.

• Currently, about 90% of the IC market is MOS based and about 8% BJT based. Optoelectronic devices
based on compound semiconductors is about 4% (expected to grow in the future)
• Of the MOS ICs, the bulk are digital ICs.
 Analog IC – 14%
 Semiconductor memories such as DRAMs, SRAMs, and nonvolatile
 flash memories - 25% of the market
 Microprocessors – 25%, and
 other application- specific ICs (ASICs) about 20%.

5.3 CMOS Process Integration

• One of the useful device for digital applications is a combination of n-channel and p-channel MOS
transistors adjacent on the chip. i.e., CMOS
• The drains of the two transistors are connected together and form the output.
• while the input terminal is the common connection to the transistor gates.
• The p-channel device has a negative threshold voltage, and the n- channel transistor has a positive
threshold voltage.

Vin nMOS pMOS Vout

0 OFF ON VDD(1)

1 ON OFF 0

(a)
Figure 3: Complementary MOS structure: (a) CMOS inverter; (b) formation of p- channel and n-
channel Devices together.

• The device technology for achieving CMOS circuits consists mainly in arranging for both n- and p-
channel devices with similar threshold voltages on the same chip.
• To achieve this goal, a diffusion or implantation must be performed in certain areas to obtain n and p
regions for the fabrication of each type of device. These regions are called tubs, tanks, or wells.

Latch up Problem in CMOS

• Due to close proximity of n-channel and p-channel devices in CMOS design leads to parasitic bipolar
structures.
• Latch up is defined as the generation of a low-impedance path in CMOS chips between the power
supply (VDD) and the ground (GND) due to the interaction of parasitic PNP and NPN bipolar junction
transistors (BJTs).
• Under certain biasing conditions the p- n- p part of the structure can supply base current to the n- p- n
structure, causing a large current to flow.
• This process, called latchup, can be a serious problem in CMOS circuits.
• Several methods have been used to eliminate the latchup problem, including using both n- type and p-
type tubs, separated by trench isolation.

• Most common technique in CMOS fabrication is twin- well Self- Aligned siLICIDE (SALICIDE)
CMOS process.
• This process is particularly important because most high- performance digital ICs, including
microprocessors, memories and application- specific ICs (ASICs) are fabricated by this process.
• There are three different CMOS fabrication process.
1. N-well process
If we start with p- epitaxial layer where n- channel devices in made. By implanting n- wells
wherever needed, p- channel device is made. This is an n- well CMOS process
2. P-well process
Alternatively, if we start with an n-substrate and make p- wells in certain regions, we have a p- well
CMOS process.
3. Twin-well process.
For optimal device performance, however, it is desirable to separately implant both the n- and the p-
Well regions, which is called twin- well CMOS.

Self- aligned twin well process

1. An n- well formation using P donor implant

To form the twin wells in a self- aligned fashion,

• First grow thermally a “pad” oxide (∼20 nm)on the Si substrate,
• Followed by low- pressure chemical vapor deposition (LPCVD) of silicon nitride (∼20 nm).
• This oxide– nitride stack is covered by photoresist, and a window is opened for the n- well.
• Reactive ion etching (RIE) is then used to etch the oxide– nitride stack.

Figure 4: (a) an n-
Well formation using P donor
implant and a photoresist
mask

Phosphorus is preferred to As
 Its Lighter
 Higher projected range
 Diffuses faster

2. p- well formation using B acceptor implant.

• After the implant, the photoresist is removed, and the patterned wafer is subjected to wet oxidation to
grow a “tank” oxide(~200nm)
• The tank oxidation process consumes Si from the substrate, and the resulting oxide swells up.
• The oxide does not grow in the regions that are protected by silicon nitride, because nitride blocks the
diffusion of oxygen and water molecules and thereby prevents oxidation of the Si substrate.

Need of Pad oxide

• It minimizes the thermal- expansion mismatch and concomitant stress between silicon nitride and the
substrate;.
• It also prevents chemical bonding of the silicon nitride to the silicon substrate.
• Using the tank oxide as a self- aligned implant mask, one does a p- type well implant using boron.

Self- aligned implant mask

• It is simpler and cheaper
• It allows a tighter packing density of the twin wells, because it is not required to account for lithographic
misalignment during layout.
• The P and the B are then diffused into the substrate to a well depth of typically a micron by a drive- in
diffusion at very high temperatures (∼1000°C)for several hours.

• After this diffusion, the silicon nitride– oxide stack and the tank oxide are etched away.
• Since the tank oxidation consumes Si from the substrate, etching it off leads to a step in the Si substrate
delineating the n- well and p- well regions.
• This step is disadvantageous from the depth- of- focus point of view during lithography.
• So, instead of a self- aligned twin- well process , one often uses two separate lithography steps for the
two well implants.
 Figure 4: (b) p- well formation
using B acceptor implant. A thick
“tank” oxide layer is grown wherever
the silicon nitride– oxide stack is
etched off.

3. An isolation pattern for field transistors

Isolation region
• Guarantee that there will be no electrical cross talk between adjacent transistors, unless they are
intentionally interconnected.
• This is achieved by ensuring that the threshold voltage of any parasitic transistor that may form in the
isolation regions is much higher than the power supply voltage on the chip, so that the parasitic channel
can never turn on under operating conditions.
• VT can be increased by
 Increasing substrate doping
 Increasing gate oxide thickness.
• But degrades sub-threshold slope, S.

• So one needs to optimize VT and S such that leakage current is minimal.

• A stack of silicon dioxide– silicon nitride is photolithographically pat-terned as in Fig. c and subjected
to RIE.
• A boron “channel stop” implant between the twin wells
 increases the acceptor doping and thus increases the threshold voltage in the p- well between the
n- channel transistors (the field threshold).
 However, B will compensate the donor doping on the n- well side, and thus reduce the threshold in
the n- well between p- channel devices.
• The B channel stop dose must thus be optimized to have acceptably high field thresholds in both types
of wells.

Figure 4: (c) An
isolation pattern for
field transistors
showing a B channel
stop implant using a
photoresist mask

4. Local Oxidation of silicon

• After the channel stop implant, the photoresist is removed and the wafer with the patterned nitride–
oxide stack shown in Fig. c
• It is subjected to wet oxidation to selectively grow a field oxide ∼300 nm thick.
• The nitride layer blocks oxidation of the Si substrate in the regions where transistors are made. This
• procedure is called LOCal Oxidation of Silicon (LOCOS).
• In this case LOCOS provides electrical isolation between the two transistors, as shown in Fig. d.

Figure 4: (d) local

oxidation of silicon
wherever the nitride
mask is removed,
leading to thick
LOCOS field oxide.

Fabrication steps for n-channel MOSFET in p-well

1. Formation of LDD structure

• The NMOS source and drain implants are done in two stages.
• The first implant is a lightly doped drain (LDD) implant (Fig a).
• When a MOSFET is operated in the saturation region, the drain- channel junction is reverse biased,
resulting in a very high electric field in the pinch- off region.
• Electrons traveling from the source to the drain in the channel can gain kinetic energy and thereby
become hot electrons, which create damage.
• The low doping in the LDD helps reduce hot carrier effects at the drain end.

Figure 5: Fabrication of the LDD structure, using

sidewall spacers.
(a) The polysilicon gate covers the thin gate oxide
and masks the first low- dose implant

2. Formation of oxide spacers

 This more conductive region allows ohmic contacts to the source and drain to be formed more easily
than the LDD regions.
 This implant is done using a self- aligned scheme by the formation of sidewall oxide spacers.
 After removing the photoresist covering the PMOS devices, we deposit conformal LPCVD oxide (100-
200 nm thick) using an organic precursor called tetra- ethyl- ortho- silicate (TEOS) over the entire
wafer.
 This oxide layer is then subjected to RIE, it leaves oxide sidewall spacers on the edges of the polysilicon
gate.

Figure 5:(b) A thick layer TEOS is deposited by CVD (c) anisotropically etched away to leave only the
sidewall spacers
 3. Source and Drain Implant
• This sidewall spacer is used as a self- aligned mask to protect the LDD regions very near the gate during
the heavier, deeper n+ source and drain implants as shown in figure 5c
4. Formation of PMOS
• Next, the NMOS devices are masked by photoresist, and a p+ source and drain implant is done for the
PMOSFETs.
• LDD is not used for the PMOS. This is due to the fact that hot hole effects are less problematic than hot
electron degradation.
• After the source– drain implants are done, the dopants are activated and the ion implant damage is
healed by a furnace anneal, or more frequently using a rapid thermal anneal.

(e)
Figure 5:(d) These spacers serve as a mask for the second, high- dose implant. (e) self- Aligned p+
source–drain implant with no LDD using photo-resist to protect NMOSFETs

• The next step is to form a metal– silicon alloy or silicide in the Source-drain and gate regions of the
MOSFETs in order to reduce the series resistance and increase the drive current(figure 6a)
• This involves depositing a thin layer of a refractory metal such as Ti over the entire wafer by sputtering,
and reacting the Ti with Si wherever they come in direct contact, by doing a two- step heat treatment
in an N ambient.
 A 600°C anneal results in the formation of Ti2 Si
 Followed by an 800°C anneal to form TiSi2

Figure 6:The formation of silicided source–

Drain and gate regions (a) a layer of refractory
Metal to form a conducting silicide layer

• The Ti on top of the sidewall oxide spacers does not form a silicide and stays as un-reacted.
• The Ti and TiN can be etched off selectively by using a wet hydrogen peroxide- based etch, which
does not attack the titanium disilicide, thereby electrically isolating the gates from the source-drain.

• Finally, the MOSFETs have to be properly interconnected according to the circuit layout, using the
metallization level.
• This involves LPCVD of an oxide dielectric layer doped with B and P, which is known as boro-
phospho- silicate glass(BPSG) on the entire wafer, patterning it by means of the contact- level reticle
and using RIE to open up the contact holes to the substrate (Fig. 6b).
• The B and P allow the oxide layer to soften and reflow more readily upon annealing, thereby helping
planarize the wafer.
• This shaping of the millions of very small contact holes is critical on a ULSI chip, because otherwise
metal deposited on the surface into the contact holes may not reach completely into the holes, leading to
a open circuit.
• In fact, sometimes a CVD tungsten layer is selectively deposited in the contact holes to form a contact
plug before one proceeds to the next step.

Figure 6: (b) the unreacted metal is removed

and a CVD glass is deposited and patterned for
contact metallization

• In a modern ULSI chip, the complexity of the device layout generally demands that multiple levels of
metallization be used for interconnecting the devices.
• Hence, after the first metal is deposited, an inter-metal dielectric isolation layer such as SiO2 is
deposited by low-temperature CVD.
• Low temperatures are very important
 by now all the active devices are in place and
 one cannot allow the dopants to diffuse significantly.
 Also, the metallization cannot withstand temperatures higher than ∼500°C.

• The dielectric isolation layer must be suitably planarized prior to the deposition of the next layer of
metal, and this is generally done by CMP.
• After planarization of the isolation layer, one uses photolithography to open up a new set of contact
holes called vias.

• Finally, a protective overcoat is deposited on the IC to prevent contamination and failure of the devices
due to the ambient.
• This generally involves plasma CVD of silicon nitride, which has the nice attribute that it blocks the
diffusion of water vapor and Na through it.
• Sodium causes a mobile ion problem in the gate dielectric of MOS devices.
• Sometimes, the protective overcoat is a BPSG layer. After the overcoat is deposited, openings are etched
for the metal bond pads.
• After the chips are tested in an automated tester, the known good dies are packaged and wire bonded.

5.4 Integration of other Circuit elements

Diodes
• It is simple to build p-n junction diodes in a monolithic circuit.
• It is also common practice to use transistors to perform diode functions.
• Since many transistors are included in a monolithic circuit, no special diffusion step is required to
fabricate the diode element.
• There are a number of ways in which a transistor can be connected as a diode.
• The most common method is to use the emitter junction as the diode, with the collector and base shorted.
• This configuration is essentially the narrow base diode structure, which has high switching speed with
little charge storage.
• Since all the transistors can be made simultaneously, the proper connections can be included in the
metallization pattern to convert some of the transistors into diodes.

Resistors

• Diffused or implanted resistors can be obtained in monolithic circuits by using the shallow junctions.
• For example, during the base implant, a resistor can be implanted which is made up of a thin p- Type
layer within one of the n- type islands.
• An n- type resistor channel can be included within the resulting p region during the emitter implant step.
• In either case, the resistance channel can be isolated from the rest of the circuit by proper biasing of the
surrounding material.
• For example, if the resistor is a p- type channel obtained during the base implant, the surrounding n
material can be connected to the most positive potential in the circuit to provide reverse- bias junction
isolation.
• The resistance of the channel depends on its length, width, depth of the implant, and resistivity of the
implanted material.
• Since the depth and resistivity are determined by the requirements of the base or emitter implant, the
variable parameters are the length and width.

• Design of diffused resistors begins with a quantity called the sheet resistance of the diffused layer.
• If the average resistivity of a diffused region is t, the resistance of a given length L is
R=ρL/wt
• Rs measured for a given layer is numerically the same for any size square(L=w)
• for a given diffusion, the sheet resistance is generally known with good accuracy.
• The width w as small as possible within the requirements of heat dissipation and photolithographic
limitations and then calculate the required length from w and Rs.
• Design criteria for diffused resistors may include the presence of high current density at the inside corner
of a sharp turn. So round corners slightly in a folded or zigzag resistor to reduce the problem.
• To reduce the amount of space/obtain larger resistance values, it is often necessary to obtain surface
layers having larger sheet resistance than is available during the standard base or emitter implants.
• Then a different implant, such as the VT adjust implant, to form shallow regions having very high sheet
resistance.

Figure 7: Monolithic resistors: (a) cross section showing use of base and emitter diffusions for resistors;
(b) top view of two resistor patterns
Capacitors
• One of the most important elements of an integrated circuit is the capacitor.
• This is particularly true in the case of memory circuits, where charge is stored in a capacitor for each bit
of information.
• Figure illustrates a one- transistor DRAM cell, in which the n- channel MOS transistor provides access
to the adjacent MOS capacitor.
• The top plate of the capacitor is polysilicon, and the bottom plate is an inversion charge contacted by an
n+ region of the transistor.
• The terms bit line and word line refer to the row and column organization of the memory.

Figure 8: Integrated capacitor for DRAM cells.

A one- Transistor memory cell in which the
transistor stores and accesses charge in an
adjacent planar MOS capacitor

Inductors

• Inductors have not been incorporated into ICs in the past,

 Because it is much harder to integrate inductors than the other circuit elements.
 There has not been a great need for integrating inductors.
• Recently, that has changed because of the growing need for rf analog ICs for portable communication
electronics.
• Inductors are very important for such applications, and can be made with reasonable Q factors using
spiral wound thin metal films on an IC.
• Such spiral patterns can be defined by photolithography and etching techniques compatible with IC
processing, or they can be incorporated in a hybrid IC.

Contacts and Interconnection

• During the metallization step, the various regions of each circuit element are contacted and proper
interconnection of the circuit elements is made.
• Aluminum is commonly used for the top metallization, since it adheres well to Si and to SiO2 if the
temperature is raised briefly to about 550°C after deposition.
• Gold is used on GaAs devices, but the adhesion properties of Au to Si and SiO2 are poor. Gold also
creates deep traps in Si.

• Silicide contacts and doped polysilicon conductors are commonly used I integrated circuits.
• Increased complexity and packing density in integrated circuits inevitably leads to a need for multilayer
metallization.
• Multiple levels of Cu metallization can be incorporated with interspersing dielectrics.
• In general, the metals may all be Al, Cu or they may be different conductors such as polysilicon or
refractory metals.
• Also, the dielectrics may be deposited oxides, boro-phospho-silicate glass for planarization.
• The planarization of the surface is extremely important to prevent breaks in the metallization.
• The most important challenge in designing interconnects is the RC time constant, which affects the speed
and active power dissipation of the chip.
• Resistance is given by
• The capacitance is given by

• The RC time constant is then

• From equation above, it is clear we need as thick a metal layer and as low a resistivity as possible.
• Low resistivities are also important in minimizing ohmic voltage drops in metal bus lines that carry
power from one end of a chip to the other.

Figure 9: Equivalent circuit illustrating the

various parasitic capacitive elements
associated with a multi Level interconnect.

 Copper has even lower resistivity than Al and is about two orders of magnitude less susceptible to
electromigration.
 Hence, it is an excellent alternative to Al for very high speed ICs
 The process breakthroughs that have made Cu viable for metallization include new electrodeposition and
electroplating techniques because
 CVD is not very practical for Cu.
 It is also very difficult to use RIE for Cu because the etch byproducts for Cu are not very volatile.
 Copper can create traps deep in the band gap of Si; hence, a suitable barrier layer such as Ti is needed
between the Cu layer and the Si substrate.
 Other parameters in Eq that can minimize the RC time constant is the use of a thick inter- metal
dielectric layer and as low a dielectric constant material as possible.

 In designing the layout of elements for a monolithic circuit, topological problems must be solved to
provide efficient interconnection without crossovers— points at which one conductor crosses another
conductor.
 If crossovers must be made on the Si surface, they can be accomplished easily at a resistor.
 Since the implanted or diffused resistor is covered by SiO2, a conductor can be deposited crossing the
insulated resistor.
 In cases requiring crossovers where no resistor is available, a low- value implanted resistor can be
inserted in one of the conductor paths.