ECEN 449: Microprocessor System Design

Department of Electrical and Computer Engineering

Texas A&M University
Prof. Sunil P. Khatri

Lab exercise created and tested by:

Abbas Fairouz, Ramu Endluri, He Zhou, Andrew Douglass and Sunil P. Khatri

Laboratory Exercise #7
IR-Remote Peripheral for Linux System

Objective
The objective of lab this week is to create and test hardware which receives and decodes Infrared (IR)
signals from a universal television remote. You will create the IR detection hardware on a bread board and
use Verilog to implement the decoding (i.e. demodulating) hardware within the FPGA. The demodulation
hardware will be encapsulated within a custom IP peripheral so that messages from the TV remote are
software accessible. An oscilloscope (Figure 1) will be used to test the bread boarded hardware, while the
demodulation process will be tested via a software routine executing on the Zynq Processor.

System Overview
The hardware system you will be creating in this lab is very similar to that of Lab 4, except the multiply
block will be replaced by a custom peripheral for demodulating the IR signal from the universal remote.
The IR receive block refers to the analog hardware that will be implemented on the bread board. The labs
that follow will integrate the IR peripheral into a more complex Linux System like that of Lab 4. However,
for this lab, we want to keep the hardware as simple as possible. The sections that follow explain the theory
of operation for the IR remote and the corresponding decoding logic.

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Figure 1: MSOX3024T Mixed Signal Oscilloscope

• IR remote control: The basic principle of an IR remote control is to utilize infrared light for transmit-
ting short control messages from the remote control to the IR receiver. Pulses of infrared light which
represent specific binary codes are transmitted from the IR remote . These binary codes correspond
to commands such as ‘Power On/Off’, ‘Volume Up/Down’, etc. The receiving hardware decodes the
pulses of light back into binary codes and uses them to command the device under control. The IR
remote we will be using encodes the binary data using Pulse Width Modulation as seen in Figure 3.
In addition to the binary data pulses, each pulse train consists of a ‘START’ pulse. A negative edge
transition separates each pulse.

• IR Receiver: We will use an IR photo-transistor to detect the pulse train generated by the remote
control. The IR photo-transistor is a transistor such that the emitter-collector current is proportional
to the amount of infrared light that strikes the junction. Thus, the current through the emitter-collector
junction increases when light falls on the photo-transistor. We will create a simple detection circuit
which converts the light pulses into a binary signal. The output of our detection circuit will feed
into a demodulator circuit which will use the length of the various pulses to demodulate each control
message.

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Figure 2: Zynq System Diagram

Negative Signal Transition Edges

Start 0 0 1 0 0 1 0 0 00 0

Figure 3: PWM Encoded Pulse Train for IR Remote

Procedure
1. You do not need to use the ZYBO Z7-10 board for the first part of lab. You will build your circuit on
the breadboard provided and utilize the multi-meter and oscilloscope as necessary.

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(a) Build the circuit shown in Figure 4. Use the power supply on your workbench (as shown in
Figure 5), to provide a voltage source of Vcc = 3.3V to your circuit. The comparator pin-out
diagram is provided for you in Figure 1a, and you may use any of the four available comparators.
Note the 10k Ω pull up resistor connected to the output terminal. This resistor is necessary
because the output of the comparator is an open-collector output.

Figure 4: IR Receiver Circuit

(b) Observe the signal IR signal on the oscilloscope, while pointing the remote control towards
the IR photo-transistor and pressing any key (Make sure your remove is in ‘TV’ mode). You
should see a pulse train on the oscilloscope where high and low are at 3.3V and 0V respectively.
Demonstrate your progress to the TA.
(c) Each control message from the remote is 12-bits in length. The remote sends a sequence of
messages when a button is held down. Hold down a button on the remote and hit ‘Run/Stop’ on
the oscilloscope to freeze an entire message pulse train.
(d) Using Figure 3 as a guide, measure the length of the ‘Start’, ‘0’, and ‘1’ pulses. You will need
to use the time axis cursors on the oscilloscope to do this. Try to make your measurements as
accurate as possible and note them in your lab manual.
(e) Use the sample codes provided in Table 1 to ensure you are interpreting the pulse train properly.
Read up on Pulse Width Modulation if the modulation scheme is unclear.

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Figure 5: E36311A Tripple Output Programmable DC Power Supply

2. At this point, you are ready to begin building the FPGA hardware. The next few steps will guide you
through the process of creating a base system for testing the custom IR peripheral and provide you
with some guidelines for creating the IR demodulation hardware.

(a) Create a block design in Vivado with everything shown in Figure2, except the IR hardware. If
any doubts about the procedure refer to lab 4.
(b) The ir demod module will be implemented on the FPGA. To set the clock frequency for the
module follow the instructions below.
• Double click on the Zynq Processing System IP to customize it.

Key Code
Volume Up 010010010000
Channel Up 000010010000
Channel 1 000000010000
Channel 2 100000010000

Table 1: Sample Command Codes

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Figure 6: LM339 Comparator

• Select ’Clock Configuration’ and expand ’PL Fabric Clocks’.

• Set the frequency of FCLK CLK0 to 75MHz for this lab.
(c) Use Vivado to create the template code for a custom peripheral with four software accessible
registered as outlined in Lab 3. Label the peripheral ‘ir demod’.
(d) In the ‘ir demod v1 SOO AXI.v’ file, disable all AXI write capabilities to the software accessi-
ble registers and ensure the AXI read capabilities remain.
(e) Since our peripheral has an input pin (i.e. IR signal from Figure 4), we must add it to the port
list of our ‘ir demod v1 SOO AXI.v’ file. Do this now using IR signal as the port name. Use
the auto generated comments as a guide for where to insert your changes.
(f) The ‘ir demod v1 SOO AXI’ Verilog module is instantiated in the ‘ir demod v1.v’ file. Define
the user port IR signal here and connect it to the IR signal defined in ‘ir demod v1 SOO AXI.v’.
(g) Now use the following guidelines to create user logic for demodulating the digital signal from
the first part of the lab.
• Use a counter to measure the length of each pulse in order to determine its significance.
Pulses in order of decreasing pulse length are as follows: ‘Start’, ‘1’, and ‘0’. The appropri-
ate count value for each pulse must be predetermined based on the rate of the system clock
and the oscilloscope measurements made in Part 1 of the lab.

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• Use a separate state register to keep track of which count value the counter has hit. For
example, since a ‘start’ pulse is the longest, the counter will hit the count value for the ‘0’
first, followed by the count value for ‘1’, and finally the count value for ‘start’.
• You will need to detect both negative and positive edges using edge detection circuitry.
Negative edges signify the beginning of a pulse while positive edges signify the end of a
pulse.
• Your logic will need an intermediate register to hold the bits of the IR message as they
arrive. Depending on your implementation, your logic may also need a register to keep
track of the current bit position of the arriving bit stream.
• Use slv reg0 to hold the latest demodulated message. This register shall by loaded after the
arrival of a complete 12-bit message.
• Use slv reg1 to hold a running count of the number of messages that have been received.
• The third software accessible register may be used for debugging.
• Read the auto-generated codes in ‘ir demod v1 SOO AXI.v’ carefully. If you use ‘S AXI ARESETN’
in your code, please notice that ‘S AXI ARESETN’ is active LOW. (NOTE: it is recom-
mended to use an external reset signal, and connect it to one of the push buttons in the
ZYBO Z7-10 board).
(h) Once your source code modifications are complete, select the ‘Ports and Interfaces’ tab in the
Package IP window. Click on the ‘Merge changes from Ports and interfaces Wizard’ at the top
of the window. If this option does not appear, type the following command in the TCL console:
ipx : : merge project changes ports [ ipx : : c u r r e n t c o r e ]

(i) Re-Package IP and import your custom IR peripheral into your Zynq system.
(j) Make the ‘IR signal’ port of your IR peripheral external by right clicking on the IR signal and
select ‘Make External’. This will create an external port with name ’IR signal’. Then create an
XDC file to connect the external signal to pin V15 on the ZYBO Z7-10 board.
(k) Create HDL wrapper, generate bitstream, and export to the SDK.
(l) Create a simple test application that continually polls your IR hardware registers and prints them
in hexadecimal format to the screen when a change is detected. You do not need to implement a
delay for this part. Do not forget to cast the base address of IP to type ‘u32’.
(m) Do NOT connect any hardware to the ZYBO Z7-10 board until the TA has inspected your setup.
Have the TA verify this is correct.
(n) Connect Vcc = 3.3V , GND, and the appropriate IR signal pin on the ZYBO Z7-10 board to your
IR receiver circuit built in Part 1 of the lab.
(o) Make sure the JP5 is set to JTAG mode and verify that your system is working by creating a
bitstream and downloading it to your ZYBO Z7-10 board. If your hardware is not operating
properly, you may be required to use Vivado and SDK to debug your user logic. Within Vivado

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you can create a test module that produces a sample pulse train and then debug your hardware
using the Vivado simulator.

Deliverables
1. [7 points.] Demo the working IR demodulation hardware to the TA.

Submit a lab report with the following items:

2. [5 points.] Correct format including an Introduction, Procedure, Results, and Conclusion.

3. [2 points.] The output of the Picocom terminal.

4. [6 points.] Answers to the following questions:

(a) What are the hexadecimal control codes for the following buttons:
• volume up/down
• channel up/down
• stop/play
• 1, 2, 3, and 4
Tabulate your results.
(b) When a button is pressed on the remote, multiple copies of the same command message are sent.
Approximately how many of the same command message are transmitted after each press of a
button? Provide some intuition as to why multiple messages are sent.
(c) What modifications would you make to your code to provide an internal signal that goes high
when a new message comes in? You do not have to synthesize this modification, but please
provide the Verilog code that would do this. Hint: you can use the message count register. If
this signal was made available to the processor, what might this signal be used for?

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