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ST 33 KTPM 2 Xi 2 C

This document provides information on TPM 2.0 devices with SPI or I2C interfaces from STMicroelectronics. It describes the key features of the ST33KTPM2XSPI and ST33KTPM2XI2C devices, which include compliance with TCG and FIPS standards, various cryptographic algorithms, and an extended temperature range. The document also provides details on the UFQFPN32 package pinout and signals.

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0% found this document useful (0 votes)
51 views21 pages

ST 33 KTPM 2 Xi 2 C

This document provides information on TPM 2.0 devices with SPI or I2C interfaces from STMicroelectronics. It describes the key features of the ST33KTPM2XSPI and ST33KTPM2XI2C devices, which include compliance with TCG and FIPS standards, various cryptographic algorithms, and an extended temperature range. The document also provides details on the UFQFPN32 package pinout and signals.

Uploaded by

jbs
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

ST33KTPM2XSPI ST33KTPM2XI2C

Data brief

TPM 2.0 devices with an SPI or I²C interface

Features
TPM features

• Flash-memory-based trusted platform module (TPM)


UFQFPN32 (5 × 5 × 0.55 mm)
• Compliant with Trusted Computing Group (TCG) trusted platform module
(TPM) Library specifications 2.0, revision 1.59 errata version 1.3 and TCG PC
Client Platform TPM Profile (PTP) for TPM 2.0 Version 1.05
• Fault-tolerant firmware loader that keeps the TPM fully functional when the
loading process is interrupted (self-recovery)
• SP800-193 compliant for protection, detection and recovery requirements
• Targeted certifications:
– Common Criteria in compliance with the TPM 2.0 protection profile
(augmented with AVA_VAN.5, resistant to high-potential attacks)
– FIPS 140-3
– TCG certification
• SPI support at up to 66 MHz
• I²C communication bus running at up to 1 Mb/s

Hardware features
• Highly reliable flash memory with error correction code
• Extended temperature range: −40 °C to 105 °C
• ESD (electrostatic discharge) protection up to 4 kV (HBM)
• 1.8 V or 3.3 V supply voltage range

Security features
• Active shield
• Monitoring of environmental parameters
• Hardware and software protection against fault injection
• FIPS SP800-90A and AIS20-compliant deterministic random-bit generator
(DRBG)
• FIPS SP800-90B and AIS31-compliant true random-number generator (TRNG)
• Cryptographic algorithms:
– RSA key generation (1024, 2048, 3072 and 4096 bits)
– RSA signature (RSASSA-PSS, RSASSA-PKCS1v1_5)
– RSA encryption (RSAES-OAEP, RSAESPKCS1-v1_5)
– SHA-1, SHA-2 (256 and 384 bits), SHA-3 (256 and 384 bits)
– HMAC SHA-1, SHA-2 and SHA-3
– AES-128,192 and 256 bits
– ECC (NIST P-256, P-384 curves): key generation, ECDH and ECDSA,
ECSchnorr
– ECDAA (BN-256 curve)
• Device provided with 3 endorsement keys (EK) and EK certificates (RSA2048,
ECC NIST P_256 and ECC NIST P_384)
• Device provisioned with three 2048-bit RSA key pairs to reduce the TPM
provisioning time

DB4737 - Rev 2 - January 2023 www.st.com


For further information contact your local STMicroelectronics sales office.
ST33KTPM2XSPI ST33KTPM2XI2C

Product's targeted compliance

• Compliant with Microsoftt ® Windows® 10 and 11


• Compliant with Linux® drivers
• Compliant with Intel® vPro® technology
• Compliant with TCG test suite for TPM 2.0
• Compliant with the open-source TCG TPM 2.0 TSS implementation

DB4737 - Rev 2 page 2/21


ST33KTPM2XSPI ST33KTPM2XI2C
Description

1 Description

The STSAFE-TPM (trusted platform module) family of products offers a broad portfolio of standardized solutions
for embedded, PC, mobile, and computing applications.
It includes turnkey products compliant with the Trusted Computing Group (TCG) standards that provide services
to protect the confidentiality, integrity, and authenticity of information and devices.
The STSAFE-TPM devices are easy to integrate thanks to the variety of supported interfaces and the availability
of TPM ecosystem software solutions.
They target Common Criteria, TCG, and FIPS certification.
The ST33KTPM2XSPI offers a slave serial peripheral interface (SPI) by default whereas the ST33KTPM2XI2C
offers exclusively a slave SPI or a slave I²C interface. Both devices are compliant with the TCG PC Client TPM
Profile specifications.
It offers resilience services during the TPM firmware upgrade process, and self-recovery of TPM firmware and
critical data upon failure detection.
The ST33KTPM2XSPI and ST33KTPM2XI2C operate in the –40 °C to 105 °C extended temperature range.
The device is offered in the UFQFPN32 ECOPACK2 package. ECOPACK is an ST trademark.

DB4737 - Rev 2 page 3/21


ST33KTPM2XSPI ST33KTPM2XI2C
UFQFPN32 pin and signal description

2 UFQFPN32 pin and signal description

The figure below gives the pinout of the UFQFPN32 package in which the devices are delivered. Table 1
describes the associated signals.

Figure 1. UFQFPN32 pinout

I2C_SDA/GPIO_6
I2C_SCL/GPIO_5
NiC
NiC

NiC
NiC
NiC
NiC
32 31 30 29 28 27 26 25
VPS 1 24 SPI_MISO/GPIO_0
GND 2 23 NiC
NiC 3 22 VPS
UFQFPN32
NiC 4 21 SPI_MOSI/GPIO_3
NiC 33
NiC 5 20 SPI_CS/GPIO_2
GPI_I2C_Select/NC(1) 6 19 SPI_CLK/GPIO_1
GPIO_PP 7 18 PIRQ
NiC 8 17 RST
9 10 11 12 13 14 15 16

DT70353V2
(1) GPI_I2C_Select for ST33KTPM2XI2C products
NiC
NiC
NiC
NiC
NiC
NiC
NiC
GND

NC for ST33KTPM2XSPI products

DB4737 - Rev 2 page 4/21


ST33KTPM2XSPI ST33KTPM2XI2C
UFQFPN32 pin and signal description

Table 1. UFQFPN32 descriptions

Signal Type Description

Power supply. This pin must be connected to 1.8 V or 3.3 V DC power rail supplied by
VPS Input
the motherboard.
GND Input Ground, has to be connected to the main motherboard ground.
Reset, active low, used to re-initialize the device. Must not be unconnected. External
RST Input
pull-up resistor required if it cannot be driven.

SPI master input, slave output (output from slave) / General-purpose input/output if I2C
SPI_MISO/GPIO_0 Output(1)
is activated
SPI master output, slave input (output from master) / General-purpose input/output if
SPI_MOSI/GPIO_3 Input(1)
I2C is activated

SPI_CLK/GPIO_1 Input(1) SPI serial clock (output from master) / General-purpose input/output if I2C is activated
SPI chip (or slave) select, internal pull-up (active low; output from master) / General-
SPI_CS/GPIO_2 Input(1)
purpose input/output if I2C is activated
PIRQ Output IRQ, active low, open drain, used by the TPM to generate an interrupt
Physical presence, active high, internal pull-down. Used to indicate physical presence to
GPIO_PP Input
the TPM.
This pin must be connected to an external pull-down resistor to activate the I²C protocol
GPI_I2C_Select Input during product boot time. It can remain unconnected for the SPI protocol.
This pin is internal pull-up by default and becomes internal floating after I²C activation.
Not internally connected: not connected to the die. May be left unconnected but no
NiC -
impact on TPM if connected.
NC - Not connected: connected to the die but unused. Must be left unconnected.
Input/ Bidirectional I²C serial data (open drain without a weak pull-up resistor) / General-
I2C_SDA/GPIO_6
output(1) purpose input/output if SPI is activated

Input I²C serial clock (open drain without a weak pull-up resistor) / General-purpose
I2C_SCL/GPIO_5 Input(1)
input/output if SPI is activated

1. In GPIO configuration, this signal is Input/output.

Note: The UFQFPN32 package has a central pad (PIN33) on the bottom, which is not connected to the die. This pin
does not impact the TPM, be it connected or not.

DB4737 - Rev 2 page 5/21


ST33KTPM2XSPI ST33KTPM2XI2C
Electrical integration guidance

3 Electrical integration guidance

This section gives some guidance on how to integrate the ST33KTPM2XSPI or ST33KTPM2XI2C device in an
application.

3.1 Recommended power supply filtering


The power supply of the device should be filtered using the circuit shown in the figure below.

Figure 2. Recommended filtering capacitors on VCC

VCC
VCC1
VCC2
1 µF
100 nF
(Min)
Device +

GND
GND1

DT64224V1
GND2

Table 2. VCC rising slope

Symbol Parameter Min. Typ. Max. Unit

SVCC VCC rising slope 2 - 2 · 103 V/ms

Note: Measurement must be done between 1.36 V and 1.62 V

3.2 SPI_CS optional filtering


Recommendation for SPI_CS integration: It is mandatory that SPI_CLK is at the low logic level when the falling
edge occurs on the SPI_CS signal. An external capacitance of 56 pF is recommended on SPI_CS for that
purpose. This capacitor might not be required depending on the intrinsic line capacitance, the SPI bus frequency,
or both.

DB4737 - Rev 2 page 6/21


ST33KTPM2XSPI ST33KTPM2XI2C
Device integration for SPI communication

3.3 Device integration for SPI communication


The figure below shows the typical hardware implementation of the ST33KTPM2XSPI device for SPI
communication.

Figure 3. Typical hardware implementation for SPI communication (UFQFPN32 package)

32

NiC 31

NC 30
29

NiC 28

NiC 27

NiC 26

NiC 25
NiC

NC
VPS 1 VPS SPI_MISO
SPI_MISO 24 33 Ω
GND 2 GND NiC 23 VPS
3 22
NiC VPS
UFQFPN32 SPI_MOSI 10 kΩ
4 NiC SPI_MOSI 21 33 Ω
NiC 33 SPI_CS
5 NiC SPI_CS 20 1 µF
6 SPI_CLK 100 nF
(Min)
GPI_I2C_Select SPI_CLK 19 33 Ω
GPIO_PP (opt) 7 GPIO_PP PIRQ
PIRQ 18
56 pF
8 NiC RST 17 RST
16 GND
NiC
10 NiC
11 NiC

NiC
13 NiC
14 NiC

15 NiC
9

12

DT68966V1
Surrounds optional
components

GND

Note: The use of a low-value resistor (typically 33 Ω) on SPI_MISO, SPI_MOSI and SPI_CLK can be recommended
for line adaptation when the signals are affected by parasite spikes. Its use is mandatory to avoid disturbance of
the ramp-up and ramp-down signals.
Note: The capacitor on SPI_CS is optional (see Section 3.2 SPI_CS optional filtering).
Note: The pull-up resistor on the PIRQ line is mandatory to optimize the power consumption in standby mode.

DB4737 - Rev 2 page 7/21


ST33KTPM2XSPI ST33KTPM2XI2C
Device integration for I²C communication

3.4 Device integration for I²C communication


The figure below shows the typical hardware implementation of the ST33KTPM2XI2C device for I²C
communication.

Figure 4. Typical hardware implementation for I²C communication (UFQFPN32 package)

1 kΩ

1 kΩ

SDA
SCL
32
31
30
29

NiC 26
NiC 25
28

27
VPS

SDA
NiC
NiC
SCL

NiC
NiC
1 VPS NC 24
2
GND GND NiC 23
1 µF
100 nF
(Min)
3 NiC VPS 22
4 NiC NC 21

10 kΩ
5 UFQFPN32
NiC NC 20
GPI_I2C_Select 6
GND 2.2 kΩ GPI_I2C_Select NC 19
GPIO_PP (opt) 7 PIRQ
GPIO_PP PIRQ 18
8 RST
NiC RST 17

16 GND
9 NiC
10 NiC
11 NiC

NiC
NiC
14 NiC
15 NiC
12

13

DT68967V2
GND

Note: The pull-up resistor on the PIRQ line is mandatory to optimize the power consumption in standby mode.

DB4737 - Rev 2 page 8/21


ST33KTPM2XSPI ST33KTPM2XI2C
Package information

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

4.1 UFQFPN32 package information


UFQFPN stands for 32-pin, 5 × 5 × 0.550 mm, 0.5 mm pitch, thermally enhanced, ultra-fine pitch, quad flat
package, no lead.

Figure 5. UFQFPN32 - Outline


D

ddd C
e A1
C
A3
SEATING PLANE
D1
b

E2 b
E1 E

1
L
32
D2 L
PIN 1 Identifier A0B8_ME_V3

1. Drawing is not to scale.


2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to the PCB ground.

DB4737 - Rev 2 page 9/21


ST33KTPM2XSPI ST33KTPM2XI2C
UFQFPN32 package information

Table 3. UFQFPN32 - Mechanical data

Millimeters Inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236


A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 - 0.300 0.0071 - 0.0118

D(2) 4.900 5.000 5.100 0.1929 0.1969 0.2008

D1 3.400 - 3.700 0.1339 - 0.1457


D2 3.400 - 3.700 0.1339 - 0.1457

E(2) 4.900 5.000 5.100 0.1929 0.1969 0.2008

E1 3.400 - 3.700 0.1339 - 0.1457


E2 3.400 - 3.700 0.1339 - 0.1457
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.


2. Dimensions D and E do not include mold protrusion, not to exceed 0.15 mm.

Figure 6. UFQFPN32 - Recommended footprint

5.30

3.80

0.60

3.45

5.30 3.80

3.45
0.50

0.30

0.75

3.80 A0B8_FP_V2

1. Dimensions are expressed in millimeters.

DB4737 - Rev 2 page 10/21


ST33KTPM2XSPI ST33KTPM2XI2C
Delivery packing

5 Delivery packing

Surface-mount packages can be supplied with tape and reel packing. The reels have a 13" typical diameter.
Reels are in plastic, either anti-static or conductive, with a black conductive cavity tape. The cover tape is
transparent anti-static or conductive.
The devices are positioned in the cavities with the identifying pin (normally Pin “1”) on the same side as the
sprocket holes in the tape.
The STMicroelectronics tape and reel specifications are compliant with the EIA 481-A standard specification.

Table 4. Packages on tape and reel

Package Description Tape width Tape pitch Reel diameter Quantity per reel

UFQFPN32 Very thin fine pitch quad flat pack no-lead package 12 mm 8 mm 13 in. 3000

Figure 7. Reel diagram

A N

D C

Table 5. Reel dimensions

Reel size Tape width A Max. B Min. C D Min. G Max. N Min. T Max. Unit

13” 12 330 1.5 13 ±0.2 20.2 12.6 100 18.4 mm

DB4737 - Rev 2 page 11/21


ST33KTPM2XSPI ST33KTPM2XI2C
Delivery packing

Figure 8. UFQFPN32 - Embossed carrier tape


P0
P2
Y E
T
D

D1

F
W
B0

Y
K0 P A0

Section Y - Y
User direction of feed

1. Drawing is not to scale.

Figure 9. UFQFPN32 - Chip orientation in the embossed carrier tape

User direction of feed

Table 6. UFQFPN32 - Carrier tape dimensions

Package A0 B0 K0 D1 Min. P P2 D P0 E F W T Max. Unit

UFQFPN 5×5 5.3 ±0.1 5.3 ±0.1 0.75 ±0.1 1.5 8 ±0.1 2 ±0.05 1.55 ±0.05 4 ±0.1 1.75 ±0.1 5.5 ±0.1 12 ±0.3 0.3 ±0.05 mm

DB4737 - Rev 2 page 12/21


ST33KTPM2XSPI ST33KTPM2XI2C
UFQFPN32 package marking information

6 UFQFPN32 package marking information

Parts marked as E or ES (for engineering sample) are not yet qualified and therefore not approved for use in
production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for
the customer using any of these engineering samples in production. ST’s Quality department must be contacted
prior to any decision to use these engineering samples to run a qualification activity.

Figure 10. UFQFPN32 standard marking example

Package face: top

Unmarkable surface

A
Marking composition field

B C

D E F G

I
J
H

Legend:

A: Marking area – 8 digits G: Assembly week (WW)


B: Marking area – 3 digits H: Second level interconnect
C: BE sequence (LLL) I: Standard STMicroelectronics logo
D: Country of origin (3 characters allowed (max.)) J: Diffusion traceability plant (WX)
E: Assembly plant (PP) K: Dot(1)
F: Assembly year (Y)

1. The dot on the back side indicates the pin 1 location.

DB4737 - Rev 2 page 13/21


ST33KTPM2XSPI ST33KTPM2XI2C
Ordering information

7 Ordering information

Table 7. Ordering information

Factory
Supported A marking B marking
Product family Ordering code Package firmware
interface(s) area area
version

ST33KTPM2XSPI ST33KTPM2X32CKE2 UFQFPN32 9.256 SPI KTPM KE2


ST33KTPM2XI2C ST33KTPM2X32CKE3 UFQFPN32 9.256 I²C & SPI KTPM KE3

DB4737 - Rev 2 page 14/21


ST33KTPM2XSPI ST33KTPM2XI2C
Support and information

8 Support and information

Additional information regarding ST TPM devices can be obtained from the www.st.com website.
For any specific support information you can contact STMicroelectronics through the following e-mail:
[email protected].
STMicroelectronics has put in place a Product Security Incident Response Team (ST PSIRT). We encourage you
to report any potential security vulnerability that you might suspect in our products through the ST PSIRT web
page: https://www.st.com/psirt.

DB4737 - Rev 2 page 15/21


ST33KTPM2XSPI ST33KTPM2XI2C

Revision history
Table 8. Document revision history

Date Revision Changes

10-May-2022 1 Initial release.


Updated:
• TPM features and Hardware features in cover page
• Section 1 Description
• Section 2 UFQFPN32 pin and signal description including
Figure 1. UFQFPN32 pinout and Table 1. UFQFPN32 descriptions
• Section 3.1 Recommended power supply filtering including
Figure 2. Recommended filtering capacitors on VCC and Table 2. VCC
rising slope
27-Jan-2023 2 • Section 3.2 SPI_CS optional filtering
• Section 3.3 Device integration for SPI communication inlcuding
Figure 3. Typical hardware implementation for SPI communication
(UFQFPN32 package)
• Section 3.4 Device integration for I²C communication including
Figure 4. Typical hardware implementation for I²C communication
(UFQFPN32 package)
• Section 4.1 UFQFPN32 package information: corrected typo on
introduction and on line D2 of Table 3. UFQFPN32 - Mechanical data

DB4737 - Rev 2 page 16/21


ST33KTPM2XSPI ST33KTPM2XI2C
Glossary

Glossary

AES Advanced encryption standard RSASSA Rivest Shamir Adelman signature scheme
with appendix
CA Certification Authority
SHA Secure Hash algorithm
CC Common Criteria
SPI Serial peripheral interface
DRBG Deterministic random bit generator
TCG Trusted Computing Group®
EC Elliptic curve
TPM Trusted platform module
ECC Elliptic curve cryptography
TRNG True random number generator
ECDAA Elliptic curve direct anonymous attestation
(algorithm) TSS TPM software stack

ECDH Elliptic curve Diffie–Hellman

ECDSA Elliptic curve digital signature algorithm

EK Endorsement key

ESD Electrostatic discharge

FIPS Federal Information Processing Standards

GPIO General purpose input/output

HBM Human body model

HMAC Hash-based message authentication code or


keyed-hash message authentication code

I²C Inter-integrated circuit

NIST National Institute of Standards and Technology

NV Nonvolatile

PKCS Public key cryptographic standards

PSS Probabilistic signature scheme

RNG Random number generator

RSA Public-key cryptosystem (created by Ron Rivest,


Adi Shamir and Leonard Adleman)

RSAES Rivest Shamir Adelman encryption/decryption


scheme

DB4737 - Rev 2 page 17/21


ST33KTPM2XSPI ST33KTPM2XI2C
Contents

Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 UFQFPN32 pin and signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical integration guidance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Recommended power supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 SPI_CS optional filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Device integration for SPI communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Device integration for I²C communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Delivery packing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6 UFQFPN32 package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
8 Support and information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

DB4737 - Rev 2 page 18/21


ST33KTPM2XSPI ST33KTPM2XI2C
List of tables

List of tables
Table 1. UFQFPN32 descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. VCC rising slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Packages on tape and reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. UFQFPN32 - Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DB4737 - Rev 2 page 19/21


ST33KTPM2XSPI ST33KTPM2XI2C
List of figures

List of figures
Figure 1. UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Recommended filtering capacitors on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Typical hardware implementation for SPI communication (UFQFPN32 package). . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Typical hardware implementation for I²C communication (UFQFPN32 package) . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. UFQFPN32 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Reel diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. UFQFPN32 - Embossed carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. UFQFPN32 - Chip orientation in the embossed carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. UFQFPN32 standard marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DB4737 - Rev 2 page 20/21


ST33KTPM2XSPI ST33KTPM2XI2C

IMPORTANT NOTICE – READ CAREFULLY


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DB4737 - Rev 2 page 21/21

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