gen sa PONS Mey moe te nis RM an SM wn mS, Fa A rin wags, 1 cd ad fon eens Be ty ee ese spent nema soa, yp, eer a ta ines are avaiable in uP 80859 ow ary abies ad WP sons) Assembly Language Programming 34 INTRODUCTION ‘Waking programs using mnemonics to solve specific roblems is called assembly language programing. The interface between hex codes and Imnemoncs i called aisemler wich canbe thease (ogame) o the ‘machine In and asembly the ser himself decodes the mnemonics by eonsing the mnemouin cat and feds dough the hex Keyboard so the ‘The progam conting of instructions writen by a user in an atserbly language is called a source progran. The source progam is converte isto ‘machine program tough the objecUmoaltr program present i the P ‘An instruction ia inary pater designed inside a Pt perform a specie function, “The eae roup of seventy four (7) insiructons i called the instruction set The whole instaction ses divided into thre genera yes 4 Information moving instructions * Infomation modifying instructions Conta nations ach ofthese te is then furtber divided int varios groups. Figure 3.1 ilsrates the iaseucion set of HP BOBS, [eeee | [eee] [eaae] [orm] [one Figure 31 Types of nsuctonspascae, POTAMTIG 8 lr cose acing pr ncoes isa fF, LDAX, DCX, SHLD, INX. 10ST sc EE ints Groop loving operation ae cari ow ee nn loin oP a eto eee Oceenbee oe er HE net DF SME ot te pp oF HIN OIE te Ny, Gea et pnt) Oso xe sete Sy 0 ee 1 ination aio stn ing eta ot ge oo ne ser or register pair (i adion [ADI2L, ADD B, ADD M, ADC B, ADC M. ‘ay tmambr cones of any eit contens of any memory lig ihe aed othe cnet ofthe acamulatr. ERAMPLES ‘ADI isrucion means tt data byte 21(H) is immediately avai {oe ton oe comets ofthe secular ADD B instctin meas hal conten of tester B are added oh cones of secular, ADD Misracoe means that cartes of memory location whos ais lead in the HL pi ae alded to the contents of the accumula. ql UCB and ADCM. he coe of Band Mate ade wih et can im ecm of sy iter canot be dicly ae Sees a te ep, for ado one ofthe data rust be i ‘An excpion tothe above eis shh mire. the inseucton DAD in which 21 Gi) Subtraction fae Any &-bit number or contents of i ‘subtracted from the cong te imu ip an rf resalt remain = accumulator using this instruction Wi 8 8 cal ind navrty ngs Progaming #9 i Logical operations sey bt number or contents of any register or memory lation cn te ‘Ay ANDORNOR whe coments of be acum wing as isction rope eat eaiing ia he scolar fs on. (00) Compare tiny fie number or contents of any register or memory lean ean be eed (or >< of =) wih the comets of the accumulator using this ftometion withthe rest modifying x Mag. “Group "a" & 3 inarutons Wasser the exceuton ofa progam rom {ts ptt leeton 1 sre othe oction in the memory. The want ay 1 Sontona U2, NZ, 3C) of unconditional (MP). eae ven in Figure 32 ee wl EEE da pea er ee eee ese Figue 32 Byte ergsrizaton In rons. or example, an istration MVIB, byte has a hex code 06 whichis created from the group ‘0° instruction format given above of the binary EEEE Figure 23. Example for oun 0.precture, Programming and Intertacig os esa “tracing woes OAT soy argngePegnmnig_ 22 INSTT command whe PHO POM EC og (ADD B: Add te coment of (B) to the coments of (A) sac 90 PE " psd ADD 1 in 1 ea 1 be Peed ag «psu eB 5) Open ot dr 19 OPEL pon 2 Bayes 10 00 1 Or ied in ass WAYS &5 SHOWN in Figure 34 1 Bescnde 630 neqealc (i) BUA er Geomplene exh compen i (A) — * Opeateu Cua pee '* Operand is implicitly (A) —— '* Binary code is 0010 L111 roy | [Pang ea hots 2 cz | Pee ae ino ae red in 4 iu foma in memey of he toca tring co ty heen oy aa ‘ean a be 1 ig e opeton ae nt von his iy cole and an toe ade te per ing © oe no exauries () MIA, 05 Lond. da ye (2 in sxamatr ee © Op-code is MVI A ieeangrecenett © Operand is 32 [ercaie ‘Operand ‘© Binary code is OOL1 1110 for MVI A [ee : | 1 Hes cote fr MV A and 32 fr it ye vevcon | [recta A Se iron ht be ate Op-Coe and the 2d and Se aproae byes opengl ade The nd ye teow nr se od a eet ten the 3rd byte is the higher order address, Ion as clied aconding othe wor ie o word a (i) JMP 2048: Inrcion mean 0 taser he progam sens 10 + follows: ae suri “ ‘the memory location 2085. - * iret 3 memory lotion to dae memory 1 te a ye i Retesrietds (2 tnador ye natn * Oper i Sat te nd 20 as 2nd yt wed oy tenn 5 bla cae 110 0 foe IMP Live instructionincdes the p-code and the operand in the a 1+ Hex code C3 foe IMP. a 185 for oe ase ) + 20 for igh order adress byte MOV GA: Copies coments of (A) into (C) + Opsoie a ay 33 DERIVATION OF HEX CODES FOR INSTRUCTIONS + Opera is C4 Manufacturers design instructions according to intemal circuitry of the * Binuy coe is 0100 LLnL riclar iP. To detive ex codes for the insuctons we use he following fey ‘bles ee Tales 31.35) LLable M canes fo Re ance Programanng ad Inetacing cing and Sending Repisers — Tabs 1c A2 Codes foe Information Register Operations nit oe “Table 3.3 Coles fr Arthmetict Immesine opera on rest pir Incement Mecrement ister pst noone single eiser Decenent snl ier Inmednte operation om single eer Reiser sit ncellaeons ‘Table 34. Codes for Branching Lope Repser Operations Operations Fre operation “hess Reiner operation Hi one a 000 Cononal vm Ph Asti 001 Simple eum : si 010 Conon! jmp 100 pa a8 100° Conditonl call 101 Simpl et 110 Special ALU operations eee ee Assenbiy Lanquaga rogranming 7 jms Branching ‘Table 35 Cove for Condit p00 tree are on Heary Bo) tor Hi even pty OPE) ma negative OM EXAMPLE (i) MVUB, byte: Using Tales 3.1 and 32. since MV belongs 0 sro0 ‘owe have alee eee Group Receiving regier ‘nfo. registers fers immediatly avaloble data byte 10 the Tr O00 O1T0 ae shown above and he “This instruction aa register, I bas a inary 0 ae 06. (a) MOV B, ug Tables 3.4 and 32, since MOV belongs 10 the eet o Using neloo ee ees “Group ‘Receiving (By reper Sending resisters -thisinsructon transfer data byte rom the C reps tothe B exit. Tres pinay code O100 O001 as shown above and hex code $ iy ADD B: Using Tale 33 since ADD belong the sro alam os one! ae jaee Group ‘Por addon For Breiser k ‘Tis insuuction adds data byte of B resister to data byte of (A) a itn ede 1000 0000 as shown above and Bex code #0 Go) SNZoadrems Usingibles34and3Ssine INZelngs 10007 rele go eos olen ees For INE For conditional jane Groupsyning a0 Intrtacing : su aan be tess PALES Big abo amt Bex ole C2 = MODES 34 ADDRESSING MOD : Ff geipng dt are called aressing modes, TE Ree rds haa tnt 2 Diet ewe 4 Reiter Indies hen SEE ee oe inmate tin me Ss eer ‘s data. In the }-byte instruction, Ist byte is Op-code, 2nd and eerie ee a } e clex| [se[s rift Ts erefaie we ce ae Figure 37° MOV B,C. 4. The register indirect mode of adéressing refers to the memory locations using the contents ofa reper pair. This second memory location adres isthe actualleective memory address where the data content to be processed will e resentored, for example LDAX B. Load accumulator indirect implying load accumulator with the contents of the memory location sored inthe BC register pai. emis Inciracéon | Memory th —4 = i om | am =e =o fectheara eumittn desir a a «6 | Fou 35 104 coos ‘ean addressing mode, te register or register pais that ts we specified, eg, MOV B.C (se Figure 3.7) Figure 88 LOAK 8 5 Inherent or implied addressing mode: An insrucion mode in hich the operand is absent in the isttion format, fo example, STC (steamy flag): HLT (stop processing). Details about instructions: 1. MOY ry, m3: move data from register 10. ‘This istuction copies each byte of data rom register Ft without isturbing the contents of reise, For example, MOV A, D; MOV M, A (Figue 39) ‘Tn MOV MA instruction the data byte $0 ying in accumulator is transfered (othe address location D003 specified inthe register pu HLSVT foe MT MLE © | one Fae 39 MOV 1 MFP sce Figure 3.10), MAFF means wansfer data byte FF 0 the 1 ri sp ea pce nthe eptey Move data immediately tothe available iene ication MT specified inthe HL register pit. tak | FF le Memory ction -aleea| =a Figure 350° ev FF te HL “ier ps 1/2 meas ner data bye U2 othe accumulator “ao ate from OD to FF. for example, MVI A, smory location |v extended spies pats (gp) BC, DE and HL. with aye to 448 FEE This ‘i the weiter pi ‘wel aval, Here “rp represents #0 uD for DE, tha is nly the fst register nae i8 en dhs streton “iy Obit a aly suentay vgs Praparieg 5h For example, suppse we want meve a data hte which is loaded in the memory location MIFF tothe B register Here, me cannot wse the MVE Manton We ve LXt insracton to fie load the adress (OFF into the HL aplster pai and then we the MOV instruction 10 copy the data yte fom Inemony tothe BL egistr a shan sn Figure 310 XI H, OOFF MOV BM Figure 331 UX H, OOFF ‘The above instructions mean load extended register HL with the address OFF where the data byte 2B is stored. 4UINR rand DCR #:IncremenvDecrement in the contents of any register" by unity. The valid registers wed a5 operands ae A. Bs ED, E, Hy L. M. INR and DCR instructions SET all flags except cay flag. For example, DCR ME: decrement in the contents of memory location stored in tegister pair HL by unity (Figure 3.12), 8 om (ef) = ene Lm one | ao PACE oes | oF Av epwoT 0 coos | Figure 3.12, INR, i) DER B: Decrement inthe contents of register B by nity. Let ‘before this instruction B contains OOD, After this instruction B contents willbe FF(H) as illstated below. 2 coman) 01 > og09 001Aeventiy Language Progamming 59 pe stars fo nerementiecremen eden NN fy unt These mstnvetons, A. LDAX ip, STAX ep: LDAX stands for loting the accumulator ingore a hes mn Airc wih the Cmte the metey cose Iie ye aes STAX sands fr string Gini the coments of th secu ino Tn the menor atone stein hetepecr rye Stade tothe LDAX. STAX and LDAX ae any vad ere Band DE eee Te ye san ot = IF res For example, LDAX D means tal (A) with contents of memery Ixcation sored in register pir DE. As illustrate in Figure 3.17 the accumulator (A) ‘loaded withthe contens (2A) wansfeed from the memory location (305) Figure 313 DCX stored inthe (DE) register pir, A000 IV: oF FFA 000 iF] oc | coo | 14 aa ; = ee 8 [el Figure 318 NK H eet p{ o | [el ret) with contents of 6: UDA Heit addres: Load accumulator (iret) aaa era tthe Io ess, fr example LDA 00S oe fo] : x Figure 3.17 LOAK . + example STA O00S (Figure 3.16) Figure 218 StAX. | a SSTAX Bs Store the contents ofthe accumulator (A) withthe contents ofthe mm | ‘memory locaton address given in the register pair BC. As illuated in ar © Figure 3.18, the contents (09) stored in accumulator (A) ae transfered to the Ee ‘memory locaton (005) sored in register (BC). ws ° e | - c— Figure 318 LOA on06 aalawtle matte lar LDA ONS is LXE H.O00S. ° e oes | 7 STA Veit addres: Sure contents of the acumulator into the 1 Helo bit addes. 1 is opposite to the s “ ees ace | | 9. LIILD 16-bit address: SHLD 16-bit address: LHLD stands for loading direct) the contents of thel6-it memory adress given in | ‘he insuction into the HL egiste pit, SHLD stands for storing ect) the contents ofthe HL rp into the 16-bit memory adress ven inthe instraction, For example, LAULD 2050: imo HL igure 3.19), lol the contents of memery loaton 2050 Fiowe 136 Sta cao,ring ad netacing ] = - nf or | om fe wl] >| ~ figure 219, LHLD 2050 seo 365 Scone FH 6 MERE eg aco | FF le} — 2061 or rigue 329 SHLD 250 cr xngig the conent oF HL eit with i nD and coments of L th hs of amie he fling Pog, 10, XCHG: DE registers. Con To understand this insta LXTH, 038 LXID. 0820 MOV A.M NCH ADD M eis o Figure 3.21 to understand the above program. The XCHG instruction fips sefeening two memory locations ata ime Toe To au of [a je xa | [——-| | | | >| 20 wen v8 3046 7 of | = |e nfo [a |e Figue 321 xcHs. The XCH instruction helps referencing two memory locations a2 1. DAD ep, DAL has cnn father reiterate of ree The result remains inthe HL pat The DAD insteton i valid nly for BC, DE, HL and SP pais. "trim se the cary ag nly and doesnot affect other 8 ‘Assembly Language Programming 55 For example, (i) DAD HE Let HL contain 0242, then ater this instvtion HL will be O484 (Figure 322) ADH w]e |e «fo [# ] Figure 322. OAO H. Gi) DAD SP: Let HL contain 0000¢H) and SP contain 2099CH) then DAD SP will make 0000 + 2089 = 2099(H) in HL. as shown in Figure (323). nf @ | @ |. ose a] « | mo | a | Figure 3.23, DAD SP. 12, DAA: This sands for decimal adjust accumulator. This instruction puts ach digit inthe accumulator back into the binary coded decimal ‘The contents ofthe accumulator are changed from a binary number toa bit BCD digits All fags S, Z, AC, P and CY are affected. ‘The DAA instruction converts the binary conteas ofthe accumulator as fllows: 1. If the valve of the low owder 4-its (D3-DO) inthe accumulator i ‘more than 9 of if AC flag is set then tbe DAA instruction adds 06 to the low order 45. 2. If the value ofthe high order 4bits (D7-D4) in the accumulator is ‘more than 9 or ifthe CY fla is set then the DAA instruction adds (06 tothe high order is. For example, add decimal (BCD 12) to the accumulator which contains (BCD 39), 9 = oor scot 12 = oo 00 (200) St = oFen or —+ eB Hen) Since the value of low order byte is greater than 9, adding 06 tothe low order its 48 = o1oo1001 (6 = ooonon10 (We St = 101 cot 13. PUSH rp. & POP rp PUSH stands for copying 2-bytes of data from any register par tothe stack pointer (SP) register. POP stand for copying 2-bytes of data from the memory location to any ofthe register pits, Revster pairs can be BC, DE, HL or PSW.progaening an noting cosa $85—ACMESE 6 Mero a Caen aman * Eas +E ar 1 a tan 398 2097 ad contents of oy Te Seite cee = mor ‘fee Sh dee Seitigier (EL PS ‘Senor tc FSW gram scala sd te gst Sine hw eee a Wes neste coef he Sack pointer reer That the SP point othe memory Tocation 2090, that is SP 1 word) represents the contents of the "The ceumtator isthe high order register al CT) es te] DEE ‘ae [xx sp[ 20 | 92 Figure 325. POP H. 1M. SPHL: This intrcton copies the contents of HL register pair into the tack pointer ester. The H register coments goto the high order ‘ess while the L register contents go into the low order address. No flags ae affected and contents of HL register pair are not altered, le HL contin OLFS(H) a shown in Figure, 3.26. Sate] zor | “Tae ae | 01 08 | ox Figue 325. SPHL SPHL causes the conte "ssa the contents Ot into 2058 and FS into 2097 Assembly Language Programming $7 15, XTHL: This s used wo exchange the contents ofthe L register with the contents af memory loeaton pointed to bythe stack poater register land the contents of H reps are exchanged with the next stack pointer location (SP +1). The content of stack pointer register are no lee No flags are affected by the use ofthis instruction. Fr example, let HL contain A257(H) SP contain 2095(H) then XTHL eases HL to contain 673804) ‘and 2095(H) and 2096(H) of SP to contain A257(H) a shown in Figure 3.27 rele]. »-fe[e [as [ss so [ms [7 ae | 67] aoe | A oer [mt se+[=] =] oa [x Figure 327. XTH, 1 stands for set cary flag to 1 stands for complement the cary fag ‘These instructions have no operands 17, JUMP instructions: There are two types of jump instructions, (@) unconditional: IMP 16-bit address (©) conditional: These ate of the following &-ypes, (0) IC 16-bit address: jump if cary (carry flag set, CY = 1) (i) INC 16-bit address: jump if no carry (cary flag reset, cy=0) (ii) 32 t6-bit address: jump if zero (zero flag set, Z = 1) (Gv) JNZ. 16-bit adress: jump if not zero (ero flag reset, 2: (JM 16-bit adress: jump if minus (sign flag set, S = 1) (si) JP 16-bit address: jump if positive (sign flag reset, S = 0) (iy IPEL6-bit address: jump if parity even (parity flag set, P= (i) JPOL6-bit address: jump if parity odd (parity flag reset, » » For example, JZ 2050 instruction transfers the rogram sequence tothe memory location 2050 when the zero flag is set (the result of some operation in the accamulator becomes 20 so that Z= 1). If he 2er0 flag isnot set the execution sequence is not altered by the jump instruction, 18. Comparison instructions: These are of the following two types. (@) CMP r or CMP M: Compares the contents of operand register (bere refers B, C.D, E, H,L, A) or memory locaton (M). ‘whose address is stored in the HL register pair) with that of the accumulator (A), Contents in both remain preserved and comparison is indicated by the seting or resetng ofthe flags shown below:nd Itrtc sna, pogaring nd ering ou 85 sp weno ce Metter CY ag se yen A Zt SEM then CY and Z fps are rea ine contents ofthe operand fog sider CMP B, lt (A) con, ass the CY 10 5b sa fren 288. re [ele fen an fe nen ft accumula chong ad te suf te comparison dues Tec by te sans of flags a5 gve Blows ad se in) < Bi data hen cay flag is st, CY = Traspens ina) = Sit daa, then Ze Magis se, Z Freee in >i at thn cary ad 27 Mags are est, Z CY =0 har enparion of two bytes performed by subtracting te an ee cnt fe wut, CPL zt rama (A) contin C2; CPL wil compare C2 with 98 and secant 25 96 efor Z nd CY ae rest, The oer flags 8, AC and ao get ret (A) reais wnchanged. 18.) IN Ait adress (b) OUT Sit adres Si aes 00 10 FP [With Nisin he cones ofthe input por given in the pend Si adres. ae rad and loaded in the accumulator. Sir. th OUT instruction is wsed to output data from the accumulate 1910 ein te pandas ogy at acted by these isto, = bese} ‘perations: uP 8085 can perform all the logic operation’ Se intone en Below 1 ANG Lodeay AND coment ofthe reser) with at CY is eset and AC ist (i) ANI i datas accumu (4) CV is reset a AC i et Logically AND B.bit data with the contents (ii) ORA re Logically OR contents of the register () with that of sccurulator (A) CY anid AC flags are reset (iv) ORI Sit data: Logically OR f-bit data with the contents of accumulator (A), CY. AC ate rose, (6) XRA Logically XOR the contents of register (f) with those of a, CY, AC reset, (i) XRU Bit data: Logically XOR 8-it dat with the contents of (a, CY, AC ese, (vil) CMA Complements the contents of (A) No flags are affected. For example, let (A) contain 1000 1001 = $9 (H), then (OMA gives 0111 0110 = 76 4 21, Register rotation: The contents of accumulator register can be shifted let or right by oe bit each time and rotation ofall the S-bits fan be achieved, Rotation can be used to produce multiplication and division in powers of 2. Following rotation based instructions are employed, () RAL: Bach bit ofthe secumulator (A) is rotated lft by one position through the cary flag. CY flag is modified according to bit Dy, Other flags are unaffected, ‘Assume accumulator (A) has A7 and CY = 0 In Figure 3.29, binary number 11100101 (= A7(H)) in the accumulator is modified after the RAL instruction to 01110010, 2 Diep PoP PTT jie ox | 1 ofrfololrtiafrjo Figure 329 FAL. ‘The Dy bit is placed in CY flag and the previous CY bit is put in as the Dy bit in the accumulator (A) register. (ii) RAR: Rota the accumulator contents right through carry. Each bit ofthe accumulator is rtated right by one position though the CY flag. Bit Dy is placed in the CY flag and inital CY bit is placed in the Dy Postion. For example, consider the accumulator contents as shown in Figure 3.30. After the RAR instruction the contents get modified in accumulator (A)roromning ant ttetacing Fo | Amu cores | = fece' rsiarson ran Accu contens = tharne ntrston RAR, ae ee cecum sate lel by one bit positon, cae em ey cam 8 seogielelelal temas ‘her enatton ALC Figure 331 LC. Diference with RAL Contents of the CY fag are not placed in bit Dy asin ‘ie isracon RAL, RRC: Stands for rou accumulator right. Bach bit of the suluior raed right by one positon. Bit Dy is placed inthe Psion of bit Dy aswell asin the CY flag. CY flag is modified coming to bt Dy, py a coset the conten nthe acamultor before the instruction ‘ono ie Figute 3.32, After RRC the contents in accumulator (A) CF bn Accumulator contort ‘ere en Figure 332 ac Assembly Language Programming 61 Difference with RAR: Contents of the CY fag are ot placed in bit poston Dyas in RAR 22, RIM: Stands fr read interrupt mask isa multi-purpose statement hich is used to check the status of the intemupts 7 5, 55 and ‘ead and transfer serial input data available at SID pin to the MSB. position of the accumulator register. No flags are affeted by this instruction. This instruction loads its ofthe accumulator with the following interpretations as shown in Figure 3.33, solv] |e] 75] 5] 55] 5B BH Bo oe Powe cot, 17,16, 15; Pending interupts, enabled if each bi TB: iterrupt enable flip-flop, is set if Ds = 1 7, 65, $5: interrupts masked, if each bit = 1 For example, et after the execution of RIM instruction in a program the accumulator contained 49(H) as shown in Figure 3.34. eT Tepe[ feleys] Figure 8.04 Accumulator contents for FIM, ‘We can explain these contents in the following way: ‘The above contents of bits ie inthe accumulator register in which D, = 1 implies tha RST 5.5 is masked Dj = implies that RST 63 is enabledtunmaske, Dy = 0 implies that RST 5.5 is enabled/unmasked 1 implies that imerupt enable flip-flop is et Ds, Ds, Dy = 0,0, 1 implies that RST 7.3 i pending. 23, SIM: Stands for set interrupt mask. Is 2 multipurpose instruction hich is used to implement interupts RST 7.5, 65 and 5.5 as wel 18 serial output data (SOD). This instuction interprets he sceumulator contents as follows (Figue 3.35) [ose ee pe seat 5 OO OO Fw 335i Dy = serial dat enable, 1 to enable and 0 to disable. Dy = reset R75, if bt Dy = mask set enable, if bit = 1 Dy, Dy, Dy = mask all interupts, if each bit = 1ro, Programming and Intrtacing aa span wt SO ine sven Below a Assembly Language Programming 6 : wit a. sa ssetDs = 2. Add the contents of register B and D by placing the contents of NM Na acme cOmets FN 10 MBE Dy | ay ‘one fepistr in the (A) sing ADC B or ADC D. ting cay © Ds | 24(H) = 0010 0100 IN : cpa Don the SOD fine ‘S4(H) => 0101 0100 seit adres: unconditional sbroutine call: The OU, = 0000 OBL = CY from he prevons ation 2. CALL ei fre ales specified y the open me HH) <> O11 TOOT wore in vegiter B SE Trev, For example, consider the CALL istacton 28. ADD #/M: Add contents of register (f) or memory (M) to (A) 15 £5 So a0 to calla subroutine located a 205, Centete The ruler aiton ts ord in he acemlator_For Pio cath 280 ‘tample, le accumulator (A) conan TE), memory locaton (2050) 2390 ‘contain A2(H) and register pair (HL) contain 20S0(H). er) Inston: LXTH, 280; ADD M cates long HL sp with 2050 ese ET: rau ro sbrotine unconditionally and then ang the cones of 2050 with coment of he (A). opr Tati) = 0111 0110 ea A2H) = 1010 Afi 90 as. ¢ almaye sed in conjunction withthe CALL statement T8(H) = 10001 1000" therefore CY = 1,Z=0, AC=0,P=0 29, ADI Shit data: add (Jmmediate) 8-it data to the contents of (Ad: The S-bit data available mmeditely sade to the accumslator ‘contents and esl is placed inthe accumulator All igs are modified For example, ADI S8(H): let (A) contain 4, so that 4A) = 0100 1010 9H) = 9101 1008 ‘AH = 1010 0011 ArshmeceIncractions 26 ACL Sit data: add immediate) to accumulator contents the 8 bit data with carry: Is commonly used for 16-bit addition, Al {ass ae moied. Previous cary fag is reset, For example, ACL $7) assume tat A) contains 26 (H) and CY = 1, cary Mag i et ‘Then afr this insretion i exeuted, O60 O10 = 26 01 OL = 37 30, Subtract operation instructions: e08 01 = CY {@) SBB r/M: Subtract contents of register or memory location and m1 110 the contents of borow flag from the contents ofthe (A), “The result is placed in the (A) and the previous borrow fag is reset. For example, SBB B: subtract the contents ofthe B register with borrow ‘rom te contents ofthe (A) Let (A) coatain 37 and (B) contain 3F. Submaction ‘is performed in 2s complement form. AC=0, Previous cary cleared ADC FM add the contents of egster (e) oF memory (M) with accumulator (A) contents " 2 vith carry: All the flags are modified (21 fg is reset. is commonly used for 16-bit E 2 & & si o> im ess and sore the result in BC. Borrow = +01 borrow needs tobe added fist tothe subtrahend he cen Cand Ey 40 = 0100 0000 Sie Tis ase ERY Bling he comets of one rexiset 2's complement of 40H is = 1100 0000 20 0d a9 the on eae Ae. Using the instruction (a) = O11 O11 = FIG 1) tot agg PS i repister C, ‘LITT O111 = borow fag is set to ind 1014 a te that heres isin 2's io ae pment cary List 01th» cone em cy More in © repister