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FA HA Comp Code

This document defines three VHDL components: a half adder (HA), an OR gate, and a full adder (FA) built from a HA and OR gate. The HA outputs the sum and carry. The OR gate outputs the logical OR of its two inputs. The FA takes three inputs, uses two HAs to generate intermediate signals, and an OR gate to output the final carry.

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26 views2 pages

FA HA Comp Code

This document defines three VHDL components: a half adder (HA), an OR gate, and a full adder (FA) built from a HA and OR gate. The HA outputs the sum and carry. The OR gate outputs the logical OR of its two inputs. The FA takes three inputs, uses two HAs to generate intermediate signals, and an OR gate to output the final carry.

Uploaded by

bhslegion1498
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HA is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
s1 : out STD_LOGIC;
c1 : out STD_LOGIC);
end HA;

architecture Behavioral of HA is

begin
s1 <= a1 xor b1;
c1 <= a1 and b1;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity or_1 is
Port ( a2 : in STD_LOGIC;
b2 : in STD_LOGIC;
y1 : out STD_LOGIC);
end or_1;

architecture Behavioral of or_1 is

begin
y1 <= a2 or b2;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FA_HA_comp is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end FA_HA_comp;

architecture Behavioral of FA_HA_comp is


signal s2, s3, s4 : STD_LOGIC;
component HA
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
s1 : out STD_LOGIC;
c1 : out STD_LOGIC);
end component;

component or_1
Port ( a2 : in STD_LOGIC;
b2 : in STD_LOGIC;
y1 : out STD_LOGIC);
end component;
begin
lvl1 : HA port map (A, B, s2, s3);
lvl2 : HA port map (s2, Cin, S, s4);
lvl3 : or_1 port map (s3, s4, Cout);
end Behavioral;

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