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MUX 4to1 Code

This document defines a 4-to-1 multiplexer entity with inputs I0 through I3, select inputs S1 and S0, and output Y. The architecture uses the select inputs to determine which input is passed to the output, with S1 and S0 encoding the selection from the 4 possible inputs.

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50 views1 page

MUX 4to1 Code

This document defines a 4-to-1 multiplexer entity with inputs I0 through I3, select inputs S1 and S0, and output Y. The architecture uses the select inputs to determine which input is passed to the output, with S1 and S0 encoding the selection from the 4 possible inputs.

Uploaded by

bhslegion1498
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Mux_4to1 is
Port ( I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
S1 : in STD_LOGIC;
S0 : in STD_LOGIC;
Y : out STD_LOGIC);
end Mux_4to1;

architecture Behavioral of Mux_4to1 is


Signal a, b, c, d : STD_LOGIC;
begin
a <= I0 and (not S1) and (not S0) ;
b <= I1 and (not S1) and S0 ;
c <= I2 and S1 and (not S0) ;
d <= I3 and S1 and S0 ;

y <= a or b or c or d ;
end Behavioral;

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