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Greatest Common Divisor Circuit Design Greatest Common Divisor Circuit Design

This document describes the design of a greatest common divisor (GCD) circuit. It includes block diagrams and schematics showing the comparator, selector array, multiplexers, and overall system. Digital simulations verify the functionality of each component and the overall GCD computation. Layout designs were checked for design rule and layout versus schematic errors. Power and area estimates are provided based on transistor counts and simulated latency. The GCD circuit was designed using a 0.8um CMOS process and has an estimated area of 0.6412mm^2 and power consumption of 13.32mW at a clock frequency of 240MHz.

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vishalideepak1324
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12 views

Greatest Common Divisor Circuit Design Greatest Common Divisor Circuit Design

This document describes the design of a greatest common divisor (GCD) circuit. It includes block diagrams and schematics showing the comparator, selector array, multiplexers, and overall system. Digital simulations verify the functionality of each component and the overall GCD computation. Layout designs were checked for design rule and layout versus schematic errors. Power and area estimates are provided based on transistor counts and simulated latency. The GCD circuit was designed using a 0.8um CMOS process and has an estimated area of 0.6412mm^2 and power consumption of 13.32mW at a clock frequency of 240MHz.

Uploaded by

vishalideepak1324
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Greatest Common Divisor Circuit Design

ECE261 CMOS VLSI Design

Team Member

Chao Chen Jae Shik Lim

Lei Kong Lingzhao Xie


Agenda

Quick Review and Block Diagram


zQuick
zModule Schematics & Digital Simulation
zSystem Simulation & Layout DRC, LVS Check
zCritical path & Area estimation, Power
Consumption
Brief Introduction
zIn mathematics, the greatest common divisor
(gcd) is the largest positive integer that divides
the numbers without a remainder.
zIn our design, a gcd(a,b) function is presented,
which returns the greatest common divisor
(gcd).
zFor example
example, gcd(1,10)
gcd(1 10) returns 1
1, while
gcd(12,9) returns 3.
P i i l ffor F
Principle Fastt GCD

00 01 10 11

00 00 00 00 00

01 00 01 01 01

10 00 01 10 01

11 00 01 01 11
Computation Circuit

a=b
a[3,0]
[ , ] a>b
Comparator
a<b
b[3,0]
[ , ] Output
MUX a
a
MUX

Selector GCD
Matrix
b
MUX
Schematics for Comparator
p
Digital Simulation for Comparator
a=7
a=10

b=7
b 7
b=7

a=b “0” a=b “1”


a>b “1”
1 a>b
b “0”
Schematics for Selector Array
Schematic for Selector Array
y
Digital Sim for Selector Array

10

5
16-bit selector schematic
Schematics for 2
2-digit
digit MUX
Digital Sim for 2-digit
2 digit MUX
When SEL Signal
g is “0”, When SEL Signal is “1”,
select IN0 select IN1
System Schematic
Digital Sim of GCD System
Digital Sim of GCD System
16-bit selector DRC Result
16-bit selector LVS Result
Selector DRC Result
Selector LVS Result
Adder DRC Result
Adder LVS Result
Comparator
p DRC Result
Comparator
p LVS Result
Top-level
p DRC Result
Top-level
p LVS Result
Floor Plan
z Top level floor plan of layout design

Selector Selector
Array Array
C
Comparator

Selector Selector
Array Array
Floor Plan
Top level floor plan of layout design
Updated
d d area estimations
i i
z Number of estimated transistor ≈ 6422

Inverter = 1033(2/ea) XOR = 8(8/ea)

Transmission Gate = 2048(2/ea)

NAND2 = 36(4/ea) NAND3 = 4(6/ea)

NAND4 = 1(8/ea)

Area per transistor: 40 λ*12 λ(λ is 0.4μm in 0.8 μm technology)

z Total estimated Area = 6422 * 40 λ*12 λ * 130% =0.6412mm^2


Power estimation
z Dynamic Power Consumption

z Assumption

system clock frequency f

activityy factor α = 0.1

no short circuit current (rising and fall time assumed equal)

P = α ⋅ C ⋅ VDD
2
⋅f

0 1 ⋅ [ 6422 ⋅ (12λ ) ⋅ (0.8


= 0.1 (0 8μ m / 2λ ) ⋅ (2 fF / μ m) ] ⋅ 32 ⋅ f
= 0.0555mW / MHz × f
Power estimation
Using the simulated latency
latency, maximum operational frequency
can be estimated.

z Maximum frequency = 1 / total latency

= 1/ 4.2ns = 240 MHz

P = α ⋅ C ⋅ VDD
2
⋅f
= 0.1 ⋅ [ 6422 ⋅ (12λ ) ⋅ (0.8μ m / 2λ ) ⋅ (2 fF / μ m) ] ⋅ 32 ⋅ f
= 0.0555
0 0555mW MH × 240 MH
W / MHz MHz
= 13.32mW
Latency Calculation
z From analog simulation, we measure latency in critical
path

p
z Comparator latencyy = 3.2ns

Selector matrix latency = 1.0 ns

The total latency = 3.2ns + 1.0ns

= 4.2ns
Latencyy Calculation
Latencyy Calculation
Thank you

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