LSM6DS33

iNEMO inertial module:

always-on 3D accelerometer and 3D gyroscope
Datasheet - production data

Description
The LSM6DS33 is a system-in-package featuring a 3D
digital accelerometer and a 3D digital gyroscope
performing at 1.25 mA (up to 1.6 kHz ODR) in high-
performance mode and enabling always-on low-power
features for an optimal motion experience for the
LGA-16L (3 x 3 x 0.86 mm) typ. consumer.
The LSM6DS33 supports main OS requirements,
offering real, virtual and batch sensors with 8 kbyte for
Features dynamic data batching.
 Power consumption: 0.9 mA in combo normal mode ST’s family of MEMS sensor modules leverages the
and 1.25 mA in combo high-performance mode up to robust and mature manufacturing processes already
1.6 kHz. used for the production of micromachined
 “Always-on” experience with low power accelerometers and gyroscopes.
consumption for both accelerometer and gyroscope The various sensing elements are manufactured using
 Smart FIFO up to 8 kbyte based on features set specialized micromachining processes, while the IC
 Compliant with Android K and L interfaces are developed using CMOS technology that
allows the design of a dedicated circuit which is
 ±2/±4/±8/±16 g full scale trimmed to better match the characteristics of the
 ±125/±250/±500/±1000/±2000 dps full scale sensing element.
 Analog supply voltage: 1.71 V to 3.6 V The LSM6DS33 has a full-scale acceleration range of
 Independent IOs supply (1.62 V) ±2/±4/±8/±16 g and an angular rate range of
 Compact footprint, 3 mm x 3 mm x 0.86 mm ±125/±250/±500/±1000/±2000 dps.
 SPI/I2C serial interface with main processor data High robustness to mechanical shock makes the
synchronization feature LSM6DS33 the preferred choice of system designers
 Embedded temperature sensor for the creation and manufacturing of reliable products.
 ECOPACK®, RoHS and “Green” compliant The LSM6DS33 is available in a plastic land grid array
(LGA) package.

Applications
Table 1. Device summary
 Pedometer, step detector and step counter
Temp.
 Significant motion and tilt functions Part number Package Packing
range [°C]
 Indoor navigation
LSM6DS33 -40 to +85 Tray
 Tap and double-tap detection LGA-16L
(3 x 3 x 0.86 mm) Tape &
 IoT and connected devices LSM6DS33TR -40 to +85
Reel
 Intelligent power saving for handheld devices
 Vibration monitoring and compensation
 Free-fall detection
 6D orientation detection

September 2017 DocID027423 Rev 6 1/78

This is information on a product in full production. www.st.com
Contents LSM6DS33

Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Tilt detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.2 I2C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6.2 Zero-g and zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 Accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4.3 Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4.4 Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4.5 Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4.6 FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4.7 Filter block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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6.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2.3 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1 LSM6DS33 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2 Pin compatibility with LSM6DS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1 FUNC_CFG_ACCESS (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2 FIFO_CTRL1 (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.3 FIFO_CTRL2 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.4 FIFO_CTRL3 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.5 FIFO_CTRL4 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.6 FIFO_CTRL5 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.7 ORIENT_CFG_G (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.8 INT1_CTRL (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.9 INT2_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.10 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.11 CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.12 CTRL2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.13 CTRL3_C (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.14 CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.15 CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.16 CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.17 CTRL7_G (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.18 CTRL8_XL (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.19 CTRL9_XL (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.20 CTRL10_C (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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9.21 WAKE_UP_SRC (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.22 TAP_SRC (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.23 D6D_SRC (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.24 STATUS_REG (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.25 OUT_TEMP_L (20h), OUT_TEMP(21h) . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.26 OUTX_L_G (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.27 OUTX_H_G (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.28 OUTY_L_G (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.29 OUTY_H_G (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.30 OUTZ_L_G (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.31 OUTZ_H_G (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.32 OUTX_L_XL (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.33 OUTX_H_XL (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.34 OUTY_L_XL (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.35 OUTY_H_XL (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.36 OUTZ_L_XL (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.37 OUTZ_H_XL (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.38 FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.39 FIFO_STATUS2 (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.40 FIFO_STATUS3 (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.41 FIFO_STATUS4 (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.42 FIFO_DATA_OUT_L (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.43 FIFO_DATA_OUT_H (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.44 TIMESTAMP0_REG (40h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.45 TIMESTAMP1_REG (41h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.46 TIMESTAMP2_REG (42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.47 STEP_TIMESTAMP_L (49h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.48 STEP_TIMESTAMP_H (4Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.49 STEP_COUNTER_L (4Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.50 STEP_COUNTER_H (4Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.51 FUNC_SRC (53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.52 TAP_CFG (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.53 TAP_THS_6D (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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9.54 INT_DUR2 (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.55 WAKE_UP_THS (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.56 WAKE_UP_DUR (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.57 FREE_FALL (5Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.58 MD1_CFG (5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.59 MD2_CFG (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10 Embedded functions register mapping . . . . . . . . . . . . . . . . . . . . . . . . . 70

11 Embedded functions registers description . . . . . . . . . . . . . . . . . . . . . 71

11.1 PEDO_THS_REG (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.2 SM_THS (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.3 PEDO_DEB_REG (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.4 STEP_COUNT_DELTA (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

12 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

13 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
13.1 LGA-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
13.2 LGA-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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List of tables LSM6DS33

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. SPI slave timing values (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. I2C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 30
Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 30
Table 16. Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. FUNC_CFG_ACCESS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. FUNC_CFG_ACCESS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19. FIFO_CTRL1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. FIFO_CTRL1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. FIFO_CTRL2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. FIFO_CTRL2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 23. FIFO_CTRL3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 24. FIFO_CTRL3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 25. Gyro FIFO decimation setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 26. Accelerometer FIFO decimation setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 27. FIFO_CTRL4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 28. FIFO_CTRL4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 29. Third FIFO data set decimation setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 30. FIFO_CTRL5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 31. FIFO_CTRL5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 32. FIFO ODR selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 33. FIFO mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 34. ORIENT_CFG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 35. ORIENT_CFG_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 36. Settings for orientation of axes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 37. INT1_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 38. INT1_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 39. INT2_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 40. INT2_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 41. WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 42. CTRL1_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 43. CTRL1_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 44. Accelerometer ODR register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 45. BW and ODR (high-performance mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 46. CTRL2_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 47. CTRL2_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 48. Gyroscope ODR configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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Table 49. CTRL3_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 50. CTRL3_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 51. CTRL4_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 52. CTRL4_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 53. CTRL5_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 54. CTRL5_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 55. Output registers rounding pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 56. Angular rate sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 57. Linear acceleration sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 58. CTRL6_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 59. CTRL6_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 60. CTRL7_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 61. CTRL7_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 62. Gyroscope high-pass filter mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 63. CTRL8_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 64. CTRL8_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 65. Accelerometer slope and high-pass filter selection and cutoff frequency . . . . . . . . . . . . . . 53
Table 66. CTRL9_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 67. CTRL9_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 68. CTRL10_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 69. CTRL10_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 70. WAKE_UP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 71. WAKE_UP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 72. TAP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 73. TAP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 74. D6D_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 75. D6D_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 76. STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 77. STATUS_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 78. OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 79. OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 80. OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 81. OUTX_L_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 82. OUTX_L_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 83. OUTX_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 84. OUTX_H_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 85. OUTY_L_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 86. OUTY_L_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 87. OUTY_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 88. OUTY_H_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 89. OUTZ_L_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 90. OUTZ_L_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 91. OUTZ_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 92. OUTZ_H_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 93. OUTX_L_XL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 94. OUTX_L_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 95. OUTX_H_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 96. OUTX_H_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 97. OUTY_L_XL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 98. OUTY_L_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 99. OUTY_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 100. OUTY_H_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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List of tables LSM6DS33

Table 101. OUTZ_L_XL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 102. OUTZ_L_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 103. OUTZ_H_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 104. OUTZ_H_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 105. FIFO_STATUS1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 106. FIFO_STATUS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 107. FIFO_STATUS2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 108. FIFO_STATUS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 109. FIFO_STATUS3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 110. FIFO_STATUS3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 111. FIFO_STATUS4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 112. FIFO_STATUS4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 113. FIFO_DATA_OUT_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 114. FIFO_DATA_OUT_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 115. FIFO_DATA_OUT_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 116. FIFO_DATA_OUT_H register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 117. TIMESTAMP0_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 118. TIMESTAMP0_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 119. TIMESTAMP1_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 120. TIMESTAMP1_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 121. TIMESTAMP2_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 122. TIMESTAMP2_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 123. STEP_TIMESTAMP_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 124. STEP_TIMESTAMP_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 125. STEP_TIMESTAMP_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 126. STEP_TIMESTAMP_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 127. STEP_COUNTER_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 128. STEP_COUNTER_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 129. STEP_COUNTER_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 130. STEP_COUNTER_H register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 131. FUNC_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 132. FUNC_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 133. TAP_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 134. TAP_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 135. TAP_THS_6D register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 136. TAP_THS_6D register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 137. Threshold for D4D/D6D function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 138. INT_DUR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 139. INT_DUR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 140. WAKE_UP_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 141. WAKE_UP_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 142. WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 143. WAKE_UP_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 144. FREE_FALL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 145. FREE_FALL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 146. Threshold for free-fall function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 147. MD1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 148. MD1_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 149. MD2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 150. MD2_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 151. Registers address map - embedded functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 152. PEDO_THS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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LSM6DS33 List of tables

Table 153. PEDO_THS_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 154. SM_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 155. SM_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 156. PEDO_DEB_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 157. PEDO_DEB_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 158. STEP_COUNT_DELTA register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 159. STEP_COUNT_DELTA register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 160. Reel dimensions for carrier tape of LGA-16 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 161. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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List of figures LSM6DS33

List of figures

Figure 1. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. SPI slave timing diagram (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. Accelerometer chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 5. Accelerometer composite filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 6. Gyroscope chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Read and write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8. SPI read protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. Multiple byte SPI read protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . . . . . . . . 32
Figure 10. SPI write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Multiple byte SPI write protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. SPI read protocol in 3-wire mode (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. LSM6DS33 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Schematic 1 (pin 15 connected to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. Schematic 2 (pin 15 connected to VDD, Vdd_IO = VDD). . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16. LGA 3x3x0.86 16L package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 17. Carrier tape information for LGA-16 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 18. LGA-16 package orientation in carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 19. Reel information for carrier tape of LGA-16 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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LSM6DS33 Overview

1 Overview

The LSM6DS33 is a system-in-package featuring a high-performance 3-axis digital

accelerometer and 3-axis digital gyroscope.
The integrated power-efficient modes are able to reduce the power consumption down to
1.25 mA in high-performance mode, combining always-on low-power features with superior
sensing precision for an optimal motion experience for the consumer thanks to ultra-low
noise performance for both the gyroscope and accelerometer.
The LSM6DS33 delivers best-in-class motion sensing that can detect orientation and
gestures in order to empower application developers and consumers with features and
capabilities that are more sophisticated than simply orienting their devices to portrait and
landscape mode.
The event-detection interrupts enable efficient and reliable motion tracking and contextual
awareness, implementing hardware recognition of free-fall events, 6D orientation, tap and
double-tap sensing, activity or inactivity, and wakeup events.
The LSM6DS33 supports main OS requirements, offering real, virtual and batch mode
sensors. In addition, the LSM6DS33 can efficiently run the sensor-related features specified
in Android, saving power and enabling faster reaction time. In particular, the LSM6DS33 has
been designed to implement hardware features such as significant motion, tilt, pedometer
functions, and timestamping.
Up to 8 kbyte of FIFO with dynamic allocation of significant data (i.e. sensors, temperature,
step counter and timestamp) allows overall power saving of the system.
Like the entire portfolio of MEMS sensor modules, the LSM6DS33 leverages the robust and
mature in-house manufacturing processes already used for the production of
micromachined accelerometers and gyroscopes. The various sensing elements are
manufactured using specialized micromachining processes, while the IC interfaces are
developed using CMOS technology that allows the design of a dedicated circuit which is
trimmed to better match the characteristics of the sensing element.
The LSM6DS33 is available in a small plastic land grid array (LGA) package of
3 x 3 x 0.86 mm to address ultra-compact solutions.

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Embedded low-power features LSM6DS33

2 Embedded low-power features

The LSM6DS33 has been designed to be fully compliant with Android, featuring the
following on-chip functions:
 8 kbyte data buffering
– 100% efficiency with flexible configurations and partitioning
– possibility to store timestamp
 Event-detection interrupts (fully configurable):
– free-fall
– wakeup
– 6D orientation
– tap and double-tap sensing
– activity / inactivity recognition
 Specific IP blocks with negligible power consumption and high-performance:
– pedometer functions: step detector and step counters
– tilt (Android compliant, refer to Section 2.1: Tilt detection for additional info
– significant motion (Android compliant)

2.1 Tilt detection

The tilt function helps to detect activity change and has been implemented in hardware
using only the accelerometer to achieve both the targets of ultra-low power consumption
and robustness during the short duration of dynamic accelerations.
It is based on a trigger of an event each time the device's tilt changes by an angle greater
than 35 degrees from the start position.
The tilt function can be used with different scenarios, for example:
a) Trigger when phone is in a front pants pocket and the user goes from sitting to
standing or standing to sitting;
b) Doesn’t trigger when phone is in a front pants pocket and the user is walking,
running or going upstairs.

12/78 DocID027423 Rev 6

LSM6DS33 Pin description

3 Pin description

Figure 1. Pin connections

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In the LSM6DS33 an I2C slave interface or SPI (3- and 4-wire) serial interface is available.

DocID027423 Rev 6 13/78

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Pin description LSM6DS33

Table 2. Pin description

Pin# Name Function

1 VDDIO(1) Power supply for I/O pins

I2C serial clock (SCL)
2 SCL
SPI serial port clock (SPC)
I2C serial data (SDA)
3 SDA SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SPI 4-wire interface serial data output (SDO)
4 SDO/SA0
I2C least significant bit of the device address (SA0)
I2C/SPI mode selection
5 CS (1: SPI idle mode / I2C communication enabled;
0: SPI communication mode / I2C disabled)
6 INT2 Programmable interrupt 2 (INT2) / Data enabled (DEN)
7 INT1 Programmable interrupt 1
8 RES Reserved, connect to GND
9 RES Reserved, connect to GND
10 RES Reserved, connect to GND
11 RES Reserved, connect to GND
12 GND 0 V supply
13 GND 0 V supply
(2)
14 NC Leave unconnected
15 RES Reserved, connect to GND
16 VDD(3) Power supply
1. Recommended 100 nF filter capacitor.
2. Leave pin electrically unconnected and soldered to PCB.
3. Recommended 100 nF capacitor.

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LSM6DS33 Module specifications

4 Module specifications

4.1 Mechanical characteristics

@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.

Table 3. Mechanical characteristics

Symbol Parameter Test conditions Min. Typ.(1) Max. Unit

±2

Linear acceleration measurement ±4

LA_FS g
range ±8
±16
±125
±250
Angular rate
G_FS ±500 dps
measurement range
±1000
±2000
FS = ±2 0.061
FS = ±4 0.122
LA_So Linear acceleration sensitivity mg/LSB
FS = ±8 0.244
FS = ±16 0.488
FS = ±125 4.375
FS = ±250 8.75
G_So Angular rate sensitivity FS = ±500 17.50 mdps/LSB
FS = ±1000 35
FS = ±2000 70
(2)
G_So% Sensitivity tolerance at component level ±1.5 %
Linear acceleration sensitivity from -40° to +85°
LA_SoDr ±1 %
change vs. temperature(3) delta from T=25°
Angular rate sensitivity change from -40° to +85°
G_SoDr ±1.5 %
vs. temperature(3) delta from T=25°
Linear acceleration typical zero-g
LA_TyOff ±40 mg
level offset accuracy(4)
Angular rate typical zero-rate
G_TyOff ±10 dps
level(4)
Linear acceleration zero-g level
LA_OffDr ±0.5 mg/ °C
change vs. temperature(3)
Angular rate typical zero-rate
G_OffDr ±0.05 dps/°C
level change vs. temperature(3)
Rn Rate noise density 7 mdps/Hz
FS= ±2 g
An Acceleration noise density 90 μg/Hz
ODR = 104 Hz

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Module specifications LSM6DS33

Table 3. Mechanical characteristics (continued)

Symbol Parameter Test conditions Min. Typ.(1) Max. Unit

12.5
26
52
104
Linear acceleration output data 208
LA_ODR
rate 416
833
1666
3332
Hz
6664
12.5
26
52
104
G_ODR Angular rate output data rate
208
416
833
1666
Top Operating temperature range -40 +85 °C
1. Typical specifications are not guaranteed.
2. Sensitivity values after factory calibration test and trimming.
3. Measurements are performed in a uniform temperature setup.
4. Values after soldering.

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LSM6DS33 Module specifications

4.2 Electrical characteristics

@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.

Table 4. Electrical characteristics

Symbol Parameter Test conditions Min. Typ.(1) Max. Unit

Vdd Supply voltage 1.71 1.8 3.6 V

Vdd_IO Power supply for I/O 1.62 Vdd+0.1 V
Gyroscope and accelerometer in
IddHP up to ODR = 1.6 kHz 1.25 mA
high-performance mode
Gyroscope and accelerometer in
IddNM ODR = 208 Hz 0.9 mA
normal mode
Gyroscope and accelerometer in
IddLP ODR = 12.5 Hz 0.42 mA
low-power mode
Accelerometer current consumption
LA_IddHP up to ODR = 1.6 kHz 240 μA
in high-performance mode
Accelerometer current consumption
LA_IddNM ODR = 104 Hz 70 μA
in normal mode
Accelerometer current consumption
LA_IddLM ODR = 12.5 Hz 24 μA
in low-power mode
Gyroscope and accelerometer in
IddPD 6 μA
power down
Top Operating temperature range -40 +85 °C
1. Typical specifications are not guaranteed.

For details related to the LSM6DS33 operating modes, refer to 5.2: Gyroscope power
modes and 5.3: Accelerometer power modes.

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Module specifications LSM6DS33

4.3 Temperature sensor characteristics

@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.

Table 5. Temperature sensor characteristics

Symbol Parameter Test condition Min. Typ.(1) Max. Unit

TODR Temperature refresh rate 52 Hz

(2)
Toff Temperature offset -15 +15 °C
TSen Temperature sensitivity 16 LSB/°C
Temperature stabilization
TST 500 μs
time(3)
T_ADC_res Temperature ADC resolution 12 bit
Top Operating temperature range -40 +85 °C
1. Typical specifications are not guaranteed.
2. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
3. Time from power ON bit to valid data based on characterization data.

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LSM6DS33 Module specifications

4.4 Communication interface characteristics

4.4.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 6. SPI slave timing values (in mode 3)

Value(1)
Symbol Parameter Unit
Min Max

tc(SPC) SPI clock cycle 100 ns

fc(SPC) SPI clock frequency 10 MHz
tsu(CS) CS setup time 5
th(CS) CS hold time 20
tsu(SI) SDI input setup time 5
th(SI) SDI input hold time 15 ns
tv(SO) SDO valid output time 50
th(SO) SDO output hold time 5
tdis(SO) SDO output disable time 50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production

Figure 2. SPI slave timing diagram (in mode 3)

Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output
ports.

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Module specifications LSM6DS33

4.4.2 I2C - inter-IC control interface

Subject to general operating conditions for Vdd and Top.

Table 7. I2C slave timing values

I2C Standard mode(1) I2C Fast mode (1)
Symbol Parameter Unit
Min Max Min Max
f(SCL) SCL clock frequency 0 100 0 400 kHz
tw(SCLL) SCL clock low time 4.7 1.3
μs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100 ns
th(SDA) SDA data hold time 0 3.45 0 0.9 μs
th(ST) START condition hold time 4 0.6
Repeated START condition
tsu(SR) 4.7 0.6
setup time
μs
tsu(SP) STOP condition setup time 4 0.6
Bus free time between STOP
tw(SP:SR) 4.7 1.3
and START condition
1. Data based on standard I2C protocol requirement, not tested in production.

Figure 3. I2C slave timing diagram

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Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

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LSM6DS33 Module specifications

4.5 Absolute maximum ratings

Stresses above those listed as “Absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 8. Absolute maximum ratings

Symbol Ratings Maximum value Unit

Vdd Supply voltage -0.3 to 4.8 V

TSTG Storage temperature range -40 to +125 °C
Sg Acceleration g for 0.2 ms 10,000 g
ESD Electrostatic discharge protection (HBM) 2 kV
Input voltage on any control pin
Vin -0.3 to Vdd_IO +0.3 V
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)

Note: Supply voltage on any pin should never exceed 4.8 V.

This device is sensitive to mechanical shock, improper handling can cause

permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can
cause permanent damage to the part.

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Module specifications LSM6DS33

4.6 Terminology

4.6.1 Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration
to the device. Because the sensor can measure DC accelerations, this can be done easily
by pointing the selected axis towards the ground, noting the output value, rotating the
sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing
so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This
value changes very little over temperature and over time. The sensitivity tolerance describes
the range of sensitivities of a large number of sensors.
An angular rate gyroscope is device that produces a positive-going digital output for
counterclockwise rotation around the axis considered. Sensitivity describes the gain of the
sensor and can be determined by applying a defined angular velocity to it. This value
changes very little over temperature and time.

4.6.2 Zero-g and zero-rate level

Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output
signal from the ideal output signal if no acceleration is present. A sensor in a steady state on
a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will
measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content
of OUT registers 00h, data expressed as 2’s complement number). A deviation from the
ideal value in this case is called zero-g offset.
Offset is to some extent a result of stress to MEMS sensor and therefore the offset can
slightly change after mounting the sensor onto a printed circuit board or exposing it to
extensive mechanical stress. Offset changes little over temperature, see “Linear
acceleration zero-g level change vs. temperature” in Table 3. The zero-g level tolerance
(TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors.
Zero-rate level describes the actual output signal if there is no angular rate present. The
zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor
and therefore the zero-rate level can slightly change after mounting the sensor onto a
printed circuit board or after exposing it to extensive mechanical stress. This value changes
very little over temperature and time.

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LSM6DS33 Functionality

5 Functionality

5.1 Operating modes

The LSM6DS33 has three operating modes available:
 only accelerometer active and gyroscope in power-down
 only gyroscope active and accelerometer in power-down
 both accelerometer and gyroscope sensors active with independent ODR
The accelerometer is activated from power down by writing ODR_XL[3:0] in CTRL1_XL
(10h) while the gyroscope is activated from power-down by writing ODR_G[3:0] in
CTRL2_G (11h). For combo mode the ODRs are totally independent.

5.2 Gyroscope power modes

In the LSM6DS33, the gyroscope can be configured in four different operating modes:
power-down, low-power, normal mode and high-performance mode. The operating mode
selected depends on the value of the G_HM_MODE bit in CTRL7_G (16h). If G_HM_MODE
is set to ‘0’, high-performance mode is valid for all ODRs (from 12.5 Hz up to 1.6 kHz).
To enable the low-power and normal mode, the G_HM_MODE bit has to be set to ‘1’. Low-
power mode is available for lower ODR (12.5, 26, 52 Hz) while normal mode is available for
ODRs equal to 104 and 208 Hz.

5.3 Accelerometer power modes

In the LSM6DS33, the accelerometer can be configured in four different operating modes:
power-down, low-power, normal mode and high-performance mode. The operating mode
selected depends on the value of the XL_HM_MODE bit in CTRL6_C (15h). If
XL_HM_MODE is set to ‘0’, high-performance mode is valid for all ODRs (from 12.5 Hz up
to 6.66 kHz).
To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to ‘1’. Low-
power mode is available for lower ODRs (12.5, 26, 52 Hz) while normal mode is available
for ODRs equal to 104 and 208 Hz.

5.4 FIFO
The presence of a FIFO allows consistent power saving for the system since the host
processor does not need continuously poll data from the sensor, but it can wake up only
when needed and burst the significant data out from the FIFO.
LSM6DS33 embeds 8 kbytes data FIFO to store the following data:
 gyroscope
 accelerometer
 step counter and timestamp
 temperature

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Functionality LSM6DS33

Writing data in the FIFO can be configured to be triggered by the:

- accelerometer/gyroscope data-ready signal; in which case the ODR must be lower than or
equal to both the accelerometer and gyroscope ODRs;
- step detection signal.
In addition, each data can be stored at a decimated data rate compared to FIFO ODR and it
is configurable by the user, setting the registers FIFO_CTRL3 (08h) and FIFO_CTRL4
(09h). The available decimation factors are 2, 3, 4, 8, 16, 32.
Programmable FIFO threshold can be set in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)
using the FTH [11:0] bits.
To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2
(3Bh), FIFO_STATUS3 (3Ch), FIFO_STATUS4 (3Dh)) can be read to detect FIFO overrun
events, FIFO full status, FIFO empty status, FIFO threshold status and the number of
unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2
pads of these status events, the configuration can be set in INT1_CTRL (0Dh) and
INT2_CTRL (0Eh).
FIFO buffer can be configured according to five different modes:
– Bypass mode
– FIFO mode
– Continuous mode
– Continuous-to-FIFO mode
– Bypass-to-continuous mode
Each mode is selected by the FIFO_MODE_[2:0] in FIFO_CTRL5 (0Ah) register. To
guarantee the correct acquisition of data during the switching into and out of FIFO mode,
the first sample acquired must be discarded.

5.4.1 Bypass mode

In Bypass mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 000), the FIFO is not
operational and it remains empty.
Bypass mode is also used to reset the FIFO when in FIFO mode.

5.4.2 FIFO mode

In FIFO mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 001) data from the output
channels are stored in the FIFO until it is full.
To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL5 (0Ah)
(FIFO_MODE_[2:0]) to '000' After this reset command, it is possible to restart FIFO mode by
writing FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0]) to '001'.
FIFO buffer memorizes up to 4096 samples of 16 bits each but the depth of the FIFO can be
resized by setting the FTH [11:0] bits in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h). If the
STOP_ON_FTH bit in CTRL4_C (13h) is set to '1', FIFO depth is limited up to FTH [11:0]
bits in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h).

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LSM6DS33 Functionality

5.4.3 Continuous mode

Continuous mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 110) provides a continuous
FIFO update: as new data arrives, the older data is discarded.
A FIFO threshold flag FIFO_STATUS2 (3Bh)(FTH) is asserted when the number of unread
samples in FIFO is greater than or equal to FIFO_CTRL1 (06h) and FIFO_CTRL2
(07h)(FTH [11:0]).
It is possible to route FIFO_STATUS2 (3Bh) (FTH) to the INT1 pin by writing in register
INT1_CTRL (0Dh) (INT1_FTH) = ‘1’ or to the INT2 pin by writing in register INT2_CTRL
(0Eh) (INT2_FTH) = ‘1’.
A full-flag interrupt can be enabled, INT1_CTRL (0Dh) (INT_ FULL_FLAG) = '1', in order to
indicate FIFO saturation and eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and
the OVER_RUN flag in FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of
unread samples available in FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)
(DIFF_FIFO[11:0]).

5.4.4 Continuous-to-FIFO mode

In Continuous-to-FIFO mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 011), FIFO
behavior changes according to the trigger event detected in one of the following interrupt
registers FUNC_SRC (53h), TAP_SRC (1Ch), WAKE_UP_SRC (1Bh) and D6D_SRC
(1Dh).
When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.
When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.

5.4.5 Bypass-to-Continuous mode

In Bypass-to-Continuous mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = '100'), data
measurement storage inside FIFO operates in Continuous mode when selected triggers in
one of the following interrupt registers FUNC_SRC (53h), TAP_SRC (1Ch),
WAKE_UP_SRC (1Bh) and D6D_SRC (1Dh) are equal to '1', otherwise FIFO content is
reset (Bypass mode).

5.4.6 FIFO reading procedure

The data stored in FIFO are accessible from dedicated registers (FIFO_DATA_OUT_L
(3Eh) and FIFO_DATA_OUT_H (3Fh)) and each FIFO sample is composed of 16 bits.
All FIFO status registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh), FIFO_STATUS3
(3Ch), FIFO_STATUS4 (3Dh)) can be read at the start of a reading operation, minimizing
the intervention of the application processor.
Saving data in the FIFO buffer is organized in four FIFO data sets consisting of 6 bytes
each:
The 1st FIFO data set is reserved for gyroscope data;
The 2nd FIFO data set is reserved for accelerometer data;

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Functionality LSM6DS33

5.4.7 Filter block diagrams

Figure 4. Accelerometer chain

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LSM6DS33 Functionality

Figure 6. Gyroscope chain

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DocID027423 Rev 6 27/78

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Digital interfaces LSM6DS33

6 Digital interfaces

The registers embedded inside the LSM6DS33 may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode. The device is compatible with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the
CS line must be tied high (i.e connected to Vdd_IO).

Table 9. Serial interface pin description

Pin name Pin description

SPI enable
CS I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled;
0: SPI communication mode / I2C disabled)
I2C Serial Clock (SCL)
SCL/SPC
SPI Serial Port Clock (SPC)
I2C Serial Data (SDA)
SDA/SDI/SDO SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
SDO/SA0
I2C less significant bit of the device address

6.1 I2C serial interface

The LSM6DS33 I2C is a bus slave. The I2C is employed to write the data to the registers,
whose content can also be read back.
The relevant I2C terminology is provided in the table below.

Table 10. I2C terminology

Term Description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a
Master
transfer
Slave The device addressed by the master

There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistors. When the bus is free, both the lines are high.
The I2C interface is implemeted with fast mode (400 kHz) I2C standards as well as with the
standard mode.
In order to disable the I2C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).

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LSM6DS33 Digital interfaces

6.1.1 I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
The Slave ADdress (SAD) associated to the LSM6DS33 is 110101xb. The SDO/SA0 pin
can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is
connected to the supply voltage, LSb is ‘1’ (address 1101011b); else if the SDO/SA0 pin is
connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to
connect and address two different inertial modules to the same I2C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver
which has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the LSM6DS33 behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted.
The increment of the address is configured by CTRL3_C (12h) (IF_INC).
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the master will transmit to the slave with direction unchanged. Table 11 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 11. SAD+Read/Write patterns

Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W

Read 110101 0 1 11010101 (D5h)

Write 110101 0 0 11010100 (D4h)

Read 110101 1 1 11010111 (D7h)

Write 110101 1 0 11010110 (D6h)

Table 12. Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA SP
Slave SAK SAK SAK

Table 13. Transfer when master is writing multiple bytes to slave

Master ST SAD + W SUB DATA DATA SP
Slave SAK SAK SAK SAK

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Digital interfaces LSM6DS33

Table 14. Transfer when master is receiving (reading) one byte of data from slave
Master ST SAD + W SUB SR SAD + R NMAK SP
Slave SAK SAK SAK DATA

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
Slave SAK SAK SAK DATA DATA DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.

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LSM6DS33 Digital interfaces

6.2 SPI bus interface

The LSM6DS33 SPI is a bus slave. The SPI allows writing and reading the registers of the
device.
The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO.

Figure 7. Read and write protocol (in mode 3)

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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are, respectively, the serial port data input and output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the
CTRL3_C (12h) (IF_INC) bit is ‘0’, the address used to read/write data remains the same for
every block. When the CTRL3_C (12h) (IF_INC) bit is ‘1’, the address used to read/write
data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.

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Digital interfaces LSM6DS33

6.2.1 SPI read

Figure 8. SPI read protocol (in mode 3)

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The SPI Read command is performed with 16 clock pulses. A multiple byte read command
is performed by adding blocks of 8 clock pulses to the previous one.

bit 0: READ bit. The value is 1.

bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-...: data DO(...-8). Further data in multiple byte reads.

Figure 9. Multiple byte SPI read protocol (2-byte example) (in mode 3)

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LSM6DS33 Digital interfaces

6.2.2 SPI write

Figure 10. SPI write protocol (in mode 3)

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The SPI Write command is performed with 16 clock pulses. A multiple byte write command
is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1 -7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb
first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.

Figure 11. Multiple byte SPI write protocol (2-byte example) (in mode 3)

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Digital interfaces LSM6DS33

6.2.3 SPI read in 3-wire mode

A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial
interface mode selection).

Figure 12. SPI read protocol in 3-wire mode (in mode 3)

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The SPI read command is performed with 16 clock pulses:

bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.

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LSM6DS33 Application hints

7 Application hints

7.1 LSM6DS33 electrical connections

Figure 13. LSM6DS33 electrical connections

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1. Leave pin electrically unconnected and soldered to PCB.

The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1,
C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device
(common design practice).
The functionality of the device and the measured acceleration/angular rate data is
selectable and accessible through the SPI/I2C interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be
completely programmed by the user through the SPI/I2C interface.

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Application hints LSM6DS33

7.2 Pin compatibility with LSM6DS0

Figure 14. Schematic 1 (pin 15 connected to GND)

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36/78 DocID027423 Rev 6

LSM6DS33 Application hints

Figure 15. Schematic 2 (pin 15 connected to VDD, Vdd_IO = VDD)

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DocID027423 Rev 6 37/78

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Register mapping LSM6DS33

8 Register mapping

The table given below provides a list of the 8/16 bit registers embedded in the device and
the corresponding addresses.

Table 16. Registers address map

Register address
Name Type Default Comment
Hex Binary

RESERVED - 00 00000000 00000000 Reserved

Embedded
functions
FUNC_CFG_ACCESS r/w 01 00000001 00000000
configuration
register
RESERVED - 02-05 - Reserved
FIFO_CTRL1 r/w 06 00000110 00000000
FIFO_CTRL2 r/w 07 00000111 00000000
FIFO
FIFO_CTRL3 r/w 08 00001000 00000000 configuration
registers
FIFO_CTRL4 r/w 09 00001001 00000000
FIFO_CTRL5 r/w 0A 00001010 00000000
ORIENT_CFG_G r/w 0B 00001011 00000000
RESERVED - 0C 00001100 - Reserved
INT1_CTRL r/w 0D 00001101 00000000 INT1 pin control
INT2_CTRL r/w 0E 00001110 00000000 INT2 pin control
WHO_AM_I r 0F 00001111 01101001 Who I am ID
CTRL1_XL r/w 10 00010000 00000000
CTRL2_G r/w 11 00010001 00000000
CTRL3_C r/w 12 00010010 00000100
CTRL4_C r/w 13 00010011 00000000
Accelerometer
CTRL5_C r/w 14 00010100 00000000 and gyroscope
CTRL6_C r/w 15 00010101 00000000 control
registers
CTRL7_G r/w 16 00010110 00000000
CTRL8_XL r/w 17 0001 0111 00000000
CTRL9_XL r/w 18 00011000 00111000
CTRL10_C r/w 19 00011001 00111000
RESERVED - 1A 00011010 - Reserved
WAKE_UP_SRC r 1B 00011011 output
Interrupts
TAP_SRC r 1C 00011100 output
registers
D6D_SRC r 1D 00011101 output

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LSM6DS33 Register mapping

Table 16. Registers address map (continued)

Register address
Name Type Default Comment
Hex Binary

Status data
STATUS_REG r 1E 00011110 output
register
RESERVED - 1F 00011111 - Reserved
OUT_TEMP_L r 20 00100000 output Temperature
output data
OUT_TEMP_H r 21 00100001 output register
OUTX_L_G r 22 00100010 output
OUTX_H_G r 23 00100011 output
OUTY_L_G r 24 00100100 output Gyroscope
OUTY_H_G r 25 00100101 output output register

OUTZ_L_G r 26 00100110 output

OUTZ_H_G r 27 00100111 output
OUTX_L_XL r 28 00101000 output
OUTX_H_XL r 29 00101001 output
OUTY_L_XL r 2A 00101010 output Accelerometer
OUTY_H_XL r 2B 00101011 output output register

OUTZ_L_XL r 2C 00101100 output

OUTZ_H_XL r 2D 00101101 output
RESERVED - 2E-39 - Reserved
FIFO_STATUS1 r 3A 00111010 output
FIFO_STATUS2 r 3B 00111011 output FIFO status
FIFO_STATUS3 r 3C 00111100 output registers

FIFO_STATUS4 r 3D 00111101 output

FIFO_DATA_OUT_L r 3E 00111110 output FIFO data
FIFO_DATA_OUT_H r 3F 00111111 output output registers

TIMESTAMP0_REG r 40 01000000 output

Timestamp
TIMESTAMP1_REG r 41 01000001 output
output registers
TIMESTAMP2_REG r/w 42 01000010 output
RESERVED - 43-48 - Reserved
STEP_TIMESTAMP_L r 49 0100 1001 output Step counter
timestamp
STEP_TIMESTAMP_H r 4A 0100 1010 output registers
STEP_COUNTER_L r 4B 01001011 output Step counter
STEP_COUNTER_H r 4C 01001100 output output registers

RESERVED - 4D-52 - Reserved

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Register mapping LSM6DS33

Table 16. Registers address map (continued)

Register address
Name Type Default Comment
Hex Binary

Interrupt
FUNC_SRC r 53 01010011 output
register
RESERVED - 54-57 - Reserved
TAP_CFG r/w 58 01011000 00000000
TAP_THS_6D r/w 59 01011001 00000000
INT_DUR2 r/w 5A 01011010 00000000
WAKE_UP_THS r/w 5B 01011011 00000000 Interrupt
WAKE_UP_DUR r/w 5C 01011100 00000000 registers

FREE_FALL r/w 5D 01011101 00000000

MD1_CFG r/w 5E 01011110 00000000
MD2_CFG r/w 5F 01011111 00000000
RESERVED - 60-6B - Reserved

Registers marked as Reserved must not be changed. Writing to those registers may cause
permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.

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LSM6DS33 Register description

9 Register description

The device contains a set of registers which are used to control its behavior and to retrieve
linear acceleration, angular rate and temperature data. The register addresses, made up of
7 bits, are used to identify them and to write the data through the serial interface.

9.1 FUNC_CFG_ACCESS (01h)

Enable embedded functions register (r/w).

Table 17. FUNC_CFG_ACCESS register

(1)
FUNC_CFG_EN 0 0(1) 0(1) 0(1) 0(1) 0(1) 0(1)
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 18. FUNC_CFG_ACCESS register description

Enable access to the embedded functions configuration registers (1) from address
02h to 32h. Default value: 0.
FUNC_CFG_EN
(0: disable access to embedded functions configuration registers;
1: enable access to embedded functions configuration registers)
1. The embedded functions configuration registers details are available in 10: Embedded functions register
mapping and 11: Embedded functions registers description.

9.2 FIFO_CTRL1 (06h)

FIFO control register (r/w).

Table 19. FIFO_CTRL1 register

FTH_7 FTH_6 FTH_5 FTH_4 FTH_3 FTH_2 FTH_1 FTH_0

Table 20. FIFO_CTRL1 register description

FIFO threshold level setting(1). Default value: 0000 0000.

FTH_[7:0] Watermark flag rises when the number of bytes written to FIFO after the next write is
greater than or equal to the threshold level.
Minimum resolution for the FIFO is 1 LSB = 2 bytes (1 word) in FIFO
1. For a complete watermark threshold configuration, consider FTH_[11:8] in FIFO_CTRL2 (07h).

9.3 FIFO_CTRL2 (07h)

FIFO control register (r/w).

Table 21. FIFO_CTRL2 register

TIMER_PEDO TIMER_PEDO
0(1) 0(1) FTH_11 FTH10 FTH_9 FTH_8
_FIFO_EN _FIFO_DRDY
1. This bit must be set to ‘0’ for the correct operation of the device.

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Register description LSM6DS33

Table 22. FIFO_CTRL2 register description

Enable pedometer step counter and timestamp as 3rd FIFO data set. Default: 0
TIMER_PEDO
(0: disable step counter and timestamp data as 3rd FIFO data set;
_FIFO_EN
1: enable step counter and timestamp data as 3rd FIFO data set)
FIFO write mode. Default: 0
TIMER_PEDO
(0: enable write in FIFO based on XL/Gyro data-ready;
_FIFO_DRDY
1: enable write in FIFO at every step detected by step counter.)
FIFO threshold level setting(1). Default value: 0000
Watermark flag rises when the number of bytes written to FIFO after the next
FTH_[11:8]
write is greater than or equal to the threshold level.
Minimum resolution for the FIFO is 1LSB = 2 bytes (1 word) in FIFO
1. For a complete watermark threshold configuration, consider FTH_[7:0] in FIFO_CTRL1 (06h).

9.4 FIFO_CTRL3 (08h)

FIFO control register (r/w).

Table 23. FIFO_CTRL3 register

DEC_FIFO DEC_FIFO DEC_FIFO DEC_FIFO DEC_FIFO DEC_FIFO
0(1) 0(1)
_GYRO2 _GYRO1 _GYRO0 _XL2 _XL1 _XL0
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 24. FIFO_CTRL3 register description

Gyro FIFO (first data set) decimation setting. Default: 000
DEC_FIFO_GYRO [2:0]
For the configuration setting, refer to Table 25.

Accelerometer FIFO (second data set) decimation setting. Default: 000

DEC_FIFO_XL [2:0]
For the configuration setting, refer to Table 26.

Table 25. Gyro FIFO decimation setting

DEC_FIFO_GYRO [2:0] Configuration

000 Gyro sensor not in FIFO

001 No decimation
010 Decimation with factor 2
011 Decimation with factor 3
100 Decimation with factor 4
101 Decimation with factor 8
110 Decimation with factor 16
111 Decimation with factor 32

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LSM6DS33 Register description

Table 26. Accelerometer FIFO decimation setting

DEC_FIFO_XL [2:0] Configuration

000 Accelerometer sensor not in FIFO

001 No decimation
010 Decimation with factor 2
011 Decimation with factor 3
100 Decimation with factor 4
101 Decimation with factor 8
110 Decimation with factor 16
111 Decimation with factor 32

9.5 FIFO_CTRL4 (09h)

FIFO control register (r/w).

Table 27. FIFO_CTRL4 register

ONLY_HIGH TIMER_PEDO TIMER_PEDO TIMER_PEDO
0(1) 0(1) 0(1) 0(1)
_DATA _DEC_FIFO2 _DEC_FIFO1 _DEC_FIFO1
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 28. FIFO_CTRL4 register description

8-bit data storage in FIFO. Default: 0
ONLY_HIGH_DATA (0: disable MSByte only memorization in FIFO for XL and Gyro;
1: enable MSByte only memorization in FIFO for XL and Gyro in FIFO)

Third FIFO data set decimation setting. Default: 000

TIMER_PEDO_DEC_ For the configuration setting, refer to Table 29.
FIFO[2:0] These bits are used when the bit TIMER_PEDO_FIFO_EN is set to ‘1’ in
FIFO_CTRL2 (07h)

Table 29. Third FIFO data set decimation setting

TIMER_PEDO_DEC_FIFO[2:0] Configuration

000 Third FIFO data set not in FIFO

001 No decimation
010 Decimation with factor 2
011 Decimation with factor 3
100 Decimation with factor 4
101 Decimation with factor 8
110 Decimation with factor 16
111 Decimation with factor 32

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9.6 FIFO_CTRL5 (0Ah)

FIFO control register (r/w).

Table 30. FIFO_CTRL5 register

ODR_ ODR_ ODR_ ODR_ FIFO_ FIFO_ FIFO_
0(1)
FIFO_3 FIFO_2 FIFO_1 FIFO_0 MODE_2 MODE_1 MODE_0
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 31. FIFO_CTRL5 register description

FIFO ODR selection, setting FIFO_MODE also. Default: 0000
ODR_FIFO_[3:0]
For the configuration setting, refer to Table 32
FIFO mode selection bits, setting ODR_FIFO also. Default value: 000
FIFO_MODE_[2:0]
For the configuration setting refer to Table 33

Table 32. FIFO ODR selection

ODR_FIFO_[3:0] Configuration(1)

0000 FIFO disabled

0001 FIFO ODR is set to 12.5 Hz
0010 FIFO ODR is set to 26 Hz
0011 FIFO ODR is set to 52 Hz
0100 FIFO ODR is set to 104 Hz
0101 FIFO ODR is set to 208 Hz
0110 FIFO ODR is set to 416 Hz
0111 FIFO ODR is set to 833 Hz
1000 FIFO ODR is set to 1.66 kHz
1001 FIFO ODR is set to 3.33 kHz
1010 FIFO ODR is set to 6.66 kHz
1. If the device is working at an ODR slower than the one selected, FIFO ODR is limited to that ODR value.
Moreover, these bits are effective if the TIMER_PEDO_FIFO_DRDY bit of FIFO_CTRL2 (07h) is set to 0.

Table 33. FIFO mode selection

FIFO_MODE_[2:0] Configuration mode

000 Bypass mode. FIFO disabled.

001 FIFO mode. Stops collecting data when FIFO is full.
010 Reserved
011 Continuous mode until trigger is deasserted, then FIFO mode.
100 Bypass mode until trigger is deasserted, then Continuous mode.
101 Reserved
110 Continuous mode. If the FIFO is full, the new sample overwrites the older one.
111 Reserved

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LSM6DS33 Register description

9.7 ORIENT_CFG_G (0Bh)

Angular rate sensor sign and orientation register (r/w).

Table 34. ORIENT_CFG_G register

(1) (1)
0 0 SignX_G SignY_G SignZ_G Orient_2 Orient_1 Orient_0
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 35. ORIENT_CFG_G register description

SignX_G Pitch axis (X) angular rate sign. Default value: 0
(0: positive sign; 1: negative sign)
SignY_G Roll axis (Y) angular rate sign. Default value: 0
(0: positive sign; 1: negative sign)
SignZ_G Yaw axis (Z) angular rate sign. Default value: 0
(0: positive sign; 1: negative sign)
Orient [2:0] Directional user-orientation selection. Default value: 000
For the configuration setting, refer to Table 36.

Table 36. Settings for orientation of axes

Orient [2:0] 000 001 010 011 100 101

Pitch X X Y Y Z Z
Roll Y Z X Z X Y
Yaw Z Y Z X Y X

9.8 INT1_CTRL (0Dh)

INT1 pad control register (r/w).
Each bit in this register enables a signal to be carried through INT1. The pad’s output will
supply the OR combination of the selected signals.

Table 37. INT1_CTRL register

INT1_
INT1_SIGN INT1_FULL INT1_ INT1_ INT1_ INT1_ INT1_
STEP_
_MOT _FLAG FIFO_OVR FTH BOOT DRDY_G DRDY_XL
DETECTOR

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Table 38. INT1_CTRL register description

INT1_ STEP_ Pedometer step recognition interrupt enable on INT1 pad. Default value: 0
DETECTOR (0: disabled; 1: enabled)
Significant motion interrupt enable on INT1 pad. Default value: 0
INT1_SIGN_MOT
(0: disabled; 1: enabled)
FIFO full flag interrupt enable on INT1 pad. Default value: 0
INT1_FULL_FLAG
(0: disabled; 1: enabled)
FIFO overrun interrupt on INT1 pad. Default value: 0
INT1_FIFO_OVR
(0: disabled; 1: enabled)
FIFO threshold interrupt on INT1 pad. Default value: 0
INT1_FTH
(0: disabled; 1: enabled)
Boot status available on INT1 pad. Default value: 0
INT1_ BOOT
(0: disabled; 1: enabled)
Gyroscope data-ready on INT1 pad. Default value: 0
INT1_DRDY_G
(0: disabled; 1: enabled)
Accelerometer data-ready on INT1 pad. Default value: 0
INT1_DRDY_XL
(0: disabled; 1: enabled)

9.9 INT2_CTRL (0Eh)

INT2 pad control register (r/w).
Each bit in this register enables a signal to be carried through INT2. The pad’s output will
supply the OR combination of the selected signals.

Table 39. INT2_CTRL register

INT2_
INT2_STEP INT2_STEP_ INT2_ INT2_ INT2_ INT2_ INT2_
DRDY
_DELTA COUNT_OV FULL_FLAG FIFO_OVR FTH DRDY_G DRDY_XL
_TEMP

Table 40. INT2_CTRL register description

Pedometer step recognition interrupt on delta time(1) enable on INT2 pad.
INT2_STEP_DELTA Default value: 0
(0: disabled; 1: enabled)
INT2_STEP_COUNT Step counter overflow interrupt enable on INT2 pad. Default value: 0
_OV (0: disabled; 1: enabled)
FIFO full flag interrupt enable on INT2 pad. Default value: 0
INT2_ FULL_FLAG
(0: disabled; 1: enabled)
FIFO overrun interrupt on INT2 pad. Default value: 0
INT2_FIFO_OVR
(0: disabled; 1: enabled)
FIFO threshold interrupt on INT2 pad. Default value: 0
INT2_FTH
(0: disabled; 1: enabled)
Temperature data-ready on INT2 pad. Default value: 0
INT2_DRDY_TEMP
(0: disabled; 1: enabled)
Gyroscope data-ready on INT2 pad. Default value: 0
INT2_DRDY_G
(0: disabled; 1: enabled)
Accelerometer data-ready on INT2 pad. Default value: 0
INT2_DRDY_XL
(0: disabled; 1: enabled)
1. Delta time value is defined in register STEP_COUNT_DELTA (15h).

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9.10 WHO_AM_I (0Fh)

Who_AM_I register (r). This register is a read-only register. Its value is fixed at 69h.

Table 41. WHO_AM_I register

0 1 1 0 1 0 0 1

9.11 CTRL1_XL (10h)

Linear acceleration sensor control register 1 (r/w).

Table 42. CTRL1_XL register

ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 FS_XL1 FS_XL0 BW_XL1 BW_XL0

Table 43. CTRL1_XL register description

ODR_XL [3:0] Output data rate and power mode selection. Default value: 0000 (see Table 44).
Accelerometer full-scale selection. Default value: 00.
FS_XL [1:0]
(00: ±2 g; 01: ±16 g; 10: ±4 g; 11: ±8 g)
Anti-aliasing filter bandwidth selection. Default value: 00
BW_XL [1:0]
(00: 400 Hz; 01: 200 Hz; 10: 100 Hz; 11: 50 Hz)

Table 44. Accelerometer ODR register setting

ODR_ ODR_ ODR_ ODR_ ODR selection [Hz] when ODR selection [Hz] when
XL3 XL2 XL1 XL0 XL_HM_MODE = 1 XL_HM_MODE = 0

0 0 0 0 Power-down Power-down
0 0 0 1 12.5 Hz (low power) 12.5 Hz (high performance)
0 0 1 0 26 Hz (low power) 26 Hz (high performance)
0 0 1 1 52 Hz (low power) 52 Hz (high performance)
0 1 0 0 104 Hz (normal mode) 104 Hz (high performance)
0 1 0 1 208 Hz (normal mode) 208 Hz (high performance)
0 1 1 0 416 Hz (high performance) 416 Hz (high performance)
0 1 1 1 833 Hz (high performance) 833 Hz (high performance)
1 0 0 0 1.66 kHz (high performance) 1.66 kHz (high performance)
1 0 0 1 3.33 kHz (high performance) 3.33 kHz (high performance)
1 0 1 0 6.66 kHz (high performance) 6.66 kHz (high performance)

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Table 45. BW and ODR (high-performance mode)

Analog filter BW (XL_HM_MODE = 0)
ODR(1)
XL_BW_SCAL_ODR = 0 XL_BW_SCAL_ODR = 1

6.66 - 3.33 kHz Filter not used

1.66 kHz 400 Hz
833 Hz 400 Hz Bandwidth is determined by
setting BW_XL[1:0] in
416 Hz 200 Hz CTRL1_XL (10h)
208 Hz 100 Hz
104 - 12.5 Hz 50 Hz
1. Filter not used when accelerometer is in normal and low-power modes.

9.12 CTRL2_G (11h)

Angular rate sensor control register 2 (r/w).

Table 46. CTRL2_G register

ODR_G3 ODR_G2 ODR_G1 ODR_G0 FS_G1 FS_G0 FS_125 0(1)
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 47. CTRL2_G register description

Gyroscope output data rate selection. Default value: 0000
ODR_G [3:0]
(Refer to Table 48)
Gyroscope full-scale selection. Default value: 00
FS_G [1:0]
(00: 250 dps; 01: 500 dps; 10: 1000 dps; 11: 2000 dps)
Gyroscope full-scale at 125 dps. Default value: 0
FS_125
(0: disabled; 1: enabled)

Table 48. Gyroscope ODR configuration setting

ODR_ ODR_ ODR_ ODR_ ODR [Hz] when ODR [Hz] when
G3 G2 G1 G0 G_HM_MODE = 1 G_HM_MODE = 0

0 0 0 0 Power down Power down

0 0 0 1 12.5 Hz (low power) 12.5 Hz (high performance)
0 0 1 0 26 Hz (low power) 26 Hz (high performance)
0 0 1 1 52 Hz (low power) 52 Hz (high performance)
0 1 0 0 104 Hz (normal mode) 104 Hz (high performance)
0 1 0 1 208 Hz (normal mode) 208 Hz (high performance)
0 1 1 0 416 Hz (high performance) 416 Hz (high performance)
0 1 1 1 833 Hz (high performance) 833 Hz (high performance)
1 0 0 0 1.66 kHz (high performance) 1.66 kHz (high performance)

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9.13 CTRL3_C (12h)

Control register 3 (r/w).

Table 49. CTRL3_C register

BOOT BDU H_LACTIVE PP_OD SIM IF_INC BLE SW_RESET

Table 50. CTRL3_C register description

BOOT Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content(1))
BDU Block Data Update. Default value: 0
(0: continuous update; 1: output registers not updated until MSB and LSB have
been read)
H_LACTIVE Interrupt activation level. Default value: 0
(0: interrupt output pads active high; 1: interrupt output pads active low)
PP_OD Push-pull/open-drain selection on INT1 and INT2 pads. Default value: 0
(0: push-pull mode; 1: open-drain mode)
SIM SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface).
IF_INC Register address automatically incremented during a multiple byte access with a
serial interface (I2C or SPI). Default value: 1
(0: disabled; 1: enabled)
BLE Big/Little Endian data selection. Default value 0
(0: data LSB @ lower address; 1: data MSB @ lower address)
SW_RESET Software reset. Default value: 0
(0: normal mode; 1: reset device)
This bit is cleared by hardware after next flash boot.
1. Boot request is executed as soon as internal oscillator is turned on. It is possible to set the bit while in
power-down mode, in this case it will be served at the next normal mode or sleep mode.

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9.14 CTRL4_C (13h)

Control register 4 (r/w).

Table 51. CTRL4_C register

XL_BW_ INT2_on_ FIFO_ DRDY_ STOP_ON
SLEEP_G I2C_disable 0(1)
SCAL_ODR INT1 TEMP_EN MASK _FTH

1. This bit must be set to ‘0’ for the correct operation of the device.

Table 52. CTRL4_C register description

XL_BW_ Accelerometer bandwidth selection. Default value: 0
SCAL_ODR (0(1): bandwidth determined by ODR selection, refer to Table 45;
1(2): bandwidth determined by setting BW_XL[1:0] in CTRL1_XL (10h) register.)
SLEEP_G Gyroscope sleep mode enable. Default value: 0
(0: disabled; 1: enabled)
INT2_on_INT1 All interrupt signals available on INT1 pad enable. Default value: 0
(0: interrupt signals divided between INT1 and INT2 pads;
1: all interrupt signals in logic or on INT1 pad)
FIFO_TEMP_EN Enable temperature data as 3rd FIFO data set(3). Default: 0
(0: disable temperature data as 3rd FIFO data set;
1: enable temperature data as 3rd FIFO data set)
DRDY_MASK Data-ready mask enable. If enabled, when switching from Power-Down to an
active mode, the accelerometer and gyroscope data-ready signals are masked
until the settling of the sensor filters is completed. Default value: 0
(0: disabled; 1: enabled)
I2C_disable Disable I2C interface. Default value: 0
(0: both I2C and SPI enabled; 1: I2C disabled, SPI only)
STOP_ON_FTH Enable FIFO threshold level use. Default value: 0.
(0: FIFO depth is not limited; 1: FIFO depth is limited to threshold level)
1. Filter used in high-performance mode only with ODR less than 3.33 kHz.
2. Filter used in high-performance mode only.
3. This bit is effective if the TIMER_PEDO_FIFO_EN bit of the FIFO_CTRL2 (07h) register is set to 0.

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9.15 CTRL5_C (14h)

Control register 5 (r/w).

Table 53. CTRL5_C register

ROUNDING2 ROUNDING1 ROUNDING0 0(1) ST1_G ST0_G ST1_XL ST0_XL
1. This bit must be set to ‘0’ for the correct operation of the device

Table 54. CTRL5_C register description

ROUNDING[2:0] Circular burst-mode (rounding) read from output registers. Default: 000
(000: no rounding; Others: refer to Table 55)
ST_G [1:0] Angular rate sensor self-test enable. Default value: 00
(00: Self-test disabled; Other: refer to Table 56)
ST_XL [1:0] Linear acceleration sensor self-test enable. Default value: 00
(00: Self-test disabled; Other: refer to Table 57)

Table 55. Output registers rounding pattern

ROUNDING[2:0] Rounding pattern

000 No rounding
001 Accelerometer only
010 Gyroscope only
011 Gyroscope + accelerometer

Table 56. Angular rate sensor self-test mode selection

ST1_G ST0_G Self-test mode

0 0 Normal mode
0 1 Positive sign self-test
1 0 Not allowed
1 1 Negative sign self-test

Table 57. Linear acceleration sensor self-test mode selection

ST1_XL ST0_XL Self-test mode

0 0 Normal mode
0 1 Positive sign self-test
1 0 Negative sign self-test
1 1 Not allowed

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9.16 CTRL6_C (15h)

Angular rate sensor control register 6 (r/w).

Table 58. CTRL6_C register

TRIG_EN LVLen LVL2_EN XL_HM_MODE 0(1) 0(1) 0(1) 0(1)
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 59. CTRL6_C register description

Gyroscope data edge-sensitive trigger enable. Default value: 0
TRIG_EN
(0: external trigger disabled; 1: external trigger enabled)
Gyroscope data level-sensitive trigger enable. Default value: 0
LVLen
(0: level-sensitive trigger disabled; 1: level sensitive trigger enabled)
Gyroscope level-sensitive latched enable. Default value: 0
LVL2_EN
(0: level-sensitive latched disabled; 1: level sensitive latched enabled)
High-performance operating mode disable for accelerometer(1). Default value: 0
XL_HM_MODE (0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
1. Normal and low-power mode depends on the ODR setting, for details refer to Table 44.

9.17 CTRL7_G (16h)

Angular rate sensor control register 7 (r/w).

Table 60. CTRL7_G register

HP_G_ HP_G_R ROUNDING_
G_HM_MODE HPCF_G1 HPCF_G0 0(1) 0(1)
EN ST STATUS
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 61. CTRL7_G register description

High-performance operating mode disable for gyroscope(1). Default: 0
G_HM_MODE (0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
Gyroscope digital high-pass filter enable. The filter is enabled only if the gyro is in HP
HP_G_EN mode. Default value: 0
(0: HPF disabled; 1: HPF enabled)
Gyro digital HP filter reset. Default: 0
HP_G_RST
(0: gyro digital HP filter reset OFF; 1: gyro digital HP filter reset ON)
Source register rounding function enable on STATUS_REG (1Eh), FUNC_SRC
ROUNDING_ (53h) and WAKE_UP_SRC (1Bh) registers. Default value: 0
STATUS
(0: disabled; 1: enabled)
Gyroscope high-pass filter cutoff frequency selection. Default value: 00.
HPCF_G[1:0]
Refer to Table 62.
1. Normal and low-power mode depends on the ODR setting, for details refer to Table 48.

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Table 62. Gyroscope high-pass filter mode configuration

HPCF_G1 HPCF_G0 High-pass filter cutoff frequency

0 0 0.0081 Hz
0 1 0.0324 Hz
1 0 2.07 Hz
1 1 16.32 Hz

9.18 CTRL8_XL (17h)

Linear acceleration sensor control register 8 (r/w).

Table 63. CTRL8_XL register

LPF2_XL_ HPCF_ HPCF_ HP_SLOPE_X LOW_PASS
0(1) 0(1) 0(1)
EN XL1 XL0 L_EN _ON_6D
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 64. CTRL8_XL register description

LPF2_XL_EN Accelerometer low-pass filter LPF2 selection. Refer to Figure 5.
Accelerometer slope filter and high-pass filter configuration and cutoff
HPCF_XL[1:0]
setting. Refer to Table 65.
HP_SLOPE_XL_EN Accelerometer slope filter / high-pass filter selection. Refer to Figure 5.
LOW_PASS_ON_6D Low-pass filter on 6D function selection. Refer to Figure 5.

Table 65. Accelerometer slope and high-pass filter selection and cutoff frequency
HPCF_XL[1:0] Applied filter HP filter cutoff frequency [Hz]

00 Slope ODR_XL/50
01 High-pass ODR_XL/100
10 High-pass ODR_XL/9
11 High-pass ODR_XL/400

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9.19 CTRL9_XL (18h)

Linear acceleration sensor control register 9 (r/w).

Table 66. CTRL9_XL register

(1) (1)
0 0 Zen_XL Yen_XL Xen_XL 0(1) 0(1) 0(1)
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 67. CTRL9_XL register description

Accelerometer Z-axis output enable. Default value: 1
Zen_XL
(0: Z-axis output disabled; 1: Z-axis output enabled)
Accelerometer Y-axis output enable. Default value: 1
Yen_XL
(0: Y-axis output disabled; 1: Y-axis output enabled)
Accelerometer X-axis output enable. Default value: 1
Xen_XL
(0: X-axis output disabled; 1: X-axis output enabled)

9.20 CTRL10_C (19h)

Control register 10 (r/w).

Table 68. CTRL10_C register

PEDO_RST SIGN_
0(1) 0(1) Zen_G Yen_G Xen_G FUNC_EN
_STEP MOTION_EN
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 69. CTRL10_C register description

Gyroscope yaw axis (Z) output enable. Default value: 1
Zen_G
(0: Z-axis output disabled; 1: Z-axis output enabled)
Gyroscope roll axis (Y) output enable. Default value: 1
Yen_G
(0: Y-axis output disabled; 1: Y-axis output enabled)
Gyroscope pitch axis (X) output enable. Default value: 1
Xen_G
(0: X-axis output disabled; 1: X-axis output enabled)
Enable embedded functionalities (pedometer, tilt, significant motion) and
accelerometer HP and LPF2 filters (refer to Figure 5). Default value: 0
FUNC_EN
(0: disable functionalities of embedded functions and accelerometer filters;
1: enable functionalities of embedded functions and accelerometer filters)

PEDO_RST_ Reset pedometer step counter. Default value: 0

STEP (0: disabled; 1: enabled)

SIGN_MOTION Enable significant motion function. Default value: 0

_EN (0: disabled; 1: enabled)

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9.21 WAKE_UP_SRC (1Bh)

Wake up interrupt source register (r).

Table 70. WAKE_UP_SRC register

SLEEP_
0(1) 0(1) FF_IA WU_IA X_WU Y_WU Z_WU
STATE_IA
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 71. WAKE_UP_SRC register description

Free-fall event detection status. Default: 0
FF_IA
(0: free-fall event not detected; 1: free-fall event detected)
SLEEP_ Sleep event status. Default value: 0
STATE_IA (0: sleep event not detected; 1: sleep event detected)
Wakeup event detection status. Default value: 0
WU_IA
(0: wakeup event not detected; 1: wakeup event detected.)
Wakeup event detection status on X-axis. Default value: 0
X_WU
(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)
Wakeup event detection status on Y-axis. Default value: 0
Y_WU
(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)
Wakeup event detection status on Z-axis. Default value: 0
Z_WU
(0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected)

9.22 TAP_SRC (1Ch)

Tap source register (r).

Table 72. TAP_SRC register

SINGLE_ DOUBLE_
0(1) TAP_IA TAP_SIGN X_TAP Y_TAP Z_TAP
TAP TAP
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 73. TAP_SRC register description

Tap event detection status. Default: 0
TAP_IA
(0: tap event not detected; 1: tap event detected)
Single-tap event status. Default value: 0
SINGLE_TAP
(0: single tap event not detected; 1: single tap event detected)
Double-tap event detection status. Default value: 0
DOUBLE_TAP
(0: double-tap event not detected; 1: double-tap event detected.)
Sign of acceleration detected by tap event. Default: 0
TAP_SIGN (0: positive sign of acceleration detected by tap event;
1: negative sign of acceleration detected by tap event)
Tap event detection status on X-axis. Default value: 0
X_TAP
(0: tap event on X-axis not detected; 1: tap event on X-axis detected)
Tap event detection status on Y-axis. Default value: 0
Y_TAP
(0: tap event on Y-axis not detected; 1: tap event on Y-axis detected)
Tap event detection status on Z-axis. Default value: 0
Z_TAP
(0: tap event on Z-axis not detected; 1: tap event on Z-axis detected)

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9.23 D6D_SRC (1Dh)

Portrait, landscape, face-up and face-down source register (r)

Table 74. D6D_SRC register

0(1) D6D_IA ZH ZL YH YL XH XL
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 75. D6D_SRC register description

D6D_ Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0
IA (0: change position not detected; 1: change position detected)
Z-axis high event (over threshold). Default value: 0
ZH
(0: event not detected; 1: event (over threshold) detected)
Z-axis low event (under threshold). Default value: 0
ZL
(0: event not detected; 1: event (under threshold) detected)
Y-axis high event (over threshold). Default value: 0
YH
(0: event not detected; 1: event (over-threshold) detected)
Y-axis low event (under threshold). Default value: 0
YL
(0: event not detected; 1: event (under threshold) detected)
X-axis high event (over threshold). Default value: 0
X_H
(0: event not detected; 1: event (over threshold) detected)
X-axis low event (under threshold). Default value: 0
X_L
(0: event not detected; 1: event (under threshold) detected)

9.24 STATUS_REG (1Eh)

Table 76. STATUS_REG register

- - - - - TDA GDA XLDA

Table 77. STATUS_REG register description

Temperature new data available. Default: 0
TDA (0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
Gyroscope new data available. Default value: 0
GDA (0: no set of data available at gyroscope output;
1: a new set of data is available at gyroscope output)
Accelerometer new data available. Default value: 0
XLDA (0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)

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9.25 OUT_TEMP_L (20h), OUT_TEMP(21h)

Temperature data output register (r). L and H registers together express a 16-bit word in two’s
complement (r).

Table 78. OUT_TEMP_L register

Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0

Table 79. OUT_TEMP_H register

Temp15 Temp14 Temp13 Temp12 Temp11 Temp10 Temp9 Temp8

Table 80. OUT_TEMP register description

Temperature sensor output data
Temp[15:0]
The value is expressed as two’s complement sign extended on the MSB.

9.26 OUTX_L_G (22h)

Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit
word in two’s complement. (r)

Table 81. OUTX_L_G register

D7 D6 D5 D4 D3 D2 D1 D0

Table 82. OUTX_L_G register description

D[7:0] Pitch axis (X) angular rate value (LSbyte)

9.27 OUTX_H_G (23h)

Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit
word in two’s complement. (r)

Table 83. OUTX_H_G register

D15 D14 D13 D12 D11 D10 D9 D8

Table 84. OUTX_H_G register description

D[15:8] Pitch axis (X) angular rate value (MSbyte)

9.28 OUTY_L_G (24h)

Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit
word in two’s complement. (r).

Table 85. OUTY_L_G register

D7 D6 D5 D4 D3 D2 D1 D0

Table 86. OUTY_L_G register description

D[7:0] Roll axis (Y) angular rate value (LSbyte)

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9.29 OUTY_H_G (25h)

Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit
word in two’s complement. (r).

Table 87. OUTY_H_G register

D15 D14 D13 D12 D11 D10 D9 D8

Table 88. OUTY_H_G register description

D[15:8] Roll axis (Y) angular rate value (MSbyte)

9.30 OUTZ_L_G (26h)

Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit
word in two’s complement. (r).

Table 89. OUTZ_L_G register

D7 D6 D5 D4 D3 D2 D1 D0

Table 90. OUTZ_L_G register description

D[7:0] Yaw axis (Z) angular rate value (LSbyte)

9.31 OUTZ_H_G (27h)

Angular rate sensor Yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit
word in two’s complement.

Table 91. OUTZ_H_G register

D15 D14 D13 D12 D11 D10 D9 D8

Table 92. OUTZ_H_G register description

D[15:8] Yaw axis (Z) angular rate value (MSbyte)

9.32 OUTX_L_XL (28h)

Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.

Table 93. OUTX_L_XL register

D7 D6 D5 D4 D3 D2 D1 D0

Table 94. OUTX_L_XL register description

D[7:0] X-axis linear acceleration value (LSbyte)

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9.33 OUTX_H_XL (29h)

Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.

Table 95. OUTX_H_XL register

D15 D14 D13 D12 D11 D10 D9 D8

Table 96. OUTX_H_XL register description

D[15:8] X-axis linear acceleration value (MSbyte)

9.34 OUTY_L_XL (2Ah)

Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.

Table 97. OUTY_L_XL register

D7 D6 D5 D4 D3 D2 D1 D0

Table 98. OUTY_L_XL register description

D[7:0] Y-axis linear acceleration value (LSbyte)

9.35 OUTY_H_XL (2Bh)

Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.

Table 99. OUTY_H_G register

D15 D14 D13 D12 D11 D10 D9 D8

Table 100. OUTY_H_G register description

D[15:8] Y-axis linear acceleration value (MSbyte)

9.36 OUTZ_L_XL (2Ch)

Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.

Table 101. OUTZ_L_XL register

D7 D6 D5 D4 D3 D2 D1 D0

Table 102. OUTZ_L_XL register description

D[7:0] Z-axis linear acceleration value (LSbyte)

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9.37 OUTZ_H_XL (2Dh)

Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.

Table 103. OUTZ_H_XL register

D15 D14 D13 D12 D11 D10 D9 D8

Table 104. OUTZ_H_XL register description

D[15:8] Z-axis linear acceleration value (MSbyte)

9.38 FIFO_STATUS1 (3Ah)

FIFO status control register (r). For a proper reading of the register, it is recommended to set the
BDU bit in CTRL3_C (12h) to 1.

Table 105. FIFO_STATUS1 register

DIFF_ DIFF_ DIFF_ DIFF_ DIFF_ DIFF_ DIFF_ DIFF_
FIFO_7 FIFO_6 FIFO_5 FIFO_4 FIFO_3 FIFO_2 FIFO_1 FIFO_0

Table 106. FIFO_STATUS1 register description

DIFF_FIFO_[7:0] Number of unread words (16-bit axes) stored in FIFO(1).
1. For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS2 (3Bh)

9.39 FIFO_STATUS2 (3Bh)

FIFO status control register (r). For a proper reading of the register, it is recommended to set the
BDU bit in CTRL3_C (12h) to 1.

Table 107. FIFO_STATUS2 register

FIFO_ FIFO_ FIFO_ DIFF_ DIFF_ DIFF_ DIFF_
FTH
OVER_RUN FULL EMPTY FIFO_11 FIFO_10 FIFO_9 FIFO_8

Table 108. FIFO_STATUS2 register description

FTH FIFO watermark status. Default value: 0
(0: FIFO filling is lower than watermark level(1);
1: FIFO filling is equal to or higher than the watermark level)
FIFO_OVER_RUN FIFO overrun status. Default value: 0
(0: FIFO is not completely filled; 1: FIFO is completely filled)
FIFO_FULL FIFO full status. Default value: 0
(0: FIFO is not full; 1: FIFO will be full at the next ODR)
FIFO_EMPTY FIFO empty bit. Default value: 0
(0: FIFO contains data; 1: FIFO is empty)
DIFF_FIFO_[7:0] Number of unread words (16-bit axes) stored in FIFO(2).
1. FIFO watermark level is set in FTH_[11:0] in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)
2. For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS1 (3Ah)

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9.40 FIFO_STATUS3 (3Ch)

FIFO status control register (r). For a proper reading of the register, it is recommended to set the
BDU bit in CTRL3_C (12h) to 1.

Table 109. FIFO_STATUS3 register

FIFO_ FIFO_ FIFO_ FIFO_ FIFO_ FIFO_ FIFO_ FIFO_
PATTERN PATTERN PATTERN PATTERN PATTERN PATTERN PATTERN PATTERN
_7 _6 _5 _4 _3 _2 _1 _0

Table 110. FIFO_STATUS3 register description

FIFO_
Word of recursive pattern read at the next reading.
PATTERN_[7:0]

9.41 FIFO_STATUS4 (3Dh)

FIFO status control register (r). For a proper reading of the register, it is recommended to set the
BDU bit in CTRL3_C (12h) to 1.

Table 111. FIFO_STATUS4 register

FIFO_ FIFO_
0(1) 0(1) 0(1) 0(1) 0(1) 0(1)
PATTERN_9 PATTERN_8
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 112. FIFO_STATUS4 register description

FIFO_
Word of recursive pattern read at the next reading.
PATTERN_[9:8]

9.42 FIFO_DATA_OUT_L (3Eh)

FIFO data output register (r). For a proper reading of the register, it is recommended to set the BDU bit
in CTRL3_C (12h) to 1.

Table 113. FIFO_DATA_OUT_L register

DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_
OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_
FIFO_L_7 FIFO_L_6 FIFO_L_5 FIFO_L_4 FIFO_L_3 FIFO_L_2 FIFO_L_1 FIFO_L_0

Table 114. FIFO_DATA_OUT_L register description

DATA_OUT_FIFO_L_[7:0] FIFO data output (first byte)

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9.43 FIFO_DATA_OUT_H (3Fh)

FIFO data output register (r). For a proper reading of the register, it is recommended to set the BDU bit
in CTRL3_C (12h) to 1.

Table 115. FIFO_DATA_OUT_H register

DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_
OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_
FIFO_H_7 FIFO_H_6 FIFO_H_5 FIFO_H_4 FIFO_H_3 FIFO_H_2 FIFO_H_1 FIFO_H_0

Table 116. FIFO_DATA_OUT_H register description

DATA_OUT_FIFO_H_[7:0] FIFO data output (second byte)

9.44 TIMESTAMP0_REG (40h)

Timestamp first byte data output register (r). The value is expressed as a 24-bit word and the bit
resolution is defined by setting the value in WAKE_UP_DUR (5Ch).

Table 117. TIMESTAMP0_REG register

TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA
MP0_7 MP0_6 MP0_5 MP0_4 MP0_3 MP0_2 MP0_1 MP0_0

Table 118. TIMESTAMP0_REG register description

TIMESTAMP0_[7:0] TIMESTAMP first byte data output

9.45 TIMESTAMP1_REG (41h)

Timestamp second byte data output register (r). The value is expressed as a 24-bit word and the bit
resolution is defined by setting value in WAKE_UP_DUR (5Ch).

Table 119. TIMESTAMP1_REG register

TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA
MP1_7 MP1_6 MP1_5 MP1_4 MP1_3 MP1_2 MP1_1 MP1_0

Table 120. TIMESTAMP1_REG register description

TIMESTAMP1_[7:0] TIMESTAMP second byte data output

9.46 TIMESTAMP2_REG (42h)

Timestamp third byte data output register (r/w). The value is expressed as a 24-bit word and the bit
resolution is defined by setting the value in WAKE_UP_DUR (5Ch). To reset the timer, the AAh value
has to be stored in this register.

Table 121. TIMESTAMP2_REG register

TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA
MP2_7 MP2_6 MP2_5 MP2_4 MP2_3 MP2_2 MP2_1 MP2_0

Table 122. TIMESTAMP2_REG register description

TIMESTAMP2_[7:0] TIMESTAMP third byte data output

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9.47 STEP_TIMESTAMP_L (49h)

Step counter timestamp information register (r). When a step is detected, the value of
TIMESTAMP_REG1 register is copied in STEP_TIMESTAMP_L.

Table 123. STEP_TIMESTAMP_L register

STEP_ STEP_ STEP_ STEP_ STEP_ STEP_ STEP_ STEP_
TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA
MP_L_7 MP_L_6 MP_L_5 MP_L_4 MP_L_3 MP_L_2 MP_L_1 MP_L_0

Table 124. STEP_TIMESTAMP_L register description

STEP_TIMESTAMP_L[7:0] Timestamp of last step detected.

9.48 STEP_TIMESTAMP_H (4Ah)

Step counter timestamp information register (r). When a step is detected, the value of
TIMESTAMP_REG2 register is copied in STEP_TIMESTAMP_H.

Table 125. STEP_TIMESTAMP_H register

STEP_ STEP_ STEP_ STEP_ STEP_ STEP_ STEP_ STEP_
TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA TIMESTA
MP_H_7 MP_H_6 MP_H_5 MP_H_4 MP_H_3 MP_H_2 MP_H_1 MP_H_0

Table 126. STEP_TIMESTAMP_H register description

STEP_TIMESTAMP_H[7:0] Timestamp of last step detected.

9.49 STEP_COUNTER_L (4Bh)

Step counter output register (r).

Table 127. STEP_COUNTER_L register

STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO
UNTER_L UNTER_L UNTER_L UNTER_L UNTER_L UNTER_L UNTER_L UNTER_L
_7 _6 _5 _4 _3 _2 _1 _0

Table 128. STEP_COUNTER_L register description

STEP_COUNTER_L_[7:0] Step counter output (LSbyte)

9.50 STEP_COUNTER_H (4Ch)

Step counter output register (r).

Table 129. STEP_COUNTER_H register

STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO
UNTER_H UNTER_H UNTER_H UNTER_H UNTER_H UNTER_H UNTER_H UNTER_H
_7 _6 _5 _4 _3 _2 _1 _0

Table 130. STEP_COUNTER_H register description

STEP_COUNTER_H_[7:0] Step counter output (MSbyte)

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9.51 FUNC_SRC (53h)

Significant motion, tilt, step detector interrupt source register (r).

Table 131. FUNC_SRC register

STEP_COUNT_ SIGN_ STEP_ STEP_
TILT_IA 0 0 0
DELTA_IA MOTION_IA DETECTED OVERFLOW

Table 132. FUNC_SRC register description

Pedometer step recognition on delta time status. Default value: 0
STEP_COUNT
(0: no step recognized during delta time; 1: at least one step recognized during
_DELTA_IA
delta time)
SIGN_ Significant motion event detection status. Default value: 0
MOTION_IA (0: significant motion event not detected; 1: significant motion event detected)
Tilt event detection status. Default value: 0
TILT_IA
(0: tilt event not detected; 1: tilt event detected)
STEP_ Step detector event detection status. Default value: 0
DETECTED (0: step detector event not detected; 1: step detector event detected)
STEP_ Step counter overflow status. Default value: 0
OVERFLOW (0: step counter value < 216; 1: step counter value reached 216)

9.52 TAP_CFG (58h)

Timestamp, pedometer, tilt, filtering, and tap recognition functions configuration register
(r/w).

Table 133. TAP_CFG register

TIMER_ SLOPE
PEDO_EN TILT_EN TAP_X_EN TAP_Y_EN TAP_Z_EN LIR
EN _FDS

Table 134. TAP_CFG register description

Timestamp count enable, output data are collected in TIMESTAMP0_REG (40h),
TIMER_EN TIMESTAMP1_REG (41h), TIMESTAMP2_REG (42h) register. Default: 0
(0: timestamp count disabled; 1: timestamp count enabled)
Pedometer algorithm enable. Default value: 0
PEDO_EN
(0: pedometer algorithm disabled; 1: pedometer algorithm enabled)
Tilt calculation enable. Default value: 0
TILT_EN
(0: tilt calculation disabled; 1: tilt calculation enabled.)
Enable accelerometer HP and LPF2 filters (refer to Figure 5). Default value: 0
SLOPE_FDS
(0: disable; 1: enable)
Enable X direction in tap recognition. Default value: 0
TAP_X_EN
(0: X direction disabled; 1:X direction enabled)
Enable Y direction in tap recognition. Default value: 0
TAP_Y_EN
(0: Y direction disabled; 1:Y direction enabled)
Enable Z direction in tap recognition. Default value: 0
TAP_Z_EN
(0: Z direction disabled; 1: Z direction enabled)
Latched Interrupt. Default value: 0
LIR
(0: interrupt request not latched; 1: interrupt request latched)

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9.53 TAP_THS_6D (59h)

Portrait/landscape position and tap function threshold register (r/w).

Table 135. TAP_THS_6D register

SIXD_THS SIXD_THS TAP_THS TAP_THS TAP_THS TAP_THS TAP_THS
D4D_EN
1 0 4 3 2 1 0

Table 136. TAP_THS_6D register description

4D orientation detection enable (Z-axis position detection is disabled).
D4D_EN Default value: 0
(0: disabled; 1: enabled)
Threshold for D6D function. Default value: 00
SIXD_THS[1:0]
For details, refer to Table 137.
TAP_THS[4:0] Threshold for tap recognition. Default value: 00000

Table 137. Threshold for D4D/D6D function

SIXD_THS[1:0] Threshold value
00 80 degrees
01 70 degrees
10 60 degrees
11 50 degrees

9.54 INT_DUR2 (5Ah)

Tap recognition function setting register (r/w).

Table 138. INT_DUR2 register

DUR3 DUR2 DUR1 DUR0 QUIET1 QUIET0 SHOCK1 SHOCK0

Table 139. INT_DUR2 register description

Duration of maximum time gap for double tap recognition. Default: 0000
When double tap recognition is enabled, this register expresses the maximum time
DUR[3:0] between two consecutive detected taps to determine a double tap event. The
default value of these bits is 0000b which corresponds to 16*ODR_XL time. If
DUR[3:0] bits are set to a different value, 1LSB corresponds to 32*ODR_XL time.
Expected quiet time after a tap detection. Default value: 00
Quiet time is the time after the first detected tap in which there must not be any
QUIET[1:0] overthreshold event. The default value of these bits is 00b which corresponds to
2*ODR_ time. If QUIET[1:0] bits are set to a different value, 1LSB corresponds to
4*ODR_time.
Maximum duration of overthreshold event. Default value: 00
Maximum duration is the maximum time of an overthreshold signal detection to be
SHOCK[1:0] recognized as a tap event. The default value of these bits is 00b which corresponds
to 4*ODR_ time. If SHOCK[1:0] bits are set to a different value, 1LSB corresponds
to 8*ODR_time.

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9.55 WAKE_UP_THS (5Bh)

Single and double-tap function threshold register (r/w).

Table 140. WAKE_UP_THS register

SINGLE_
DOUBLE INACTIVITY WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0
_TAP

Table 141. WAKE_UP_THS register description

Single/double-tap event enable. Default: 0
SINGLE_DOUBLE_TAP (0: only single-tap event enabled;
1: both single and double-tap events enabled)
Inactivity event enable. Default value: 0
INACTIVITY
(0: sleep disabled; 1: sleep enabled)
WK_THS[5:0] Threshold for wakeup. Default value: 000000

9.56 WAKE_UP_DUR (5Ch)

Free-fall, wakeup, timestamp and sleep mode functions duration setting register (r/w).

Table 142. WAKE_UP_DUR register

WAKE_ WAKE_ TIMER_ SLEEP_ SLEEP_ SLEEP_ SLEEP_
FF_DUR5
DUR1 DUR0 HR DUR3 DUR2 DUR1 DUR0

Table 143. WAKE_UP_DUR register description

Free fall duration event. Default: 0
FF_DUR5 For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in
FREE_FALL (5Dh) configuration.
Wake up duration event. Default: 00
WAKE_DUR[1:0]
1LSB = 1 ODR_time
Timestamp register resolution setting(1). Default value: 0
TIMER_HR
(0: 1LSB = 6.4 ms; 1: 1LSB = 25 μs)
Duration to go in sleep mode. Default value: 0000
SLEEP_DUR[3:0]
1 LSB = 512 ODR
1. Configuration of this bit affects TIMESTAMP0_REG (40h), TIMESTAMP1_REG (41h),
TIMESTAMP2_REG (42h), STEP_TIMESTAMP_L (49h), STEP_TIMESTAMP_H (4Ah), and
STEP_COUNT_DELTA (15h) registers.

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9.57 FREE_FALL (5Dh)

Free-fall function duration setting register (r/w).

Table 144. FREE_FALL register

FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0

Table 145. FREE_FALL register description

Free-fall duration event. Default: 0
FF_DUR[4:0] For the complete configuration of the free fall duration, refer to FF_DUR5 in
WAKE_UP_DUR (5Ch) configuration
Free fall threshold setting. Default: 000
FF_THS[2:0]
For details refer to Table 146.

Table 146. Threshold for free-fall function

FF_THS[2:0] Threshold value
000 156 mg
001 219 mg
010 250 mg
011 312 mg
100 344 mg
101 406 mg
110 469 mg
111 500 mg

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9.58 MD1_CFG (5Eh)

Functions routing on INT1 register (r/w).

Table 147. MD1_CFG register

INT1_ INT1_ INT1_
INT1_
INACT_ SINGLE_ INT1_WU INT1_FF DOUBLE_ INT1_6D INT1_TILT
TIMER
STATE TAP TAP

Table 148. MD1_CFG register description

INT1_INACT_ Routing on INT1 of inactivity mode. Default: 0
STATE (0: routing on INT1 of inactivity disabled; 1: routing on INT1 of inactivity enabled)
Single-tap recognition routing on INT1. Default: 0
INT1_SINGLE_
(0: routing of single-tap event on INT1 disabled;
TAP
1: routing of single-tap event on INT1 enabled)
Routing of wakeup event on INT1. Default value: 0
INT1_WU (0: routing of wakeup event on INT1 disabled;
1: routing of wakeup event on INT1 enabled)
Routing of free-fall event on INT1. Default value: 0
INT1_FF (0: routing of free-fall event on INT1 disabled;
1: routing of free-fall event on INT1 enabled)
Routing of tap event on INT1. Default value: 0
INT1_DOUBLE
(0: routing of double-tap event on INT1 disabled;
_TAP
1: routing of double-tap event on INT1 enabled)
Routing of 6D event on INT1. Default value: 0
INT1_6D
(0: routing of 6D event on INT1 disabled; 1: routing of 6D event on INT1 enabled)
Routing of tilt event on INT1. Default value: 0
INT1_TILT
(0: routing of tilt event on INT1 disabled; 1: routing of tilt event on INT1 enabled)
Routing of end counter event of timer on INT1. Default value: 0
INT1_TIMER (0: routing of end counter event of timer on INT1 disabled;
1: routing of end counter event of timer event on INT1 enabled)

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9.59 MD2_CFG (5Fh)

Functions routing on INT2 register (r/w).

Table 149. MD2_CFG register

INT2_ INT2_ INT2_
INACT_ SINGLE_ INT2_WU INT2_FF DOUBLE_ INT2_6D INT2_TILT 0(1)
STATE TAP TAP
1. This bit must be set to ‘0’ for the correct operation of the device.

Table 150. MD2_CFG register description

INT2_INACT_ Routing on INT2 of inactivity mode. Default: 0
STATE (0: routing on INT2 of inactivity disabled; 1: routing on INT2 of inactivity enabled)
Single-tap recognition routing on INT2. Default: 0
INT2_SINGLE_
(0: routing of single-tap event on INT2 disabled;
TAP
1: routing of single-tap event on INT2 enabled)
Routing of wakeup event on INT2. Default value: 0
INT2_WU (0: routing of wakeup event on INT2 disabled;
1: routing of wake-up event on INT2 enabled)
Routing of free-fall event on INT2. Default value: 0
INT2_FF (0: routing of free-fall event on INT2 disabled;
1: routing of free-fall event on INT2 enabled)
Routing of tap event on INT2. Default value: 0
INT2_DOUBLE
(0: routing of double-tap event on INT2 disabled;
_TAP
1: routing of double-tap event on INT2 enabled)
Routing of 6D event on INT2. Default value: 0
INT2_6D
(0: routing of 6D event on INT2 disabled; 1: routing of 6D event on INT2 enabled)
Routing of tilt event on INT2. Default value: 0
INT2_TILT
(0: routing of tilt event on INT2 disabled; 1: routing of tilt event on INT2 enabled)

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10 Embedded functions register mapping

The table given below provides a list of the registers for the embedded functions avaialble in
the device and the corresponding addresses. Embedded functions registers are accessible
when FUNC_CFG_EN is set to ‘1’ in FUNC_CFG_ACCESS (01h).
Note: All modifications of the content of the embedded functions registers have to be performed
with the device in power-down mode.

Table 151. Registers address map - embedded functions

Register address
Name Type Default Comment
Hex Binary

RESERVED - 02-0E Reserved

PEDO_THS_REG r/w 0F 00001111 00010000
RESERVED - 10-12 Reserved
SM_THS r/w 13 00010011 00000110
PEDO_DEB_REG r/w 14 00010100 01101110
STEP_COUNT_DELTA r/w 15 0001 0101 00000000
RESERVED - 24-32 Reserved

Registers marked as Reserved must not be changed. Writing to those registers may cause
permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.

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11 Embedded functions registers description

Note: All modifications of the content of the embedded functions registers have to be performed
with the device in power-down mode.

11.1 PEDO_THS_REG (0Fh)

Pedometer minimum threshold and internal full-scale configuration register (r/w).

Table 152. PEDO_THS_REG register

THS_ THS_ THS_ THS_ THS_
PEDO_4G - -
MIN4 MIN3 MIN2 MIN1 MIN0

Table 153. PEDO_THS_REG register description

This bit sets the internal full scale used in pedometer functions. Using this bit,
saturation is avoided (e.g. FAST walk).
PEDO_ 4G 0: internal full scale = 2 g.
1: internal full scale 4 g (device full_scale @CTRL1_XL must be ≥ 4 g, otherwise
internal full scale is 2 g)
Configurable minimum threshold. 1LSB = 16 mg @PEDO_4G=0, 1LSB = 32 mg
THS_ MIN[4:0]
@PEDO_4G=1

11.2 SM_THS (13h)

Significant motion configuration register (r/w).

Table 154. SM_THS register

SM_THS_ SM_THS_ SM_THS_ SM_THS_ SM_THS_ SM_THS_ SM_THS_ SM_THS_
7 6 5 4 3 2 1 0

Table 155. SM_THS register description

SM_THS[7:0] Significant motion threshold. Default value: 00000110

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11.3 PEDO_DEB_REG (14h)

Pedometer debounce configuration register (r/w).

Table 156. PEDO_DEB_REG register

DEB_ DEB_ DEB_ DEB_ DEB_ DEB_ DEB_ DEB_
TIME4 TIME3 TIME2 TIME1 TIME0 STEP2 STEP1 STEP0

Table 157. PEDO_DEB_REG register description

Debounce time. If the time between two consecutive steps is greater than
DEB_ TIME[4:0]
DEB_TIME*80ms, the debouncer is reactivated. Default value: 01101
Debounce threshold. Minimum number of steps to increment the step counter
DEB_ STEP[2:0]
(debounce). Default value: 110

11.4 STEP_COUNT_DELTA (15h)

Time period register for step detection on delta time (r/w).

Table 158. STEP_COUNT_DELTA register

SC_ SC_ SC_ SC_ SC_ SC_ SC_ SC_
DELTA_7 DELTA_6 DELTA_5 DELTA_4 DELTA_3 DELTA_2 DELTA_1 DELTA_0

Table 159. STEP_COUNT_DELTA register description

SC_DELTA[7:0] Time period value(1) (1LSB = 1.6384 s)
1. This value is effective if the TIMER_EN bit of the TAP_CFG (58h) register is set to 1 and the TIMER_HR
bit of the WAKE_UP_DUR (5Ch) register is set to 0.

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LSM6DS33 Soldering information

12 Soldering information

The LGA package is compliant with the ECOPACK®, RoHS and "Green" standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave "Pin 1 Indicator" unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com/mems.

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Package information LSM6DS33

13 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

13.1 LGA-16 package information

Figure 16. LGA 3x3x0.86 16L package outline and dimensions

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13.2 LGA-16 packing information

Figure 17. Carrier tape information for LGA-16 package

Figure 18. LGA-16 package orientation in carrier tape

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Package information LSM6DS33

Figure 19. Reel information for carrier tape of LGA-16 package

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Table 160. Reel dimensions for carrier tape of LGA-16 package

Reel dimensions (mm)

A (max) 330
B (min) 1.5
C 13 ±0.25
D (min) 20.2
N (min) 60
G 12.4 +2/-0
T (max) 18.4

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LSM6DS33 Revision history

14 Revision history

Table 161. Document revision history

Date Revision Changes

18-Feb-2015 1 Initial release

17-Jul-2015 2 Updated registers in Section 9: Register description
27-Jul-2015 3 First public release
Updated package representation on page 1
09-Oct-2015 4 Added PEDO_THS_REG (0Fh) and PEDO_DEB_REG (14h)
Added Section 13.2: LGA-16 packing information
Updated Table 2: Pin description
Updated Table 3: Mechanical characteristics
Updated Table 8: Absolute maximum ratings
11-Jan-2017 5 Updated Figure 5: Accelerometer composite filter
Updated Section 9: Register description
Updated Section 10: Embedded functions register mapping and Section 11:
Embedded functions registers description
Specified SPI mode 3 in Section 4.4.1: SPI - serial peripheral interface and throughout
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